[PowerPC] Exploit xxperm, check for dead vectors and substitute vperm with xxperm

[maryammo]

Summary

vperm instruction requires the data to be in the Altivec registers, if one of
the vector operands is not used after this vperm instruction then it can be
substituted by xxperm which doubles the number of available registers.

[maryammo]

NFC

[maryammo]

NFC

[amyk]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

10191

I assume this is meant to be deleted?

10206

Minor nit.

10209

Can we elaborate why we want V2 as the destination?

10217

nit: XSWAP -> XXSWAPD maybe to match the actual opcode?

10235

nit: IE->i.e.
Can we also put a space after each i.e. to view the illustration better?

10287

Might be good to pull isPPC64() into a separate variable like how you did for isLittleEndian.

llvm/lib/Target/PowerPC/PPCInstrVSX.td

119

nit: Put SDT_PPCxxperm near the beginning of the file nearby the other SDT* definitions.

[amyk]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

10209

Thanks for bringing this up with me again.
I think I misunderstood or read this incorrectly at the time, so you can probably disregard the comment regarding the elaboration.

[maryammo]

Address review comments

[amyk]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

10217

nit: Update the names?

10235

nit: Could we add a space after each i.e. to view the illustration better?

10281

Do we mean to get V2->getOperand(0) here?

10301

Isn't V1.getValueType() here just ValType?

[maryammo]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

10301

V1.getValueType() is the current valueType for V1 while ValType is the original one. (there are possible bitcasts)

[maryammo]

Address review comments

[stefanp]

Thank you for your patience and sorry it took me so long to get to this.

I have a bunch of comments but most of them are not a big deal and a couple of them don't require action at all it's just something that's important to notice.
Overall I think that the patch makes sense and hopefully after this round of changes we will be ready to put it in.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

10177

Is VPermMask used anymore other than the LLVM_DEBUG?

If it's not this line will cause a warning, or error with -Werror, when the LLVM_DEBUG is removed in some builds.

It looks to me like the whole for loop starting on line 10163 might be redundant as you do the same thing above and in LowerVPERM.
You may want to restructure the code so that you have

if (Subtarget.isISA3_0() && (V1->hasOneUse() || V2->hasOneUse())) {
  // Do the codegen with XXPERM here
  LLVM_DEBUG(dbgs() << "Emitting a VPERM for the following shuffle:\n");
  LLVM_DEBUG(SVOp->dump());
  LLVM_DEBUG(dbgs() << "With the following permute control vector:\n");
  LLVM_DEBUG(VPermMask.dump());
} else {
  // Do the codegen with VPERM here
  LLVM_DEBUG(dbgs() << "Emitting a XXPERM for the following shuffle:\n");
  LLVM_DEBUG(SVOp->dump());
  LLVM_DEBUG(dbgs() << "With the following permute control vector:\n");
  LLVM_DEBUG(XXPermMask.dump());
}

Or, at least get rid of the above code because it's not really needed. The debug info can come at the end of LowerVPERM.

10184

Aren't these lines the same as the lines 10177 - 10178 ?
If they are you probably don't need them.

10192

nit:
Use EVT instead for auto.
Code is generally easier to read when we have the types spelled out.

10206

nit:
vector -> vectors

10281

I don't think you have to do anything about this but more of a note to make sure it is taken into consideration. (Perhaps a comment in the code would be good.)
Not a big deal because this is debug info but in this case we could be overwriting the dl from the previous if statement if we have two swaps. I guess we want to use the location of the original swap which is fine and it doesn't matter which one we use.

10292

Does this get incremented twice for the same instruction?
Once here and once on line 10175 above.

10295

Oh, I see. The second half of the debug comment is down here.
It may be a good idea to move the two parts of the comment to the same place down here.

Also, the initial part of the comment :

Emitting a VPERM for the following shuffle:

May not be true as this may now be an XXPERM.

llvm/lib/Target/PowerPC/PPCInstrVSX.td

91

Is it possible to add a type constraint for the last operand here?

SDTCisVT<3, v4i32>

Or is that going to cause issues elsewhere?

llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll

8059

Interesting. Here we actually end up with an extra copy which is not what we want but it's because the xxperm feeds the return value and so the register allocation is constrained by the ABI. For this patch I think we can ignore this but we should make a note of it to fix it at a later date.

[maryammo]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

10295

The code staring in line 10163 for LLVB_DEBUG uses

10295

The LLVM_DEBUG code block starting at line 10163 uses SVOp which we dont pass it to LowerVPERM function as it is not needed here, that is why we have it there, I plan to delete LLVM_DEBUG from here and keep it there. Please lemme know if you have a concern.

llvm/lib/Target/PowerPC/PPCInstrVSX.td

91

The last one is SDTCisVT<2, v2f64> that has a different type constraint, are you suggesting to change it?

[stefanp]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

10295

The only concern I have with moving this comment up is that we still put out the debug message:

Emitting a VPERM for the following shuffle:

when in fact this may not be what is going on. We may be emitting a XXPERM for the shuffle.
You can move everything down because SVOp is just a cast of Op :

ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);

You can either re-do the cast or you can pass SVOp instead of Op because at this point we are pretty much guaranteed that Op is a ShuffleVectorSDNode.

llvm/lib/Target/PowerPC/PPCInstrVSX.td

91

No, I think that constraint is fine.
What I'm saying is that this SDTypeProfile<1, 3, has 1 output and 3 inputs.
Currently, the output and the first 2 inputs have a constraint but the last input doesn't have a constraint.

So, what I'm thinking of is:

--- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -88,7 +88,7 @@ def SDT_PPCst_vec_be : SDTypeProfile<0, 2, [
 
 def SDT_PPCxxperm : SDTypeProfile<1, 3, [
   SDTCisVT<0, v2f64>, SDTCisVT<1, v2f64>,
-  SDTCisVT<2, v2f64>]>;
+  SDTCisVT<2, v2f64>, SDTCisVT<3, v4i32>]>;
 //--------------------------- Custom PPC nodes -------------------------------//
 def PPClxvd2x  : SDNode<"PPCISD::LXVD2X", SDT_PPClxvd2x,
                         [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
@@ -4151,8 +4151,8 @@ def : Pat<(v8i16 (PPCldsplat ForceXForm:$A)),
           (v8i16 (VSPLTHs 3, (LXSIHZX ForceXForm:$A)))>;
 def : Pat<(v16i8 (PPCldsplat ForceXForm:$A)),
           (v16i8 (VSPLTBs 7, (LXSIBZX ForceXForm:$A)))>;
-def : Pat<(v2f64 (PPCxxperm v2f64:$XT, v2f64:$XB, (v16i8 (bitconvert v4i32:$C)))),
-          (XXPERM v2f64:$XT, v2f64:$XB, v4i32:$C)>;
 def : Pat<(v2f64 (PPCxxperm v2f64:$XT, v2f64:$XB, v4i32:$C)),
           (XXPERM v2f64:$XT, v2f64:$XB, v4i32:$C)>;
 } // HasVSX, HasP9Vector

[maryammo]

llvm/lib/Target/PowerPC/PPCInstrVSX.td

91

Such a change causes build failure which seems to be related to
def : Pat<(v2f64 (PPCxxperm v2f64:$XT, v2f64:$XB, (v16i8 (bitconvert v4i32:$C)))),

(XXPERM v2f64:$XT, v2f64:$XB, v4i32:$C)>;

[stefanp]

llvm/lib/Target/PowerPC/PPCInstrVSX.td

91

Right which is why I don't think you need those two lines for that pattern.
The two patterns:

def : Pat<(v2f64 (PPCxxperm v2f64:$XT, v2f64:$XB, (v16i8 (bitconvert v4i32:$C)))),
         (XXPERM v2f64:$XT, v2f64:$XB, v4i32:$C)>;
def : Pat<(v2f64 (PPCxxperm v2f64:$XT, v2f64:$XB, v4i32:$C)),
         (XXPERM v2f64:$XT, v2f64:$XB, v4i32:$C)>;

do practically the same thing and I don't believe there is any use for the first one.

You can add the constraint and then remove the pattern that isn't used.

[maryammo]

Address review comments

[stefanp]

I think this looks good.
Thank you for addressing the comments!

LGTM

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

10158

nit:
big-endian-based -> big-endian based

[stefanp]

Sorry, I know that I had approved this before but it seems that the test p10-splatImm32-undef.ll starts failing with this patch.
It may just be that the test needs to be updated but please make sure that is all it is.

[maryammo]

Unset the hasSideEffects for XXPERM

[stefanp]

Thank you for fixing that last test!
LGTM.

llvm/lib/Target/PowerPC/PPCISelLowering.h

enum NodeType : unsigned {
 
     /// VECSHL - The PPC vector shift left instruction
     ///
     VECSHL,
 
     /// XXPERMDI - The PPC XXPERMDI instruction
     ///
     XXPERMDI,
+    XXPERM,
 
     /// The CMPB instruction (takes two operands of i32 or i64).
     CMPB,
 
     /// Hi/Lo - These represent the high and low 16-bit parts of a global
     /// address respectively.  These nodes have two operands, the first of
     /// which must be a TargetGlobalAddress, and the second of which must be a
     /// Constant.  Selected naively, these turn into 'lis G+C' and 'li G+C',
private:
     SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerFunnelShift(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerVPERM(SDValue Op, SelectionDAG &DAG, ArrayRef<int> PermMask,
+                       EVT VT, SDValue V1, SDValue V2) const;
     SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerBSWAP(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
     SDValue lowerToLibCall(const char *LibCallName, SDValue Op,
                            SelectionDAG &DAG) const;
     SDValue lowerLibCallBasedOnType(const char *LibCallFloatName,

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

 
 cl::opt<bool> DisableAutoPairedVecSt(
     "disable-auto-paired-vec-st",
     cl::desc("disable automatically generated 32byte paired vector stores"),
     cl::init(true), cl::Hidden);
 
 STATISTIC(NumTailCalls, "Number of tail calls");
 STATISTIC(NumSiblingCalls, "Number of sibling calls");
-STATISTIC(ShufflesHandledWithVPERM, "Number of shuffles lowered to a VPERM");
+STATISTIC(ShufflesHandledWithVPERM,
+          "Number of shuffles lowered to a VPERM or XXPERM");
 STATISTIC(NumDynamicAllocaProbed, "Number of dynamic stack allocation probed");
 
 static bool isNByteElemShuffleMask(ShuffleVectorSDNode *, unsigned, int);
 
 static SDValue widenVec(SelectionDAG &DAG, SDValue Vec, const SDLoc &dl);
 
 static const char AIXSSPCanaryWordName[] = "__ssp_canary_word";
 
const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
   case PPCISD::VPERM:           return "PPCISD::VPERM";
   case PPCISD::XXSPLT:          return "PPCISD::XXSPLT";
   case PPCISD::XXSPLTI_SP_TO_DP:
     return "PPCISD::XXSPLTI_SP_TO_DP";
   case PPCISD::XXSPLTI32DX:
     return "PPCISD::XXSPLTI32DX";
   case PPCISD::VECINSERT:       return "PPCISD::VECINSERT";
   case PPCISD::XXPERMDI:        return "PPCISD::XXPERMDI";
+  case PPCISD::XXPERM:
+    return "PPCISD::XXPERM";
   case PPCISD::VECSHL:          return "PPCISD::VECSHL";
   case PPCISD::CMPB:            return "PPCISD::CMPB";
   case PPCISD::Hi:              return "PPCISD::Hi";
   case PPCISD::Lo:              return "PPCISD::Lo";
   case PPCISD::TOC_ENTRY:       return "PPCISD::TOC_ENTRY";
   case PPCISD::ATOMIC_CMP_SWAP_8: return "PPCISD::ATOMIC_CMP_SWAP_8";
   case PPCISD::ATOMIC_CMP_SWAP_16: return "PPCISD::ATOMIC_CMP_SWAP_16";
   case PPCISD::DYNALLOC:        return "PPCISD::DYNALLOC";
SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
   // vector that will get spilled to the constant pool.
   if (V2.isUndef()) V2 = V1;
 
   // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
   // that it is in input element units, not in bytes.  Convert now.
 
   // For little endian, the order of the input vectors is reversed, and
   // the permutation mask is complemented with respect to 31.  This is
   // necessary to produce proper semantics with the big-endian-biased vperm
   // instruction.
   EVT EltVT = V1.getValueType().getVectorElementType();
   unsigned BytesPerElement = EltVT.getSizeInBits()/8;
 
   SmallVector<SDValue, 16> ResultMask;
   for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
     unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
 
     for (unsigned j = 0; j != BytesPerElement; ++j)
       if (isLittleEndian)
         ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement + j),
                                              dl, MVT::i32));
       else
         ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement + j, dl,
                                              MVT::i32));
   }
 
   ShufflesHandledWithVPERM++;
   SDValue VPermMask = DAG.getBuildVector(MVT::v16i8, dl, ResultMask);
   LLVM_DEBUG(dbgs() << "Emitting a VPERM for the following shuffle:\n");
   LLVM_DEBUG(SVOp->dump());
   LLVM_DEBUG(dbgs() << "With the following permute control vector:\n");
   LLVM_DEBUG(VPermMask.dump());
 
+  LLVM_DEBUG(dbgs() << "Emitting a VPERM for the following shuffle:\n");
+  LLVM_DEBUG(SVOp->dump());
+  return LowerVPERM(Op, DAG, PermMask, VT, V1, V2);
+}
+
+SDValue PPCTargetLowering::LowerVPERM(SDValue Op, SelectionDAG &DAG,
+                                      ArrayRef<int> PermMask, EVT VT,
+                                      SDValue V1, SDValue V2) const {
+  // SDValue VPERMNode;
+  unsigned Opcode = PPCISD::VPERM;
+  auto ValType = V1.getValueType();
+  SDLoc dl(Op);
+  bool NeedSwap = false;
+  bool isLittleEndian = Subtarget.isLittleEndian();
+
+  // Only need to place items backwards in LE,
+  // the mask will be properly calculated.
+  if (isLittleEndian)
+    std::swap(V1, V2);
+
+  if (Subtarget.isISA3_0() && (V1->hasOneUse() || V2->hasOneUse())) {
+    LLVM_DEBUG(
+        dbgs()
+        << "At least one of two input vector is dead - using XXPERM instead\n");
+    Opcode = PPCISD::XXPERM;
+
+    // if V2 is dead, then we swap vV1 and V2 so we can
+    // use V2 as the destination instead.
+    if (!V1->hasOneUse() && V2->hasOneUse()) {
+      std::swap(V1, V2);
+      NeedSwap = !NeedSwap;
+    }
+  }
+
+  bool V1HasXSWAP = V1->getOperand(0)->getOpcode() == PPCISD::XXSWAPD;
+  bool V2HasXSWAP = V2->getOperand(0)->getOpcode() == PPCISD::XXSWAPD;
+
+  // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
+  // that it is in input element units, not in bytes.  Convert now.
+
+  // For little endian, the order of the input vectors is reversed, and
+  // the permutation mask is complemented with respect to 31.  This is
+  // necessary to produce proper semantics with the big-endian-based vperm
+  // instruction.
+  EVT EltVT = V1.getValueType().getVectorElementType();
+  unsigned BytesPerElement = EltVT.getSizeInBits() / 8;
+
+  /*
+  Vectors will be appended like so: [ V1 | v2 ]
+  XXSWAPD on V1:
+  [   A   |   B   |   C   |   D   ] -> [   C   |   D   |   A   |   B   ]
+     0-3     4-7     8-11   12-15         0-3     4-7     8-11   12-15
+  IE, index of A, B += 8, and index of C, D -= 8.
+  XXSWAPD on V2:
+  [   E   |   F   |   G   |   H   ] -> [   G   |   H   |   E   |   F   ]
+    16-19   20-23   24-27   28-31        16-19   20-23   24-27   28-31
+  IE, index of E, F += 8, index of G, H -= 8
+  Swap V1 and V2:
+  [   V1   |   V2  ] -> [   V2   |   V1   ]
+     0-15     16-31        0-15     16-31
+  IE, index of V1 += 16, index of V2 -= 16
+  */
+
+  SmallVector<SDValue, 16> ResultMask;
+  for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
+    unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
+
+    if (V1HasXSWAP) {
+      if (SrcElt < 8)
+        SrcElt += 8;
+      else if (SrcElt < 16)
+        SrcElt -= 8;
+    }
+    if (V2HasXSWAP) {
+      if (SrcElt > 23)
+        SrcElt -= 8;
+      else if (SrcElt > 15)
+        SrcElt += 8;
+    }
+    if (NeedSwap) {
+      if (SrcElt < 16)
+        SrcElt += 16;
+      else
+        SrcElt -= 16;
+    }
+    for (unsigned j = 0; j != BytesPerElement; ++j)
       if (isLittleEndian)
-    return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
-                       V2, V1, VPermMask);
+        ResultMask.push_back(
+            DAG.getConstant(31 - (SrcElt * BytesPerElement + j), dl, MVT::i32));
       else
-    return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
-                       V1, V2, VPermMask);
+        ResultMask.push_back(
+            DAG.getConstant(SrcElt * BytesPerElement + j, dl, MVT::i32));
+  }
+
+  if (V1HasXSWAP) {
+    dl = SDLoc(V1->getOperand(0));
+    V1 = V1->getOperand(0)->getOperand(1);
+  }
+  if (V2HasXSWAP) {
+    dl = SDLoc(V1->getOperand(0));
+    V2 = V2->getOperand(0)->getOperand(1);
+  }
+
+  if (V1HasXSWAP || V2HasXSWAP || Opcode == PPCISD::XXPERM) {
+    if (Subtarget.isPPC64() && ValType != MVT::v2f64)
+      V1 = DAG.getBitcast(MVT::v2f64, V1);
+    if (Subtarget.isPPC64() && V2.getValueType() != MVT::v2f64)
+      V2 = DAG.getBitcast(MVT::v2f64, V2);
+  }
+
+  ShufflesHandledWithVPERM++;
+  SDValue VPermMask = DAG.getBuildVector(MVT::v16i8, dl, ResultMask);
+  LLVM_DEBUG(dbgs() << "With the following permute control vector:\n");
+  LLVM_DEBUG(VPermMask.dump());
+
+  if (Opcode == PPCISD::XXPERM)
+    VPermMask = DAG.getBitcast(MVT::v4i32, VPermMask);
+
+  SDValue VPERMNode =
+      DAG.getNode(Opcode, dl, V1.getValueType(), V1, V2, VPermMask);
+
+  // if (ValType != MVT::v2f64 && Opcode == PPCISD::XXPERM)
+  VPERMNode = DAG.getBitcast(ValType, VPERMNode);
+  return VPERMNode;
 }
 
 /// getVectorCompareInfo - Given an intrinsic, return false if it is not a
 /// vector comparison.  If it is, return true and fill in Opc/isDot with
 /// information about the intrinsic.
 static bool getVectorCompareInfo(SDValue Intrin, int &CompareOpc,
                                  bool &isDot, const PPCSubtarget &Subtarget) {
   unsigned IntrinsicID =

llvm/lib/Target/PowerPC/PPCInstrAltivec.td

 
 def : Pat<(int_ppc_altivec_vmaddfp v4f32:$A, v4f32:$B, v4f32:$C),
           (VMADDFP $A, $B, $C)>;
 def : Pat<(int_ppc_altivec_vnmsubfp v4f32:$A, v4f32:$B, v4f32:$C),
           (VNMSUBFP $A, $B, $C)>;
 
 def : Pat<(PPCvperm v16i8:$vA, v16i8:$vB, v16i8:$vC),
           (VPERM $vA, $vB, $vC)>;
+def : Pat<(PPCvperm v2f64:$vA, v2f64:$vB, v16i8:$vC),
+          (VPERM $vA, $vB, $vC)>;
 
 def : Pat<(PPCfre v4f32:$A), (VREFP $A)>;
 def : Pat<(PPCfrsqrte v4f32:$A), (VRSQRTEFP $A)>;
 
 // Vector shifts
 def : Pat<(v16i8 (shl v16i8:$vA, v16i8:$vB)),
           (v16i8 (VSLB $vA, $vB))>;
 def : Pat<(v8i16 (shl v8i16:$vA, v8i16:$vB)),

llvm/lib/Target/PowerPC/PPCInstrVSX.td

def SDT_PPCld_vec_be : SDTypeProfile<1, 1, [
   SDTCisVec<0>, SDTCisPtrTy<1>
 ]>;
 def SDT_PPCst_vec_be : SDTypeProfile<0, 2, [
   SDTCisVec<0>, SDTCisPtrTy<1>
 ]>;
 
 //--------------------------- Custom PPC nodes -------------------------------//
 def PPClxvd2x  : SDNode<"PPCISD::LXVD2X", SDT_PPClxvd2x,
                         [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 def PPCstxvd2x : SDNode<"PPCISD::STXVD2X", SDT_PPCstxvd2x,
                         [SDNPHasChain, SDNPMayStore]>;
 def PPCld_vec_be  : SDNode<"PPCISD::LOAD_VEC_BE", SDT_PPCld_vec_be,
                         [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 def PPCst_vec_be : SDNode<"PPCISD::STORE_VEC_BE", SDT_PPCst_vec_be,
                         [SDNPHasChain, SDNPMayStore]>;
 def PPCxxswapd : SDNode<"PPCISD::XXSWAPD", SDT_PPCxxswapd, [SDNPHasChain]>;
 def PPCmfvsr : SDNode<"PPCISD::MFVSR", SDTUnaryOp, []>;
def PPCldsplat : SDNode<"PPCISD::LD_SPLAT", SDT_PPCldsplat,
                         [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 def PPCzextldsplat : SDNode<"PPCISD::ZEXT_LD_SPLAT", SDT_PPCldsplat,
                         [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 def PPCsextldsplat : SDNode<"PPCISD::SEXT_LD_SPLAT", SDT_PPCldsplat,
                         [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 def PPCSToV : SDNode<"PPCISD::SCALAR_TO_VECTOR_PERMUTED",
                      SDTypeProfile<1, 1, []>, []>;
 
+def SDT_PPCxxperm : SDTypeProfile<1, 3,
+                                  [SDTCisVT<0, v2f64>, SDTCisVT<1, v2f64>,
+                                   SDTCisVT<2, v2f64>]>;
+def PPCxxperm : SDNode<"PPCISD::XXPERM", SDT_PPCxxperm, []>;
 //-------------------------- Predicate definitions ---------------------------//
 def HasVSX : Predicate<"Subtarget->hasVSX()">;
 def IsLittleEndian : Predicate<"Subtarget->isLittleEndian()">;
 def IsBigEndian : Predicate<"!Subtarget->isLittleEndian()">;
 def IsPPC64 : Predicate<"Subtarget->isPPC64()">;
 def HasOnlySwappingMemOps : Predicate<"!Subtarget->hasP9Vector()">;
 def HasP8Vector : Predicate<"Subtarget->hasP8Vector()">;
 def HasDirectMove : Predicate<"Subtarget->hasDirectMove()">;
def XXBRD : XX2_XT6_XO5_XB6<60, 23, 475, "xxbrd", vsrc,
     [(set v2i64:$XT, (bswap v2i64:$XB))]>;
   // FIXME: Setting the hasSideEffects flag here to match current behaviour.
   let hasSideEffects = 1 in
   def XXBRQ : XX2_XT6_XO5_XB6<60, 31, 475, "xxbrq", vsrc, []>;
 
   // Vector Permute
   // FIXME: Setting the hasSideEffects flag here to match current behaviour.
   let hasSideEffects = 1 in {
-    def XXPERM  : XX3_XT5_XA5_XB5<60, 26, "xxperm" , vsrc, vsrc, vsrc,
-                                  IIC_VecPerm, []>;
-    def XXPERMR : XX3_XT5_XA5_XB5<60, 58, "xxpermr", vsrc, vsrc, vsrc,
-                                  IIC_VecPerm, []>;
+    def XXPERM  : XX3Form<60, 26, (outs vsrc:$XT),
+                                  (ins vsrc:$XA, vsrc:$XTi, vsrc:$XB),
+                          "xxperm $XT, $XA, $XB", IIC_VecPerm, []>,
+                          RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
+    def XXPERMR : XX3Form<60, 58, (outs vsrc:$XT),
+                                  (ins vsrc:$XA, vsrc:$XTi, vsrc:$XB),
+                          "xxpermr $XT, $XA, $XB", IIC_VecPerm, []>,
+                          RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
   }
 
   // Vector Splat Immediate Byte
   // FIXME: Setting the hasSideEffects flag here to match current behaviour.
   let hasSideEffects = 1 in
   def XXSPLTIB : X_RD6_IMM8<60, 360, (outs vsrc:$XT), (ins u8imm:$IMM8),
                             "xxspltib $XT, $IMM8", IIC_VecPerm, []>;
 

 def : Pat<(v4f32 (PPCldsplat ForceXForm:$A)),
           (v4f32 (LXVWSX ForceXForm:$A))>;
 def : Pat<(v4i32 (PPCldsplat ForceXForm:$A)),
           (v4i32 (LXVWSX ForceXForm:$A))>;
 def : Pat<(v8i16 (PPCldsplat ForceXForm:$A)),
           (v8i16 (VSPLTHs 3, (LXSIHZX ForceXForm:$A)))>;
 def : Pat<(v16i8 (PPCldsplat ForceXForm:$A)),
           (v16i8 (VSPLTBs 7, (LXSIBZX ForceXForm:$A)))>;
+def : Pat<(v2f64 (PPCxxperm v2f64:$XT, v2f64:$XB, (v16i8 (bitconvert v4i32:$C)))),
+          (XXPERM v2f64:$XT, v2f64:$XB, v4i32:$C)>;
+def : Pat<(v2f64 (PPCxxperm v2f64:$XT, v2f64:$XB, v4i32:$C)),
+          (XXPERM v2f64:$XT, v2f64:$XB, v4i32:$C)>;
 } // HasVSX, HasP9Vector
 
 // Any Power9 VSX subtarget with equivalent length but better Power10 VSX
 // patterns.
 // Two identical blocks are required due to the slightly different predicates:
 // One without P10 instructions, the other is BigEndian only with P10 instructions.
 let Predicates = [HasVSX, HasP9Vector, NoP10Vector] in {
 // Little endian Power10 subtargets produce a shorter pattern but require a

llvm/test/CodeGen/PowerPC/aix-p9-insert-extract.ll

 }
 
 ; The following testcases use the same vector in both arguments of the
 ; shufflevector.  If halfword element 3 in BE mode(or 4 in LE mode) is the one
 ; we're attempting to insert, then we can use the vector insert instruction
 define <8 x i16> @shuffle_vector_halfword_0_4(<8 x i16> %a) {
 ; CHECK-64-LABEL: shuffle_vector_halfword_0_4:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    ld 3, L..C0(2)
-; CHECK-64-NEXT:    lxv 35, 0(3)
-; CHECK-64-NEXT:    vperm 2, 2, 2, 3
+; CHECK-64-NEXT:    ld 3, L..C0(2) # %const.0
+; CHECK-64-NEXT:    lxv 0, 0(3)
+; CHECK-64-NEXT:    xxperm 34, 34, 0
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_halfword_0_4:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    lwz 3, L..C0(2)
-; CHECK-32-NEXT:    lxv 35, 0(3)
-; CHECK-32-NEXT:    vperm 2, 2, 2, 3
+; CHECK-32-NEXT:    lwz 3, L..C0(2) # %const.0
+; CHECK-32-NEXT:    lxv 0, 0(3)
+; CHECK-32-NEXT:    xxperm 34, 34, 0
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 4, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_1_3(<8 x i16> %a) {
 ; CHECK-64-LABEL: shuffle_vector_halfword_1_3:

 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 3, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_3_4(<8 x i16> %a) {
 ; CHECK-64-LABEL: shuffle_vector_halfword_3_4:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    ld 3, L..C1(2)
-; CHECK-64-NEXT:    lxv 35, 0(3)
-; CHECK-64-NEXT:    vperm 2, 2, 2, 3
+; CHECK-64-NEXT:    ld 3, L..C1(2) # %const.0
+; CHECK-64-NEXT:    lxv 0, 0(3)
+; CHECK-64-NEXT:    xxperm 34, 34, 0
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_halfword_3_4:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    lwz 3, L..C1(2)
-; CHECK-32-NEXT:    lxv 35, 0(3)
-; CHECK-32-NEXT:    vperm 2, 2, 2, 3
+; CHECK-32-NEXT:    lwz 3, L..C1(2) # %const.0
+; CHECK-32-NEXT:    lxv 0, 0(3)
+; CHECK-32-NEXT:    xxperm 34, 34, 0
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 4, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_4_3(<8 x i16> %a) {
 ; CHECK-64-LABEL: shuffle_vector_halfword_4_3:

 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 3, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_6_4(<8 x i16> %a) {
 ; CHECK-64-LABEL: shuffle_vector_halfword_6_4:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    ld 3, L..C2(2)
-; CHECK-64-NEXT:    lxv 35, 0(3)
-; CHECK-64-NEXT:    vperm 2, 2, 2, 3
+; CHECK-64-NEXT:    ld 3, L..C2(2) # %const.0
+; CHECK-64-NEXT:    lxv 0, 0(3)
+; CHECK-64-NEXT:    xxperm 34, 34, 0
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_halfword_6_4:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    lwz 3, L..C2(2)
-; CHECK-32-NEXT:    lxv 35, 0(3)
-; CHECK-32-NEXT:    vperm 2, 2, 2, 3
+; CHECK-32-NEXT:    lwz 3, L..C2(2) # %const.0
+; CHECK-32-NEXT:    lxv 0, 0(3)
+; CHECK-32-NEXT:    xxperm 34, 34, 0
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 4, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_7_4(<8 x i16> %a) {
 ; CHECK-64-LABEL: shuffle_vector_halfword_7_4:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    ld 3, L..C3(2)
-; CHECK-64-NEXT:    lxv 35, 0(3)
-; CHECK-64-NEXT:    vperm 2, 2, 2, 3
+; CHECK-64-NEXT:    ld 3, L..C3(2) # %const.0
+; CHECK-64-NEXT:    lxv 0, 0(3)
+; CHECK-64-NEXT:    xxperm 34, 34, 0
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_halfword_7_4:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    lwz 3, L..C3(2)
-; CHECK-32-NEXT:    lxv 35, 0(3)
-; CHECK-32-NEXT:    vperm 2, 2, 2, 3
+; CHECK-32-NEXT:    lwz 3, L..C3(2) # %const.0
+; CHECK-32-NEXT:    lxv 0, 0(3)
+; CHECK-32-NEXT:    xxperm 34, 34, 0
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 4>
   ret <8 x i16> %vecins
 }
 
 ; The following testcases take one byte element from the second vector and
 ; inserts it at various locations in the first vector

 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 7, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_1_8(<16 x i8> %a) {
 ; CHECK-64-LABEL: shuffle_vector_byte_1_8:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    ld 3, L..C4(2)
-; CHECK-64-NEXT:    lxv 35, 0(3)
-; CHECK-64-NEXT:    vperm 2, 2, 2, 3
+; CHECK-64-NEXT:    ld 3, L..C4(2) # %const.0
+; CHECK-64-NEXT:    lxv 0, 0(3)
+; CHECK-64-NEXT:    xxperm 34, 34, 0
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_1_8:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    lwz 3, L..C4(2)
-; CHECK-32-NEXT:    lxv 35, 0(3)
-; CHECK-32-NEXT:    vperm 2, 2, 2, 3
+; CHECK-32-NEXT:    lwz 3, L..C4(2) # %const.0
+; CHECK-32-NEXT:    lxv 0, 0(3)
+; CHECK-32-NEXT:    xxperm 34, 34, 0
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 8, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_2_8(<16 x i8> %a) {
 ; CHECK-64-LABEL: shuffle_vector_byte_2_8:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    ld 3, L..C5(2)
-; CHECK-64-NEXT:    lxv 35, 0(3)
-; CHECK-64-NEXT:    vperm 2, 2, 2, 3
+; CHECK-64-NEXT:    ld 3, L..C5(2) # %const.0
+; CHECK-64-NEXT:    lxv 0, 0(3)
+; CHECK-64-NEXT:    xxperm 34, 34, 0
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_2_8:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    lwz 3, L..C5(2)
-; CHECK-32-NEXT:    lxv 35, 0(3)
-; CHECK-32-NEXT:    vperm 2, 2, 2, 3
+; CHECK-32-NEXT:    lwz 3, L..C5(2) # %const.0
+; CHECK-32-NEXT:    lxv 0, 0(3)
+; CHECK-32-NEXT:    xxperm 34, 34, 0
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 8, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_3_7(<16 x i8> %a) {
 ; CHECK-64-LABEL: shuffle_vector_byte_3_7:

 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 7, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_5_8(<16 x i8> %a) {
 ; CHECK-64-LABEL: shuffle_vector_byte_5_8:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    ld 3, L..C6(2)
-; CHECK-64-NEXT:    lxv 35, 0(3)
-; CHECK-64-NEXT:    vperm 2, 2, 2, 3
+; CHECK-64-NEXT:    ld 3, L..C6(2) # %const.0
+; CHECK-64-NEXT:    lxv 0, 0(3)
+; CHECK-64-NEXT:    xxperm 34, 34, 0
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_5_8:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    lwz 3, L..C6(2)
-; CHECK-32-NEXT:    lxv 35, 0(3)
-; CHECK-32-NEXT:    vperm 2, 2, 2, 3
+; CHECK-32-NEXT:    lwz 3, L..C6(2) # %const.0
+; CHECK-32-NEXT:    lxv 0, 0(3)
+; CHECK-32-NEXT:    xxperm 34, 34, 0
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 8, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_6_8(<16 x i8> %a) {
 ; CHECK-64-LABEL: shuffle_vector_byte_6_8:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    ld 3, L..C7(2)
-; CHECK-64-NEXT:    lxv 35, 0(3)
-; CHECK-64-NEXT:    vperm 2, 2, 2, 3
+; CHECK-64-NEXT:    ld 3, L..C7(2) # %const.0
+; CHECK-64-NEXT:    lxv 0, 0(3)
+; CHECK-64-NEXT:    xxperm 34, 34, 0
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_6_8:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    lwz 3, L..C7(2)
-; CHECK-32-NEXT:    lxv 35, 0(3)
-; CHECK-32-NEXT:    vperm 2, 2, 2, 3
+; CHECK-32-NEXT:    lwz 3, L..C7(2) # %const.0
+; CHECK-32-NEXT:    lxv 0, 0(3)
+; CHECK-32-NEXT:    xxperm 34, 34, 0
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_7_8(<16 x i8> %a) {
 ; CHECK-64-LABEL: shuffle_vector_byte_7_8:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    ld 3, L..C8(2)
-; CHECK-64-NEXT:    lxv 35, 0(3)
-; CHECK-64-NEXT:    vperm 2, 2, 2, 3
+; CHECK-64-NEXT:    ld 3, L..C8(2) # %const.0
+; CHECK-64-NEXT:    lxv 0, 0(3)
+; CHECK-64-NEXT:    xxperm 34, 34, 0
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_7_8:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    lwz 3, L..C8(2)
-; CHECK-32-NEXT:    lxv 35, 0(3)
-; CHECK-32-NEXT:    vperm 2, 2, 2, 3
+; CHECK-32-NEXT:    lwz 3, L..C8(2) # %const.0
+; CHECK-32-NEXT:    lxv 0, 0(3)
+; CHECK-32-NEXT:    xxperm 34, 34, 0
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 8, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_8_7(<16 x i8> %a) {
 ; CHECK-64-LABEL: shuffle_vector_byte_8_7:

 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 7, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_11_8(<16 x i8> %a) {
 ; CHECK-64-LABEL: shuffle_vector_byte_11_8:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    ld 3, L..C9(2)
-; CHECK-64-NEXT:    lxv 35, 0(3)
-; CHECK-64-NEXT:    vperm 2, 2, 2, 3
+; CHECK-64-NEXT:    ld 3, L..C9(2) # %const.0
+; CHECK-64-NEXT:    lxv 0, 0(3)
+; CHECK-64-NEXT:    xxperm 34, 34, 0
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_11_8:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    lwz 3, L..C9(2)
-; CHECK-32-NEXT:    lxv 35, 0(3)
-; CHECK-32-NEXT:    vperm 2, 2, 2, 3
+; CHECK-32-NEXT:    lwz 3, L..C9(2) # %const.0
+; CHECK-32-NEXT:    lxv 0, 0(3)
+; CHECK-32-NEXT:    xxperm 34, 34, 0
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 8, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_12_8(<16 x i8> %a) {
 ; CHECK-64-LABEL: shuffle_vector_byte_12_8:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    ld 3, L..C10(2)
-; CHECK-64-NEXT:    lxv 35, 0(3)
-; CHECK-64-NEXT:    vperm 2, 2, 2, 3
+; CHECK-64-NEXT:    ld 3, L..C10(2) # %const.0
+; CHECK-64-NEXT:    lxv 0, 0(3)
+; CHECK-64-NEXT:    xxperm 34, 34, 0
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_12_8:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    lwz 3, L..C10(2)
-; CHECK-32-NEXT:    lxv 35, 0(3)
-; CHECK-32-NEXT:    vperm 2, 2, 2, 3
+; CHECK-32-NEXT:    lwz 3, L..C10(2) # %const.0
+; CHECK-32-NEXT:    lxv 0, 0(3)
+; CHECK-32-NEXT:    xxperm 34, 34, 0
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 8, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_13_7(<16 x i8> %a) {
 ; CHECK-64-LABEL: shuffle_vector_byte_13_7:

 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 7, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_15_8(<16 x i8> %a) {
 ; CHECK-64-LABEL: shuffle_vector_byte_15_8:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    ld 3, L..C11(2)
-; CHECK-64-NEXT:    lxv 35, 0(3)
-; CHECK-64-NEXT:    vperm 2, 2, 2, 3
+; CHECK-64-NEXT:    ld 3, L..C11(2) # %const.0
+; CHECK-64-NEXT:    lxv 0, 0(3)
+; CHECK-64-NEXT:    xxperm 34, 34, 0
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_15_8:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    lwz 3, L..C11(2)
-; CHECK-32-NEXT:    lxv 35, 0(3)
-; CHECK-32-NEXT:    vperm 2, 2, 2, 3
+; CHECK-32-NEXT:    lwz 3, L..C11(2) # %const.0
+; CHECK-32-NEXT:    lxv 0, 0(3)
+; CHECK-32-NEXT:    xxperm 34, 34, 0
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 8>
   ret <16 x i8> %vecins
 }
 
 ; The following tests try to insert one halfword element into the vector.  We
 ; should always be using the 'vinserth' instruction.

llvm/test/CodeGen/PowerPC/aix-p9-xxinsertw-xxextractuw.ll

 entry:
   %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
   ret <4 x float> %vecins
 }
 define <4 x float> @testSameVecEl0LE(<4 x float> %a) {
 ; CHECK-64-LABEL: testSameVecEl0LE:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    ld 3, L..C0(2) # %const.0
-; CHECK-64-NEXT:    lxv 35, 0(3)
-; CHECK-64-NEXT:    vperm 2, 2, 2, 3
+; CHECK-64-NEXT:    lxv 0, 0(3)
+; CHECK-64-NEXT:    xxperm 34, 34, 0
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: testSameVecEl0LE:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    lwz 3, L..C0(2) # %const.0
-; CHECK-32-NEXT:    lxv 35, 0(3)
-; CHECK-32-NEXT:    vperm 2, 2, 2, 3
+; CHECK-32-NEXT:    lxv 0, 0(3)
+; CHECK-32-NEXT:    xxperm 34, 34, 0
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 6, i32 1, i32 2, i32 3>
   ret <4 x float> %vecins
 }
 define <4 x float> @testSameVecEl1LE(<4 x float> %a) {
 ; CHECK-64-LABEL: testSameVecEl1LE:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    ld 3, L..C1(2) # %const.0
-; CHECK-64-NEXT:    lxv 35, 0(3)
-; CHECK-64-NEXT:    vperm 2, 2, 2, 3
+; CHECK-64-NEXT:    lxv 0, 0(3)
+; CHECK-64-NEXT:    xxperm 34, 34, 0
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: testSameVecEl1LE:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    lwz 3, L..C1(2) # %const.0
-; CHECK-32-NEXT:    lxv 35, 0(3)
-; CHECK-32-NEXT:    vperm 2, 2, 2, 3
+; CHECK-32-NEXT:    lxv 0, 0(3)
+; CHECK-32-NEXT:    xxperm 34, 34, 0
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
   ret <4 x float> %vecins
 }
 define <4 x float> @testSameVecEl3LE(<4 x float> %a) {
 ; CHECK-64-LABEL: testSameVecEl3LE:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    ld 3, L..C2(2) # %const.0
-; CHECK-64-NEXT:    lxv 35, 0(3)
-; CHECK-64-NEXT:    vperm 2, 2, 2, 3
+; CHECK-64-NEXT:    lxv 0, 0(3)
+; CHECK-64-NEXT:    xxperm 34, 34, 0
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: testSameVecEl3LE:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    lwz 3, L..C2(2) # %const.0
-; CHECK-32-NEXT:    lxv 35, 0(3)
-; CHECK-32-NEXT:    vperm 2, 2, 2, 3
+; CHECK-32-NEXT:    lxv 0, 0(3)
+; CHECK-32-NEXT:    xxperm 34, 34, 0
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 6>
   ret <4 x float> %vecins
 }
 define <4 x float> @insertVarF(<4 x float> %a, float %f, i32 %el) {
 ; CHECK-64-LABEL: insertVarF:
 ; CHECK-64:       # %bb.0: # %entry

llvm/test/CodeGen/PowerPC/build-vector-tests.ll

 }
 
 define <4 x i32> @fromDiffMemConsDi(i32* nocapture readonly %arr) {
 ; P9BE-LABEL: fromDiffMemConsDi:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    lxv v2, 0(r3)
 ; P9BE-NEXT:    addis r3, r2, .LCPI7_0@toc@ha
 ; P9BE-NEXT:    addi r3, r3, .LCPI7_0@toc@l
-; P9BE-NEXT:    lxv v3, 0(r3)
-; P9BE-NEXT:    vperm v2, v2, v2, v3
+; P9BE-NEXT:    lxv vs0, 0(r3)
+; P9BE-NEXT:    xxperm v2, v2, vs0
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffMemConsDi:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lxvw4x v2, 0, r3
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffMemConsDi:

 ; P9BE-LABEL: fromDiffMemVarDi:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    sldi r4, r4, 2
 ; P9BE-NEXT:    add r3, r3, r4
 ; P9BE-NEXT:    li r4, -12
 ; P9BE-NEXT:    lxvx v2, r3, r4
 ; P9BE-NEXT:    addis r3, r2, .LCPI9_0@toc@ha
 ; P9BE-NEXT:    addi r3, r3, .LCPI9_0@toc@l
-; P9BE-NEXT:    lxv v3, 0(r3)
-; P9BE-NEXT:    vperm v2, v2, v2, v3
+; P9BE-NEXT:    lxv vs0, 0(r3)
+; P9BE-NEXT:    xxperm v2, v2, vs0
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffMemVarDi:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    sldi r4, r4, 2
 ; P9LE-NEXT:    add r3, r3, r4
 ; P9LE-NEXT:    li r4, -12
 ; P9LE-NEXT:    lxvx v2, r3, r4
 ; P9LE-NEXT:    addis r3, r2, .LCPI9_0@toc@ha
 ; P9LE-NEXT:    addi r3, r3, .LCPI9_0@toc@l
-; P9LE-NEXT:    lxv v3, 0(r3)
-; P9LE-NEXT:    vperm v2, v2, v2, v3
+; P9LE-NEXT:    lxv vs0, 0(r3)
+; P9LE-NEXT:    xxperm v2, v2, vs0
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffMemVarDi:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    sldi r4, r4, 2
 ; P8BE-NEXT:    addis r5, r2, .LCPI9_0@toc@ha
 ; P8BE-NEXT:    add r3, r3, r4
 ; P8BE-NEXT:    addi r4, r5, .LCPI9_0@toc@l
 ; P8BE-NEXT:    addi r3, r3, -12
 ; P8BE-NEXT:    lxvw4x v3, 0, r4
 ; P8BE-NEXT:    lxvw4x v2, 0, r3
 ; P8BE-NEXT:    vperm v2, v2, v2, v3
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fromDiffMemVarDi:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    sldi r4, r4, 2
 ; P8LE-NEXT:    addis r5, r2, .LCPI9_0@toc@ha
+; P8LE-NEXT:    sldi r4, r4, 2
+; P8LE-NEXT:    addi r5, r5, .LCPI9_0@toc@l
 ; P8LE-NEXT:    add r3, r3, r4
-; P8LE-NEXT:    addi r4, r5, .LCPI9_0@toc@l
+; P8LE-NEXT:    lxvd2x vs0, 0, r5
 ; P8LE-NEXT:    addi r3, r3, -12
-; P8LE-NEXT:    lxvd2x vs1, 0, r4
-; P8LE-NEXT:    lxvd2x vs0, 0, r3
-; P8LE-NEXT:    xxswapd v3, vs1
-; P8LE-NEXT:    xxswapd v2, vs0
+; P8LE-NEXT:    lxvd2x v2, 0, r3
+; P8LE-NEXT:    xxswapd v3, vs0
 ; P8LE-NEXT:    vperm v2, v2, v2, v3
 ; P8LE-NEXT:    blr
 entry:
   %idxprom = sext i32 %elem to i64
   %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom
   %0 = load i32, i32* %arrayidx, align 4
   %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
   %sub = add nsw i32 %elem, -1
entry:
   %1 = load <4 x float>, <4 x float>* %0, align 4
   %2 = fptosi <4 x float> %1 to <4 x i32>
   ret <4 x i32> %2
 }
 
 define <4 x i32> @fromDiffMemConsDConvftoi(float* nocapture readonly %ptr) {
 ; P9BE-LABEL: fromDiffMemConsDConvftoi:
 ; P9BE:       # %bb.0: # %entry
-; P9BE-NEXT:    lxv v2, 0(r3)
+; P9BE-NEXT:    lxv vs0, 0(r3)
 ; P9BE-NEXT:    addis r3, r2, .LCPI18_0@toc@ha
 ; P9BE-NEXT:    addi r3, r3, .LCPI18_0@toc@l
-; P9BE-NEXT:    lxv v3, 0(r3)
-; P9BE-NEXT:    vperm v2, v2, v2, v3
-; P9BE-NEXT:    xvcvspsxws v2, v2
+; P9BE-NEXT:    lxv vs1, 0(r3)
+; P9BE-NEXT:    xxperm vs0, vs0, vs1
+; P9BE-NEXT:    xvcvspsxws v2, vs0
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffMemConsDConvftoi:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    lxv v2, 0(r3)
+; P9LE-NEXT:    lxv vs0, 0(r3)
 ; P9LE-NEXT:    addis r3, r2, .LCPI18_0@toc@ha
 ; P9LE-NEXT:    addi r3, r3, .LCPI18_0@toc@l
-; P9LE-NEXT:    lxv v3, 0(r3)
-; P9LE-NEXT:    vperm v2, v2, v2, v3
-; P9LE-NEXT:    xvcvspsxws v2, v2
+; P9LE-NEXT:    lxv vs1, 0(r3)
+; P9LE-NEXT:    xxperm vs0, vs0, vs1
+; P9LE-NEXT:    xvcvspsxws v2, vs0
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffMemConsDConvftoi:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    addis r4, r2, .LCPI18_0@toc@ha
 ; P8BE-NEXT:    lxvw4x v2, 0, r3
 ; P8BE-NEXT:    addi r4, r4, .LCPI18_0@toc@l
 ; P8BE-NEXT:    lxvw4x v3, 0, r4
 ; P8BE-NEXT:    vperm v2, v2, v2, v3
 ; P8BE-NEXT:    xvcvspsxws v2, v2
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fromDiffMemConsDConvftoi:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    addis r4, r2, .LCPI18_0@toc@ha
-; P8LE-NEXT:    lxvd2x vs0, 0, r3
+; P8LE-NEXT:    lxvd2x v2, 0, r3
 ; P8LE-NEXT:    addi r4, r4, .LCPI18_0@toc@l
-; P8LE-NEXT:    lxvd2x vs1, 0, r4
-; P8LE-NEXT:    xxswapd v2, vs0
-; P8LE-NEXT:    xxswapd v3, vs1
+; P8LE-NEXT:    lxvd2x vs0, 0, r4
+; P8LE-NEXT:    xxswapd v3, vs0
 ; P8LE-NEXT:    vperm v2, v2, v2, v3
 ; P8LE-NEXT:    xvcvspsxws v2, v2
 ; P8LE-NEXT:    blr
 entry:
   %arrayidx = getelementptr inbounds float, float* %ptr, i64 3
   %0 = load float, float* %arrayidx, align 4
   %conv = fptosi float %0 to i32
   %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0

 }
 
 define <4 x i32> @fromDiffMemConsDui(i32* nocapture readonly %arr) {
 ; P9BE-LABEL: fromDiffMemConsDui:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    lxv v2, 0(r3)
 ; P9BE-NEXT:    addis r3, r2, .LCPI39_0@toc@ha
 ; P9BE-NEXT:    addi r3, r3, .LCPI39_0@toc@l
-; P9BE-NEXT:    lxv v3, 0(r3)
-; P9BE-NEXT:    vperm v2, v2, v2, v3
+; P9BE-NEXT:    lxv vs0, 0(r3)
+; P9BE-NEXT:    xxperm v2, v2, vs0
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffMemConsDui:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lxvw4x v2, 0, r3
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffMemConsDui:

 ; P9BE-LABEL: fromDiffMemVarDui:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    sldi r4, r4, 2
 ; P9BE-NEXT:    add r3, r3, r4
 ; P9BE-NEXT:    li r4, -12
 ; P9BE-NEXT:    lxvx v2, r3, r4
 ; P9BE-NEXT:    addis r3, r2, .LCPI41_0@toc@ha
 ; P9BE-NEXT:    addi r3, r3, .LCPI41_0@toc@l
-; P9BE-NEXT:    lxv v3, 0(r3)
-; P9BE-NEXT:    vperm v2, v2, v2, v3
+; P9BE-NEXT:    lxv vs0, 0(r3)
+; P9BE-NEXT:    xxperm v2, v2, vs0
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffMemVarDui:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    sldi r4, r4, 2
 ; P9LE-NEXT:    add r3, r3, r4
 ; P9LE-NEXT:    li r4, -12
 ; P9LE-NEXT:    lxvx v2, r3, r4
 ; P9LE-NEXT:    addis r3, r2, .LCPI41_0@toc@ha
 ; P9LE-NEXT:    addi r3, r3, .LCPI41_0@toc@l
-; P9LE-NEXT:    lxv v3, 0(r3)
-; P9LE-NEXT:    vperm v2, v2, v2, v3
+; P9LE-NEXT:    lxv vs0, 0(r3)
+; P9LE-NEXT:    xxperm v2, v2, vs0
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffMemVarDui:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    sldi r4, r4, 2
 ; P8BE-NEXT:    addis r5, r2, .LCPI41_0@toc@ha
 ; P8BE-NEXT:    add r3, r3, r4
 ; P8BE-NEXT:    addi r4, r5, .LCPI41_0@toc@l
 ; P8BE-NEXT:    addi r3, r3, -12
 ; P8BE-NEXT:    lxvw4x v3, 0, r4
 ; P8BE-NEXT:    lxvw4x v2, 0, r3
 ; P8BE-NEXT:    vperm v2, v2, v2, v3
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fromDiffMemVarDui:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    sldi r4, r4, 2
 ; P8LE-NEXT:    addis r5, r2, .LCPI41_0@toc@ha
+; P8LE-NEXT:    sldi r4, r4, 2
+; P8LE-NEXT:    addi r5, r5, .LCPI41_0@toc@l
 ; P8LE-NEXT:    add r3, r3, r4
-; P8LE-NEXT:    addi r4, r5, .LCPI41_0@toc@l
+; P8LE-NEXT:    lxvd2x vs0, 0, r5
 ; P8LE-NEXT:    addi r3, r3, -12
-; P8LE-NEXT:    lxvd2x vs1, 0, r4
-; P8LE-NEXT:    lxvd2x vs0, 0, r3
-; P8LE-NEXT:    xxswapd v3, vs1
-; P8LE-NEXT:    xxswapd v2, vs0
+; P8LE-NEXT:    lxvd2x v2, 0, r3
+; P8LE-NEXT:    xxswapd v3, vs0
 ; P8LE-NEXT:    vperm v2, v2, v2, v3
 ; P8LE-NEXT:    blr
 entry:
   %idxprom = sext i32 %elem to i64
   %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom
   %0 = load i32, i32* %arrayidx, align 4
   %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
   %sub = add nsw i32 %elem, -1
entry:
   %1 = load <4 x float>, <4 x float>* %0, align 4
   %2 = fptoui <4 x float> %1 to <4 x i32>
   ret <4 x i32> %2
 }
 
 define <4 x i32> @fromDiffMemConsDConvftoui(float* nocapture readonly %ptr) {
 ; P9BE-LABEL: fromDiffMemConsDConvftoui:
 ; P9BE:       # %bb.0: # %entry
-; P9BE-NEXT:    lxv v2, 0(r3)
+; P9BE-NEXT:    lxv vs0, 0(r3)
 ; P9BE-NEXT:    addis r3, r2, .LCPI50_0@toc@ha
 ; P9BE-NEXT:    addi r3, r3, .LCPI50_0@toc@l
-; P9BE-NEXT:    lxv v3, 0(r3)
-; P9BE-NEXT:    vperm v2, v2, v2, v3
-; P9BE-NEXT:    xvcvspuxws v2, v2
+; P9BE-NEXT:    lxv vs1, 0(r3)
+; P9BE-NEXT:    xxperm vs0, vs0, vs1
+; P9BE-NEXT:    xvcvspuxws v2, vs0
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffMemConsDConvftoui:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    lxv v2, 0(r3)
+; P9LE-NEXT:    lxv vs0, 0(r3)
 ; P9LE-NEXT:    addis r3, r2, .LCPI50_0@toc@ha
 ; P9LE-NEXT:    addi r3, r3, .LCPI50_0@toc@l
-; P9LE-NEXT:    lxv v3, 0(r3)
-; P9LE-NEXT:    vperm v2, v2, v2, v3
-; P9LE-NEXT:    xvcvspuxws v2, v2
+; P9LE-NEXT:    lxv vs1, 0(r3)
+; P9LE-NEXT:    xxperm vs0, vs0, vs1
+; P9LE-NEXT:    xvcvspuxws v2, vs0
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffMemConsDConvftoui:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    addis r4, r2, .LCPI50_0@toc@ha
 ; P8BE-NEXT:    lxvw4x v2, 0, r3
 ; P8BE-NEXT:    addi r4, r4, .LCPI50_0@toc@l
 ; P8BE-NEXT:    lxvw4x v3, 0, r4
 ; P8BE-NEXT:    vperm v2, v2, v2, v3
 ; P8BE-NEXT:    xvcvspuxws v2, v2
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fromDiffMemConsDConvftoui:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    addis r4, r2, .LCPI50_0@toc@ha
-; P8LE-NEXT:    lxvd2x vs0, 0, r3
+; P8LE-NEXT:    lxvd2x v2, 0, r3
 ; P8LE-NEXT:    addi r4, r4, .LCPI50_0@toc@l
-; P8LE-NEXT:    lxvd2x vs1, 0, r4
-; P8LE-NEXT:    xxswapd v2, vs0
-; P8LE-NEXT:    xxswapd v3, vs1
+; P8LE-NEXT:    lxvd2x vs0, 0, r4
+; P8LE-NEXT:    xxswapd v3, vs0
 ; P8LE-NEXT:    vperm v2, v2, v2, v3
 ; P8LE-NEXT:    xvcvspuxws v2, v2
 ; P8LE-NEXT:    blr
 entry:
   %arrayidx = getelementptr inbounds float, float* %ptr, i64 3
   %0 = load float, float* %arrayidx, align 4
   %conv = fptoui float %0 to i32
   %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0

llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll

 ; CHECK-P9-NEXT:    xxlxor v3, v3, v3
 ; CHECK-P9-NEXT:    vmrghb v2, v3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: testmrglb3:
 ; CHECK-P9-BE:       # %bb.0: # %entry
 ; CHECK-P9-BE-NEXT:    lxsd v2, 0(r3)
 ; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI12_0@toc@ha
-; CHECK-P9-BE-NEXT:    xxlxor v4, v4, v4
+; CHECK-P9-BE-NEXT:    xxlxor vs0, vs0, vs0
 ; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI12_0@toc@l
-; CHECK-P9-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-P9-BE-NEXT:    vperm v2, v4, v2, v3
+; CHECK-P9-BE-NEXT:    lxv vs1, 0(r3)
+; CHECK-P9-BE-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-P9-BE-NEXT:    blr
 ;
 ; CHECK-NOVSX-LABEL: testmrglb3:
 ; CHECK-NOVSX:       # %bb.0: # %entry
 ; CHECK-NOVSX-NEXT:    vxor v2, v2, v2
 ; CHECK-NOVSX-NEXT:    ld r3, 0(r3)
 ; CHECK-NOVSX-NEXT:    addis r4, r2, .LCPI12_0@toc@ha
 ; CHECK-NOVSX-NEXT:    addi r4, r4, .LCPI12_0@toc@l

 ; CHECK-P9-NEXT:    lxv v3, 0(r3)
 ; CHECK-P9-NEXT:    vmrgow v2, v3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: replace_undefs_in_splat:
 ; CHECK-P9-BE:       # %bb.0: # %entry
 ; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI15_0@toc@ha
 ; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI15_0@toc@l
-; CHECK-P9-BE-NEXT:    lxv v3, 0(r3)
+; CHECK-P9-BE-NEXT:    lxv vs1, 0(r3)
 ; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI15_1@toc@ha
 ; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI15_1@toc@l
-; CHECK-P9-BE-NEXT:    lxv v4, 0(r3)
-; CHECK-P9-BE-NEXT:    vperm v2, v2, v4, v3
+; CHECK-P9-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-P9-BE-NEXT:    xxperm vs0, v2, vs1
+; CHECK-P9-BE-NEXT:    xxlor v2, vs0, vs0
 ; CHECK-P9-BE-NEXT:    blr
 ;
 ; CHECK-NOVSX-LABEL: replace_undefs_in_splat:
 ; CHECK-NOVSX:       # %bb.0: # %entry
 ; CHECK-NOVSX-NEXT:    addis r3, r2, .LCPI15_0@toc@ha
 ; CHECK-NOVSX-NEXT:    addis r4, r2, .LCPI15_1@toc@ha
 ; CHECK-NOVSX-NEXT:    addi r3, r3, .LCPI15_0@toc@l
 ; CHECK-NOVSX-NEXT:    lvx v3, 0, r3

llvm/test/CodeGen/PowerPC/extract-and-store.ll

 ; CHECK-BE-NEXT:    stfiwx f0, r5, r4
 ; CHECK-BE-NEXT:    vperm v3, v2, v2, v3
 ; CHECK-BE-NEXT:    stxvw4x vs35, 0, r5
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test_stores_exceed_vec_size:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI16_0@toc@ha
-; CHECK-P9-NEXT:    xxsldwi vs0, vs34, vs34, 1
+; CHECK-P9-NEXT:    xxlor vs1, vs34, vs34
 ; CHECK-P9-NEXT:    addi r3, r3, .LCPI16_0@toc@l
-; CHECK-P9-NEXT:    lxv vs35, 0(r3)
+; CHECK-P9-NEXT:    lxv vs0, 0(r3)
 ; CHECK-P9-NEXT:    li r3, 16
+; CHECK-P9-NEXT:    xxperm vs1, vs34, vs0
+; CHECK-P9-NEXT:    xxsldwi vs0, vs34, vs34, 1
 ; CHECK-P9-NEXT:    stfiwx f0, r5, r3
 ; CHECK-P9-NEXT:    li r3, 20
+; CHECK-P9-NEXT:    stxv vs1, 0(r5)
 ; CHECK-P9-NEXT:    stxsiwx vs34, r5, r3
-; CHECK-P9-NEXT:    vperm v3, v2, v2, v3
-; CHECK-P9-NEXT:    stxv vs35, 0(r5)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: test_stores_exceed_vec_size:
 ; CHECK-P9-BE:       # %bb.0: # %entry
 ; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI16_0@toc@ha
-; CHECK-P9-BE-NEXT:    xxsldwi vs0, vs34, vs34, 1
+; CHECK-P9-BE-NEXT:    xxlor vs1, vs34, vs34
 ; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI16_0@toc@l
-; CHECK-P9-BE-NEXT:    lxv vs35, 0(r3)
+; CHECK-P9-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-P9-BE-NEXT:    li r3, 16
+; CHECK-P9-BE-NEXT:    xxperm vs1, vs34, vs0
+; CHECK-P9-BE-NEXT:    xxsldwi vs0, vs34, vs34, 1
 ; CHECK-P9-BE-NEXT:    stxsiwx vs34, r5, r3
 ; CHECK-P9-BE-NEXT:    li r3, 20
+; CHECK-P9-BE-NEXT:    stxv vs1, 0(r5)
 ; CHECK-P9-BE-NEXT:    stfiwx f0, r5, r3
-; CHECK-P9-BE-NEXT:    vperm v3, v2, v2, v3
-; CHECK-P9-BE-NEXT:    stxv vs35, 0(r5)
 ; CHECK-P9-BE-NEXT:    blr
 entry:
   %vecext = extractelement <4 x i32> %a, i32 2
   store i32 %vecext, i32* %b, align 4
   %vecext1 = extractelement <4 x i32> %a, i32 3
   %arrayidx2 = getelementptr inbounds i32, i32* %b, i64 1
   store i32 %vecext1, i32* %arrayidx2, align 4
   %vecext3 = extractelement <4 x i32> %a, i32 0

llvm/test/CodeGen/PowerPC/load-and-splat.ll

 ;
 ; P9-AIX32-LABEL: test4:
 ; P9-AIX32:       # %bb.0: # %entry
 ; P9-AIX32-NEXT:    lwz r5, 24(r4)
 ; P9-AIX32-NEXT:    lwz r4, 28(r4)
 ; P9-AIX32-NEXT:    stw r4, -16(r1)
 ; P9-AIX32-NEXT:    lwz r4, L..C0(r2) # %const.0
 ; P9-AIX32-NEXT:    stw r5, -32(r1)
-; P9-AIX32-NEXT:    lxv v3, -16(r1)
-; P9-AIX32-NEXT:    lxv v4, -32(r1)
-; P9-AIX32-NEXT:    lxv v2, 0(r4)
-; P9-AIX32-NEXT:    vperm v2, v4, v3, v2
-; P9-AIX32-NEXT:    stxv v2, 0(r3)
+; P9-AIX32-NEXT:    lxv vs1, -16(r1)
+; P9-AIX32-NEXT:    lxv vs2, -32(r1)
+; P9-AIX32-NEXT:    lxv vs0, 0(r4)
+; P9-AIX32-NEXT:    xxperm vs1, vs2, vs0
+; P9-AIX32-NEXT:    stxv vs1, 0(r3)
 ; P9-AIX32-NEXT:    blr
 ;
 ; P8-AIX32-LABEL: test4:
 ; P8-AIX32:       # %bb.0: # %entry
 ; P8-AIX32-NEXT:    lwz r5, L..C0(r2) # %const.0
 ; P8-AIX32-NEXT:    lwz r6, 28(r4)
 ; P8-AIX32-NEXT:    lwz r4, 24(r4)
 ; P8-AIX32-NEXT:    stw r6, -16(r1)

 ; P7-NEXT:    blr
 ;
 ; P9-AIX32-LABEL: test5:
 ; P9-AIX32:       # %bb.0: # %entry
 ; P9-AIX32-NEXT:    lwz r4, 0(r4)
 ; P9-AIX32-NEXT:    srawi r5, r4, 31
 ; P9-AIX32-NEXT:    stw r4, -16(r1)
 ; P9-AIX32-NEXT:    lwz r4, L..C1(r2) # %const.0
-; P9-AIX32-NEXT:    lxv v3, -16(r1)
+; P9-AIX32-NEXT:    lxv vs1, -16(r1)
 ; P9-AIX32-NEXT:    stw r5, -32(r1)
-; P9-AIX32-NEXT:    lxv v4, -32(r1)
-; P9-AIX32-NEXT:    lxv v2, 0(r4)
-; P9-AIX32-NEXT:    vperm v2, v4, v3, v2
-; P9-AIX32-NEXT:    stxv v2, 0(r3)
+; P9-AIX32-NEXT:    lxv vs2, -32(r1)
+; P9-AIX32-NEXT:    lxv vs0, 0(r4)
+; P9-AIX32-NEXT:    xxperm vs1, vs2, vs0
+; P9-AIX32-NEXT:    stxv vs1, 0(r3)
 ; P9-AIX32-NEXT:    blr
 ;
 ; P8-AIX32-LABEL: test5:
 ; P8-AIX32:       # %bb.0: # %entry
 ; P8-AIX32-NEXT:    lwz r5, L..C1(r2) # %const.0
 ; P8-AIX32-NEXT:    lwz r4, 0(r4)
 ; P8-AIX32-NEXT:    stw r4, -16(r1)
 ; P8-AIX32-NEXT:    srawi r4, r4, 31

 ; P7-NEXT:    stxvd2x vs0, 0, r3
 ; P7-NEXT:    blr
 ;
 ; P9-AIX32-LABEL: test6:
 ; P9-AIX32:       # %bb.0: # %entry
 ; P9-AIX32-NEXT:    lwz r4, 0(r4)
 ; P9-AIX32-NEXT:    li r5, 0
 ; P9-AIX32-NEXT:    stw r5, -32(r1)
-; P9-AIX32-NEXT:    lxv v3, -32(r1)
+; P9-AIX32-NEXT:    lxv vs1, -32(r1)
 ; P9-AIX32-NEXT:    stw r4, -16(r1)
 ; P9-AIX32-NEXT:    lwz r4, L..C2(r2) # %const.0
-; P9-AIX32-NEXT:    lxv v4, -16(r1)
-; P9-AIX32-NEXT:    lxv v2, 0(r4)
-; P9-AIX32-NEXT:    vperm v2, v3, v4, v2
-; P9-AIX32-NEXT:    stxv v2, 0(r3)
+; P9-AIX32-NEXT:    lxv vs2, -16(r1)
+; P9-AIX32-NEXT:    lxv vs0, 0(r4)
+; P9-AIX32-NEXT:    xxperm vs2, vs1, vs0
+; P9-AIX32-NEXT:    stxv vs2, 0(r3)
 ; P9-AIX32-NEXT:    blr
 ;
 ; P8-AIX32-LABEL: test6:
 ; P8-AIX32:       # %bb.0: # %entry
 ; P8-AIX32-NEXT:    lwz r6, L..C2(r2) # %const.0
 ; P8-AIX32-NEXT:    lwz r4, 0(r4)
 ; P8-AIX32-NEXT:    li r5, 0
 ; P8-AIX32-NEXT:    stw r5, -32(r1)

llvm/test/CodeGen/PowerPC/load-shuffle-and-shuffle-store.ll

 ; CHECK-P8-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-BE-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: load_swap10:
 ; CHECK-P9-BE:       # %bb.0:
 ; CHECK-P9-BE-NEXT:    lxv v2, 0(r3)
 ; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
 ; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI2_0@toc@l
-; CHECK-P9-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-P9-BE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-P9-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-P9-BE-NEXT:    xxperm v2, v2, vs0
 ; CHECK-P9-BE-NEXT:    blr
   %v1 = load <4 x i32>, <4 x i32>* %vp1
   %v2 = load <4 x i32>, <4 x i32>* %vp2
   %v3 = shufflevector <4 x i32> %v1, <4 x i32> %v2, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
   ret <4 x i32> %v3
 }
 
 define <4 x i32> @load_swap11(<4 x i32>* %vp1, <4 x i32>* %vp2) {

 ; CHECK-P8-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-BE-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: load_swap11:
 ; CHECK-P9-BE:       # %bb.0:
 ; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
 ; CHECK-P9-BE-NEXT:    lxv v2, 0(r4)
 ; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI3_0@toc@l
-; CHECK-P9-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-P9-BE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-P9-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-P9-BE-NEXT:    xxperm v2, v2, vs0
 ; CHECK-P9-BE-NEXT:    blr
   %v1 = load <4 x i32>, <4 x i32>* %vp1
   %v2 = load <4 x i32>, <4 x i32>* %vp2
   %v3 = shufflevector <4 x i32> %v1, <4 x i32> %v2, <4 x i32> <i32 7, i32 6, i32 5, i32 4>
   ret <4 x i32> %v3
 }
 
 define <8 x i16> @load_swap20(<8 x i16>* %vp1, <8 x i16>* %vp2){

 ; CHECK-P8-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-BE-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: load_swap20:
 ; CHECK-P9-BE:       # %bb.0:
 ; CHECK-P9-BE-NEXT:    lxv v2, 0(r3)
 ; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
 ; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI4_0@toc@l
-; CHECK-P9-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-P9-BE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-P9-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-P9-BE-NEXT:    xxperm v2, v2, vs0
 ; CHECK-P9-BE-NEXT:    blr
   %v1 = load <8 x i16>, <8 x i16>* %vp1
   %v2 = load <8 x i16>, <8 x i16>* %vp2
   %v3 = shufflevector <8 x i16> %v1, <8 x i16> %v2, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
   ret <8 x i16> %v3
 }
 
 define <8 x i16> @load_swap21(<8 x i16>* %vp1, <8 x i16>* %vp2){

 ; CHECK-P8-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-BE-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: load_swap21:
 ; CHECK-P9-BE:       # %bb.0:
 ; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
 ; CHECK-P9-BE-NEXT:    lxv v2, 0(r4)
 ; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI5_0@toc@l
-; CHECK-P9-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-P9-BE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-P9-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-P9-BE-NEXT:    xxperm v2, v2, vs0
 ; CHECK-P9-BE-NEXT:    blr
   %v1 = load <8 x i16>, <8 x i16>* %vp1
   %v2 = load <8 x i16>, <8 x i16>* %vp2
   %v3 = shufflevector <8 x i16> %v1, <8 x i16> %v2, <8 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
   ret <8 x i16> %v3
 }
 
 define <16 x i8> @load_swap30(<16 x i8>* %vp1, <16 x i8>* %vp2){

 ; CHECK-P8-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-BE-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: load_swap50:
 ; CHECK-P9-BE:       # %bb.0:
 ; CHECK-P9-BE-NEXT:    lxv v2, 0(r3)
 ; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI9_0@toc@ha
 ; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI9_0@toc@l
-; CHECK-P9-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-P9-BE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-P9-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-P9-BE-NEXT:    xxperm v2, v2, vs0
 ; CHECK-P9-BE-NEXT:    blr
   %v1 = load <4 x float>, <4 x float>* %vp1
   %v2 = load <4 x float>, <4 x float>* %vp2
   %v3 = shufflevector <4 x float> %v1, <4 x float> %v2, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
   ret <4 x float> %v3
 }
 
 define <4 x float> @load_swap51(<4 x float>* %vp1, <4 x float>* %vp2) {

 ; CHECK-P8-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-BE-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: load_swap51:
 ; CHECK-P9-BE:       # %bb.0:
 ; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI10_0@toc@ha
 ; CHECK-P9-BE-NEXT:    lxv v2, 0(r4)
 ; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI10_0@toc@l
-; CHECK-P9-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-P9-BE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-P9-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-P9-BE-NEXT:    xxperm v2, v2, vs0
 ; CHECK-P9-BE-NEXT:    blr
   %v1 = load <4 x float>, <4 x float>* %vp1
   %v2 = load <4 x float>, <4 x float>* %vp2
   %v3 = shufflevector <4 x float> %v1, <4 x float> %v2, <4 x i32> <i32 7, i32 6, i32 5, i32 4>
   ret <4 x float> %v3
 }
 
 define void @swap_store00(<2 x i64> %v1, <2 x i64> %v2, <2 x i64>* %vp) {

 ; CHECK-P8-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-BE-NEXT:    stxvw4x v2, 0, r7
 ; CHECK-P8-BE-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: swap_store10:
 ; CHECK-P9-BE:       # %bb.0:
 ; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI13_0@toc@ha
 ; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI13_0@toc@l
-; CHECK-P9-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-P9-BE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-P9-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-P9-BE-NEXT:    xxperm v2, v2, vs0
 ; CHECK-P9-BE-NEXT:    stxv v2, 0(r7)
 ; CHECK-P9-BE-NEXT:    blr
   %v3 = shufflevector <4 x i32> %v1, <4 x i32> %v2, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
   store <4 x i32> %v3, <4 x i32>* %vp
   ret void
 }
 
 define void @swap_store11(<4 x i32> %v1, <4 x i32> %v2, <4 x i32>* %vp) {

 ; CHECK-P8-BE-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P8-BE-NEXT:    stxvw4x v2, 0, r7
 ; CHECK-P8-BE-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: swap_store11:
 ; CHECK-P9-BE:       # %bb.0:
 ; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI14_0@toc@ha
 ; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI14_0@toc@l
-; CHECK-P9-BE-NEXT:    lxv v2, 0(r3)
-; CHECK-P9-BE-NEXT:    vperm v2, v3, v3, v2
-; CHECK-P9-BE-NEXT:    stxv v2, 0(r7)
+; CHECK-P9-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-P9-BE-NEXT:    xxperm v3, v3, vs0
+; CHECK-P9-BE-NEXT:    stxv v3, 0(r7)
 ; CHECK-P9-BE-NEXT:    blr
   %v3 = shufflevector <4 x i32> %v1, <4 x i32> %v2, <4 x i32> <i32 7, i32 6, i32 5, i32 4>
   store <4 x i32> %v3, <4 x i32>* %vp
   ret void
 }
 
 define void @swap_store20(<8 x i16> %v1, <8 x i16> %v2, <8 x i16>* %vp) {
 ; CHECK-P8-LABEL: swap_store20:

 ; CHECK-P8-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-BE-NEXT:    stxvw4x v2, 0, r7
 ; CHECK-P8-BE-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: swap_store20:
 ; CHECK-P9-BE:       # %bb.0:
 ; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI15_0@toc@ha
 ; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI15_0@toc@l
-; CHECK-P9-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-P9-BE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-P9-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-P9-BE-NEXT:    xxperm v2, v2, vs0
 ; CHECK-P9-BE-NEXT:    stxv v2, 0(r7)
 ; CHECK-P9-BE-NEXT:    blr
   %v3 = shufflevector <8 x i16> %v1, <8 x i16> %v2, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
   store <8 x i16> %v3, <8 x i16>* %vp
   ret void
 }
 
 define void @swap_store21(<8 x i16> %v1, <8 x i16> %v2, <8 x i16>* %vp) {

 ; CHECK-P8-BE-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P8-BE-NEXT:    stxvw4x v2, 0, r7
 ; CHECK-P8-BE-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: swap_store21:
 ; CHECK-P9-BE:       # %bb.0:
 ; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI16_0@toc@ha
 ; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI16_0@toc@l
-; CHECK-P9-BE-NEXT:    lxv v2, 0(r3)
-; CHECK-P9-BE-NEXT:    vperm v2, v3, v3, v2
-; CHECK-P9-BE-NEXT:    stxv v2, 0(r7)
+; CHECK-P9-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-P9-BE-NEXT:    xxperm v3, v3, vs0
+; CHECK-P9-BE-NEXT:    stxv v3, 0(r7)
 ; CHECK-P9-BE-NEXT:    blr
   %v3 = shufflevector <8 x i16> %v1, <8 x i16> %v2, <8 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
   store <8 x i16> %v3, <8 x i16>* %vp
   ret void
 }
 
 define void @swap_store30(<16 x i8> %v1, <16 x i8> %v2, <16 x i8>* %vp) {
 ; CHECK-P8-LABEL: swap_store30:

 ; CHECK-P8-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-BE-NEXT:    stxvw4x v2, 0, r7
 ; CHECK-P8-BE-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: swap_store50:
 ; CHECK-P9-BE:       # %bb.0:
 ; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI21_0@toc@ha
 ; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI21_0@toc@l
-; CHECK-P9-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-P9-BE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-P9-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-P9-BE-NEXT:    xxperm v2, v2, vs0
 ; CHECK-P9-BE-NEXT:    stxv v2, 0(r7)
 ; CHECK-P9-BE-NEXT:    blr
   %v3 = shufflevector <4 x float> %v1, <4 x float> %v2, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
   store <4 x float> %v3, <4 x float>* %vp
   ret void
 }
 
 define void @swap_store51(<4 x float> %v1, <4 x float> %v2, <4 x float>* %vp) {

 ; CHECK-P8-BE-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P8-BE-NEXT:    stxvw4x v2, 0, r7
 ; CHECK-P8-BE-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: swap_store51:
 ; CHECK-P9-BE:       # %bb.0:
 ; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI22_0@toc@ha
 ; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI22_0@toc@l
-; CHECK-P9-BE-NEXT:    lxv v2, 0(r3)
-; CHECK-P9-BE-NEXT:    vperm v2, v3, v3, v2
-; CHECK-P9-BE-NEXT:    stxv v2, 0(r7)
+; CHECK-P9-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-P9-BE-NEXT:    xxperm v3, v3, vs0
+; CHECK-P9-BE-NEXT:    stxv v3, 0(r7)
 ; CHECK-P9-BE-NEXT:    blr
   %v3 = shufflevector <4 x float> %v1, <4 x float> %v2, <4 x i32> <i32 7, i32 6, i32 5, i32 4>
   store <4 x float> %v3, <4 x float>* %vp
   ret void
 }

llvm/test/CodeGen/PowerPC/p10-vector-rotate.ll

entry:
   %tmp = tail call <1 x i128> @llvm.ppc.altivec.vrlqmi(<1 x i128> %a, <1 x i128> %c, <1 x i128> %b)
   ret <1 x i128> %tmp
 }
 
 ; Function Attrs: nounwind readnone
 define <1 x i128> @test_vrlqnm(<1 x i128> %a, <1 x i128> %b, <1 x i128> %c) {
 ; CHECK-LE-LABEL: test_vrlqnm:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    plxv v5, .LCPI4_0@PCREL(0), 1
-; CHECK-LE-NEXT:    vperm v3, v4, v3, v5
+; CHECK-LE-NEXT:    plxv vs0, .LCPI4_0@PCREL(0), 1
+; CHECK-LE-NEXT:    xxperm v3, v4, vs0
 ; CHECK-LE-NEXT:    vrlqnm v2, v2, v3
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test_vrlqnm:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI4_0@toc@l
-; CHECK-BE-NEXT:    lxv v5, 0(r3)
-; CHECK-BE-NEXT:    vperm v3, v3, v4, v5
-; CHECK-BE-NEXT:    vrlqnm v2, v2, v3
+; CHECK-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-BE-NEXT:    xxperm v4, v3, vs0
+; CHECK-BE-NEXT:    vrlqnm v2, v2, v4
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast <1 x i128> %b to <16 x i8>
   %1 = bitcast <1 x i128> %c to <16 x i8>
   %shuffle.i = shufflevector <16 x i8> %0, <16 x i8> %1, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 16, i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
   %d = bitcast <16 x i8> %shuffle.i to <1 x i128>
   %tmp = tail call <1 x i128> @llvm.ppc.altivec.vrlqnm(<1 x i128> %a, <1 x i128> %d)
   ret <1 x i128> %tmp
 }
 
 ; Function Attrs: nounwind readnone
 declare <1 x i128> @llvm.ppc.altivec.vrlqmi(<1 x i128>, <1 x i128>, <1 x i128>)
 
 ; Function Attrs: nounwind readnone
 declare <1 x i128> @llvm.ppc.altivec.vrlqnm(<1 x i128>, <1 x i128>)

llvm/test/CodeGen/PowerPC/p9-vinsert-vextract.ll

 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vinserth 2, 2, 14
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_halfword_0_4:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI16_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI16_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 0, 0(3)
+; CHECK-BE-NEXT:    xxperm 34, 34, 0
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 4, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_1_3(<8 x i16> %a) {
 ; CHECK-LABEL: shuffle_vector_halfword_1_3:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LCPI17_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI17_0@toc@l
-; CHECK-NEXT:    lxv 35, 0(3)
-; CHECK-NEXT:    vperm 2, 2, 2, 3
+; CHECK-NEXT:    lxv 0, 0(3)
+; CHECK-NEXT:    xxperm 34, 34, 0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_halfword_1_3:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vinserth 2, 2, 2
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 3, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_2_3(<8 x i16> %a) {
 ; CHECK-LABEL: shuffle_vector_halfword_2_3:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LCPI18_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI18_0@toc@l
-; CHECK-NEXT:    lxv 35, 0(3)
-; CHECK-NEXT:    vperm 2, 2, 2, 3
+; CHECK-NEXT:    lxv 0, 0(3)
+; CHECK-NEXT:    xxperm 34, 34, 0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_halfword_2_3:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vinserth 2, 2, 4
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 3, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_3_4(<8 x i16> %a) {
 ; CHECK-LABEL: shuffle_vector_halfword_3_4:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vinserth 2, 2, 8
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_halfword_3_4:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI19_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI19_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 0, 0(3)
+; CHECK-BE-NEXT:    xxperm 34, 34, 0
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 4, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_4_3(<8 x i16> %a) {
 ; CHECK-LABEL: shuffle_vector_halfword_4_3:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LCPI20_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI20_0@toc@l
-; CHECK-NEXT:    lxv 35, 0(3)
-; CHECK-NEXT:    vperm 2, 2, 2, 3
+; CHECK-NEXT:    lxv 0, 0(3)
+; CHECK-NEXT:    xxperm 34, 34, 0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_halfword_4_3:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vinserth 2, 2, 8
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 3, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_5_3(<8 x i16> %a) {
 ; CHECK-LABEL: shuffle_vector_halfword_5_3:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LCPI21_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI21_0@toc@l
-; CHECK-NEXT:    lxv 35, 0(3)
-; CHECK-NEXT:    vperm 2, 2, 2, 3
+; CHECK-NEXT:    lxv 0, 0(3)
+; CHECK-NEXT:    xxperm 34, 34, 0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_halfword_5_3:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vinserth 2, 2, 10
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 3, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_6_4(<8 x i16> %a) {
 ; CHECK-LABEL: shuffle_vector_halfword_6_4:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vinserth 2, 2, 2
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_halfword_6_4:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI22_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI22_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 0, 0(3)
+; CHECK-BE-NEXT:    xxperm 34, 34, 0
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 4, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_7_4(<8 x i16> %a) {
 ; CHECK-LABEL: shuffle_vector_halfword_7_4:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vinserth 2, 2, 0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_halfword_7_4:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI23_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI23_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 0, 0(3)
+; CHECK-BE-NEXT:    xxperm 34, 34, 0
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 4>
   ret <8 x i16> %vecins
 }
 
 ; The following testcases take one byte element from the second vector and
 ; inserts it at various locations in the first vector

 ; The following testcases use the same vector in both arguments of the
 ; shufflevector.  If byte element 7 in BE mode(or 8 in LE mode) is the one
 ; we're attempting to insert, then we can use the vector insert instruction
 define <16 x i8> @shuffle_vector_byte_0_7(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_0_7:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LCPI56_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI56_0@toc@l
-; CHECK-NEXT:    lxv 35, 0(3)
-; CHECK-NEXT:    vperm 2, 2, 2, 3
+; CHECK-NEXT:    lxv 0, 0(3)
+; CHECK-NEXT:    xxperm 34, 34, 0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_0_7:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vinsertb 2, 2, 0
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 7, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_1_8(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_1_8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vinsertb 2, 2, 14
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_1_8:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI57_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI57_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 0, 0(3)
+; CHECK-BE-NEXT:    xxperm 34, 34, 0
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 8, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_2_8(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_2_8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vinsertb 2, 2, 13
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_2_8:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI58_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI58_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 0, 0(3)
+; CHECK-BE-NEXT:    xxperm 34, 34, 0
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 8, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_3_7(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_3_7:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LCPI59_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI59_0@toc@l
-; CHECK-NEXT:    lxv 35, 0(3)
-; CHECK-NEXT:    vperm 2, 2, 2, 3
+; CHECK-NEXT:    lxv 0, 0(3)
+; CHECK-NEXT:    xxperm 34, 34, 0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_3_7:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vinsertb 2, 2, 3
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 7, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_4_7(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_4_7:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LCPI60_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI60_0@toc@l
-; CHECK-NEXT:    lxv 35, 0(3)
-; CHECK-NEXT:    vperm 2, 2, 2, 3
+; CHECK-NEXT:    lxv 0, 0(3)
+; CHECK-NEXT:    xxperm 34, 34, 0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_4_7:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vinsertb 2, 2, 4
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 7, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_5_8(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_5_8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vinsertb 2, 2, 10
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_5_8:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI61_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI61_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 0, 0(3)
+; CHECK-BE-NEXT:    xxperm 34, 34, 0
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 8, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_6_8(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_6_8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vinsertb 2, 2, 9
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_6_8:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI62_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI62_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 0, 0(3)
+; CHECK-BE-NEXT:    xxperm 34, 34, 0
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_7_8(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_7_8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vinsertb 2, 2, 8
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_7_8:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI63_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI63_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 0, 0(3)
+; CHECK-BE-NEXT:    xxperm 34, 34, 0
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 8, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_8_7(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_8_7:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LCPI64_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI64_0@toc@l
-; CHECK-NEXT:    lxv 35, 0(3)
-; CHECK-NEXT:    vperm 2, 2, 2, 3
+; CHECK-NEXT:    lxv 0, 0(3)
+; CHECK-NEXT:    xxperm 34, 34, 0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_8_7:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vinsertb 2, 2, 8
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 7, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_9_7(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_9_7:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LCPI65_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI65_0@toc@l
-; CHECK-NEXT:    lxv 35, 0(3)
-; CHECK-NEXT:    vperm 2, 2, 2, 3
+; CHECK-NEXT:    lxv 0, 0(3)
+; CHECK-NEXT:    xxperm 34, 34, 0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_9_7:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vinsertb 2, 2, 9
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 7, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_10_7(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_10_7:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LCPI66_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI66_0@toc@l
-; CHECK-NEXT:    lxv 35, 0(3)
-; CHECK-NEXT:    vperm 2, 2, 2, 3
+; CHECK-NEXT:    lxv 0, 0(3)
+; CHECK-NEXT:    xxperm 34, 34, 0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_10_7:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vinsertb 2, 2, 10
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 7, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_11_8(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_11_8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vinsertb 2, 2, 4
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_11_8:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI67_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI67_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 0, 0(3)
+; CHECK-BE-NEXT:    xxperm 34, 34, 0
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 8, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_12_8(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_12_8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vinsertb 2, 2, 3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_12_8:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI68_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI68_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 0, 0(3)
+; CHECK-BE-NEXT:    xxperm 34, 34, 0
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 8, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_13_7(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_13_7:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LCPI69_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI69_0@toc@l
-; CHECK-NEXT:    lxv 35, 0(3)
-; CHECK-NEXT:    vperm 2, 2, 2, 3
+; CHECK-NEXT:    lxv 0, 0(3)
+; CHECK-NEXT:    xxperm 34, 34, 0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_13_7:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vinsertb 2, 2, 13
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 7, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_14_7(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_14_7:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LCPI70_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI70_0@toc@l
-; CHECK-NEXT:    lxv 35, 0(3)
-; CHECK-NEXT:    vperm 2, 2, 2, 3
+; CHECK-NEXT:    lxv 0, 0(3)
+; CHECK-NEXT:    xxperm 34, 34, 0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_14_7:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vinsertb 2, 2, 14
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 7, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_15_8(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_15_8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vinsertb 2, 2, 0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_15_8:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI71_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI71_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 0, 0(3)
+; CHECK-BE-NEXT:    xxperm 34, 34, 0
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 8>
   ret <16 x i8> %vecins
 }
 
 ; The following tests try to insert one halfword element into the vector.  We
 ; should always be using the 'vinserth' instruction.

llvm/test/CodeGen/PowerPC/ppc-shufflevector-combine.ll

 ; RUN:    | FileCheck %s --check-prefix=BE-32
 
 
 ; Function Attrs: nounwind
 define dso_local <4 x i16> @shufflevector_combine(<4 x i32> %0) #0 {
 ; AIX-LABEL: shufflevector_combine:
 ; AIX:       # %bb.0: # %newFuncRoot
 ; AIX-NEXT:    ld 3, L..C0(2) # %const.0
-; AIX-NEXT:    xxlxor 36, 36, 36
-; AIX-NEXT:    lxv 35, 0(3)
+; AIX-NEXT:    xxlxor 1, 1, 1
+; AIX-NEXT:    lxv 0, 0(3)
 ; AIX-NEXT:    li 3, 0
-; AIX-NEXT:    vperm 2, 4, 2, 3
+; AIX-NEXT:    xxperm 34, 1, 0
 ; AIX-NEXT:    vinsw 2, 3, 8
 ; AIX-NEXT:    vpkuwum 2, 2, 2
 ; AIX-NEXT:    blr
 ;
 ; AIX-32-LABEL: shufflevector_combine:
 ; AIX-32:       # %bb.0: # %newFuncRoot
 ; AIX-32-NEXT:    lwz 3, L..C0(2) # %const.0
-; AIX-32-NEXT:    xxlxor 36, 36, 36
-; AIX-32-NEXT:    lxv 35, 0(3)
+; AIX-32-NEXT:    xxlxor 1, 1, 1
+; AIX-32-NEXT:    lxv 0, 0(3)
 ; AIX-32-NEXT:    li 3, 0
-; AIX-32-NEXT:    vperm 2, 4, 2, 3
+; AIX-32-NEXT:    xxperm 34, 1, 0
 ; AIX-32-NEXT:    vinsw 2, 3, 8
 ; AIX-32-NEXT:    vpkuwum 2, 2, 2
 ; AIX-32-NEXT:    blr
 ;
 ; LE-LABEL: shufflevector_combine:
 ; LE:       # %bb.0: # %newFuncRoot
-; LE-NEXT:    plxv v3, .LCPI0_0@PCREL(0), 1
-; LE-NEXT:    xxlxor v4, v4, v4
+; LE-NEXT:    plxv vs0, .LCPI0_0@PCREL(0), 1
+; LE-NEXT:    xxlxor v3, v3, v3
 ; LE-NEXT:    li r3, 0
-; LE-NEXT:    vperm v2, v2, v4, v3
-; LE-NEXT:    vinsw v2, r3, 4
-; LE-NEXT:    vpkuwum v2, v2, v2
+; LE-NEXT:    xxperm v3, v2, vs0
+; LE-NEXT:    vinsw v3, r3, 4
+; LE-NEXT:    vpkuwum v2, v3, v3
 ; LE-NEXT:    blr
 ;
 ; LE-32-LABEL: shufflevector_combine:
 ; LE-32:       # %bb.0: # %newFuncRoot
 ; LE-32-NEXT:    li r3, .LCPI0_0@l
 ; LE-32-NEXT:    lis r4, .LCPI0_0@ha
-; LE-32-NEXT:    xxlxor v4, v4, v4
-; LE-32-NEXT:    lxvx v3, r4, r3
+; LE-32-NEXT:    xxlxor v3, v3, v3
+; LE-32-NEXT:    lxvx vs0, r4, r3
 ; LE-32-NEXT:    li r3, 0
-; LE-32-NEXT:    vperm v2, v2, v4, v3
-; LE-32-NEXT:    vinsw v2, r3, 4
-; LE-32-NEXT:    vpkuwum v2, v2, v2
+; LE-32-NEXT:    xxperm v3, v2, vs0
+; LE-32-NEXT:    vinsw v3, r3, 4
+; LE-32-NEXT:    vpkuwum v2, v3, v3
 ; LE-32-NEXT:    blr
 ;
 ; BE-LABEL: shufflevector_combine:
 ; BE:       # %bb.0: # %newFuncRoot
 ; BE-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
-; BE-NEXT:    xxlxor v4, v4, v4
+; BE-NEXT:    xxlxor vs0, vs0, vs0
 ; BE-NEXT:    addi r3, r3, .LCPI0_0@toc@l
-; BE-NEXT:    lxv v3, 0(r3)
+; BE-NEXT:    lxv vs1, 0(r3)
 ; BE-NEXT:    li r3, 0
-; BE-NEXT:    vperm v2, v4, v2, v3
+; BE-NEXT:    xxperm v2, vs0, vs1
 ; BE-NEXT:    vinsw v2, r3, 8
 ; BE-NEXT:    vpkuwum v2, v2, v2
 ; BE-NEXT:    blr
 ;
 ; BE-32-LABEL: shufflevector_combine:
 ; BE-32:       # %bb.0: # %newFuncRoot
 ; BE-32-NEXT:    li r3, .LCPI0_0@l
 ; BE-32-NEXT:    lis r4, .LCPI0_0@ha
-; BE-32-NEXT:    xxlxor v4, v4, v4
-; BE-32-NEXT:    lxvx v3, r4, r3
+; BE-32-NEXT:    xxlxor vs1, vs1, vs1
+; BE-32-NEXT:    lxvx vs0, r4, r3
 ; BE-32-NEXT:    li r3, 0
-; BE-32-NEXT:    vperm v2, v4, v2, v3
+; BE-32-NEXT:    xxperm v2, vs1, vs0
 ; BE-32-NEXT:    vinsw v2, r3, 8
 ; BE-32-NEXT:    vpkuwum v2, v2, v2
 ; BE-32-NEXT:    blr
 newFuncRoot:
   %1 = shufflevector <4 x i32> zeroinitializer, <4 x i32> %0, <4 x i32> <i32 0, i32 7, i32 undef, i32 6>
   %2 = insertelement <4 x i32> %1, i32 0, i64 2
   %3 = trunc <4 x i32> %2 to <4 x i16>
   ret <4 x i16> %3
 }
 
 attributes #0 = { nounwind }

llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll

 ; CHECK-PWR9-BE-NEXT:    clrlwi r9, r9, 24
 ; CHECK-PWR9-BE-NEXT:    sub r9, r10, r9
 ; CHECK-PWR9-BE-NEXT:    srawi r10, r9, 31
 ; CHECK-PWR9-BE-NEXT:    xor r9, r9, r10
 ; CHECK-PWR9-BE-NEXT:    sub r9, r9, r10
 ; CHECK-PWR9-BE-NEXT:    li r10, 7
 ; CHECK-PWR9-BE-NEXT:    vextublx r11, r10, v2
 ; CHECK-PWR9-BE-NEXT:    vextublx r10, r10, v3
+; CHECK-PWR9-BE-NEXT:    mtfprwz f2, r9
 ; CHECK-PWR9-BE-NEXT:    clrlwi r11, r11, 24
 ; CHECK-PWR9-BE-NEXT:    clrlwi r10, r10, 24
 ; CHECK-PWR9-BE-NEXT:    sub r10, r11, r10
 ; CHECK-PWR9-BE-NEXT:    srawi r11, r10, 31
 ; CHECK-PWR9-BE-NEXT:    xor r10, r10, r11
 ; CHECK-PWR9-BE-NEXT:    sub r10, r10, r11
 ; CHECK-PWR9-BE-NEXT:    li r11, 8
 ; CHECK-PWR9-BE-NEXT:    vextublx r12, r11, v2
 ; CHECK-PWR9-BE-NEXT:    vextublx r11, r11, v3
 ; CHECK-PWR9-BE-NEXT:    clrlwi r12, r12, 24
 ; CHECK-PWR9-BE-NEXT:    clrlwi r11, r11, 24
 ; CHECK-PWR9-BE-NEXT:    sub r11, r12, r11
 ; CHECK-PWR9-BE-NEXT:    srawi r12, r11, 31
 ; CHECK-PWR9-BE-NEXT:    xor r11, r11, r12
 ; CHECK-PWR9-BE-NEXT:    sub r11, r11, r12
 ; CHECK-PWR9-BE-NEXT:    li r12, 9
 ; CHECK-PWR9-BE-NEXT:    vextublx r0, r12, v2
 ; CHECK-PWR9-BE-NEXT:    vextublx r12, r12, v3
-; CHECK-PWR9-BE-NEXT:    mtvsrwz v0, r11
 ; CHECK-PWR9-BE-NEXT:    clrlwi r0, r0, 24
 ; CHECK-PWR9-BE-NEXT:    clrlwi r12, r12, 24
 ; CHECK-PWR9-BE-NEXT:    sub r12, r0, r12
 ; CHECK-PWR9-BE-NEXT:    srawi r0, r12, 31
 ; CHECK-PWR9-BE-NEXT:    xor r12, r12, r0
 ; CHECK-PWR9-BE-NEXT:    sub r12, r12, r0
 ; CHECK-PWR9-BE-NEXT:    li r0, 10
 ; CHECK-PWR9-BE-NEXT:    vextublx r30, r0, v2
 ; CHECK-PWR9-BE-NEXT:    vextublx r0, r0, v3
+; CHECK-PWR9-BE-NEXT:    mtvsrwz v4, r12
 ; CHECK-PWR9-BE-NEXT:    clrlwi r30, r30, 24
 ; CHECK-PWR9-BE-NEXT:    clrlwi r0, r0, 24
 ; CHECK-PWR9-BE-NEXT:    sub r0, r30, r0
 ; CHECK-PWR9-BE-NEXT:    srawi r30, r0, 31
 ; CHECK-PWR9-BE-NEXT:    xor r0, r0, r30
 ; CHECK-PWR9-BE-NEXT:    sub r0, r0, r30
 ; CHECK-PWR9-BE-NEXT:    li r30, 11
 ; CHECK-PWR9-BE-NEXT:    vextublx r29, r30, v2

 ; CHECK-PWR9-BE-NEXT:    clrlwi r29, r29, 24
 ; CHECK-PWR9-BE-NEXT:    sub r29, r28, r29
 ; CHECK-PWR9-BE-NEXT:    srawi r28, r29, 31
 ; CHECK-PWR9-BE-NEXT:    xor r29, r29, r28
 ; CHECK-PWR9-BE-NEXT:    sub r29, r29, r28
 ; CHECK-PWR9-BE-NEXT:    li r28, 13
 ; CHECK-PWR9-BE-NEXT:    vextublx r27, r28, v2
 ; CHECK-PWR9-BE-NEXT:    vextublx r28, r28, v3
-; CHECK-PWR9-BE-NEXT:    mtvsrwz v5, r29
-; CHECK-PWR9-BE-NEXT:    ld r29, -24(r1) # 8-byte Folded Reload
 ; CHECK-PWR9-BE-NEXT:    clrlwi r27, r27, 24
 ; CHECK-PWR9-BE-NEXT:    clrlwi r28, r28, 24
 ; CHECK-PWR9-BE-NEXT:    sub r28, r27, r28
 ; CHECK-PWR9-BE-NEXT:    srawi r27, r28, 31
 ; CHECK-PWR9-BE-NEXT:    xor r28, r28, r27
 ; CHECK-PWR9-BE-NEXT:    sub r28, r28, r27
 ; CHECK-PWR9-BE-NEXT:    li r27, 14
 ; CHECK-PWR9-BE-NEXT:    vextublx r26, r27, v2
 ; CHECK-PWR9-BE-NEXT:    vextublx r27, r27, v3
 ; CHECK-PWR9-BE-NEXT:    clrlwi r26, r26, 24
 ; CHECK-PWR9-BE-NEXT:    clrlwi r27, r27, 24
 ; CHECK-PWR9-BE-NEXT:    sub r27, r26, r27
 ; CHECK-PWR9-BE-NEXT:    srawi r26, r27, 31
 ; CHECK-PWR9-BE-NEXT:    xor r27, r27, r26
 ; CHECK-PWR9-BE-NEXT:    sub r27, r27, r26
 ; CHECK-PWR9-BE-NEXT:    li r26, 15
 ; CHECK-PWR9-BE-NEXT:    vextublx r25, r26, v2
 ; CHECK-PWR9-BE-NEXT:    vextublx r26, r26, v3
-; CHECK-PWR9-BE-NEXT:    mtvsrwz v3, r27
+; CHECK-PWR9-BE-NEXT:    mtfprwz f0, r27
 ; CHECK-PWR9-BE-NEXT:    addis r27, r2, .LCPI9_0@toc@ha
+; CHECK-PWR9-BE-NEXT:    mtvsrwz v3, r28
 ; CHECK-PWR9-BE-NEXT:    addi r27, r27, .LCPI9_0@toc@l
 ; CHECK-PWR9-BE-NEXT:    clrlwi r25, r25, 24
 ; CHECK-PWR9-BE-NEXT:    clrlwi r26, r26, 24
-; CHECK-PWR9-BE-NEXT:    lxv v4, 0(r27)
-; CHECK-PWR9-BE-NEXT:    ld r27, -40(r1) # 8-byte Folded Reload
+; CHECK-PWR9-BE-NEXT:    lxv vs1, 0(r27)
 ; CHECK-PWR9-BE-NEXT:    sub r26, r25, r26
 ; CHECK-PWR9-BE-NEXT:    srawi r25, r26, 31
 ; CHECK-PWR9-BE-NEXT:    xor r26, r26, r25
 ; CHECK-PWR9-BE-NEXT:    sub r26, r26, r25
-; CHECK-PWR9-BE-NEXT:    ld r25, -56(r1) # 8-byte Folded Reload
 ; CHECK-PWR9-BE-NEXT:    mtvsrwz v2, r26
-; CHECK-PWR9-BE-NEXT:    ld r26, -48(r1) # 8-byte Folded Reload
-; CHECK-PWR9-BE-NEXT:    vperm v2, v3, v2, v4
-; CHECK-PWR9-BE-NEXT:    mtvsrwz v3, r28
-; CHECK-PWR9-BE-NEXT:    ld r28, -32(r1) # 8-byte Folded Reload
-; CHECK-PWR9-BE-NEXT:    vperm v3, v5, v3, v4
-; CHECK-PWR9-BE-NEXT:    mtvsrwz v5, r0
+; CHECK-PWR9-BE-NEXT:    xxperm v2, vs0, vs1
+; CHECK-PWR9-BE-NEXT:    mtfprwz f0, r29
+; CHECK-PWR9-BE-NEXT:    xxperm v3, vs0, vs1
+; CHECK-PWR9-BE-NEXT:    mtfprwz f0, r0
 ; CHECK-PWR9-BE-NEXT:    vmrghh v2, v3, v2
 ; CHECK-PWR9-BE-NEXT:    mtvsrwz v3, r30
-; CHECK-PWR9-BE-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
-; CHECK-PWR9-BE-NEXT:    vperm v3, v5, v3, v4
-; CHECK-PWR9-BE-NEXT:    mtvsrwz v5, r12
-; CHECK-PWR9-BE-NEXT:    vperm v5, v0, v5, v4
-; CHECK-PWR9-BE-NEXT:    mtvsrwz v0, r3
-; CHECK-PWR9-BE-NEXT:    vmrghh v3, v5, v3
-; CHECK-PWR9-BE-NEXT:    mtvsrwz v5, r7
+; CHECK-PWR9-BE-NEXT:    xxperm v3, vs0, vs1
+; CHECK-PWR9-BE-NEXT:    mtfprwz f0, r11
+; CHECK-PWR9-BE-NEXT:    xxperm v4, vs0, vs1
+; CHECK-PWR9-BE-NEXT:    vmrghh v3, v4, v3
+; CHECK-PWR9-BE-NEXT:    mtvsrwz v4, r4
 ; CHECK-PWR9-BE-NEXT:    xxmrghw vs0, v3, v2
 ; CHECK-PWR9-BE-NEXT:    mtvsrwz v2, r10
-; CHECK-PWR9-BE-NEXT:    mtvsrwz v3, r9
-; CHECK-PWR9-BE-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-PWR9-BE-NEXT:    mtvsrwz v3, r8
-; CHECK-PWR9-BE-NEXT:    vperm v3, v5, v3, v4
-; CHECK-PWR9-BE-NEXT:    mtvsrwz v5, r5
+; CHECK-PWR9-BE-NEXT:    xxperm v2, vs2, vs1
+; CHECK-PWR9-BE-NEXT:    mtfprwz f2, r7
+; CHECK-PWR9-BE-NEXT:    xxperm v3, vs2, vs1
+; CHECK-PWR9-BE-NEXT:    mtfprwz f2, r5
 ; CHECK-PWR9-BE-NEXT:    vmrghh v2, v3, v2
 ; CHECK-PWR9-BE-NEXT:    mtvsrwz v3, r6
-; CHECK-PWR9-BE-NEXT:    vperm v3, v5, v3, v4
-; CHECK-PWR9-BE-NEXT:    mtvsrwz v5, r4
-; CHECK-PWR9-BE-NEXT:    vperm v4, v0, v5, v4
+; CHECK-PWR9-BE-NEXT:    xxperm v3, vs2, vs1
+; CHECK-PWR9-BE-NEXT:    mtfprwz f2, r3
+; CHECK-PWR9-BE-NEXT:    xxperm v4, vs2, vs1
+; CHECK-PWR9-BE-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
+; CHECK-PWR9-BE-NEXT:    ld r29, -24(r1) # 8-byte Folded Reload
+; CHECK-PWR9-BE-NEXT:    ld r28, -32(r1) # 8-byte Folded Reload
+; CHECK-PWR9-BE-NEXT:    ld r27, -40(r1) # 8-byte Folded Reload
+; CHECK-PWR9-BE-NEXT:    ld r26, -48(r1) # 8-byte Folded Reload
+; CHECK-PWR9-BE-NEXT:    ld r25, -56(r1) # 8-byte Folded Reload
 ; CHECK-PWR9-BE-NEXT:    vmrghh v3, v4, v3
 ; CHECK-PWR9-BE-NEXT:    xxmrghw vs1, v3, v2
 ; CHECK-PWR9-BE-NEXT:    xxmrghd v2, vs1, vs0
 ; CHECK-PWR9-BE-NEXT:    blr
 ;
 ; CHECK-PWR8-LABEL: sub_absv_8_ext:
 ; CHECK-PWR8:       # %bb.0: # %entry
 ; CHECK-PWR8-NEXT:    xxswapd vs0, v2

llvm/test/CodeGen/PowerPC/pre-inc-disable.ll

 ; RUN: llc -mcpu=pwr9 -O3 -verify-machineinstrs -ppc-vsr-nums-as-vr \
 ; RUN:     -mtriple=powerpc-ibm-aix-xcoff -vec-extabi \
 ; RUN:     < %s | FileCheck %s --check-prefixes=P9BE-AIX32
 
 define void @test64(i8* nocapture readonly %pix2, i32 signext %i_pix2) {
 ; P9LE-LABEL: test64:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    add 5, 3, 4
-; P9LE-NEXT:    lxsdx 2, 3, 4
+; P9LE-NEXT:    lfdx 0, 3, 4
 ; P9LE-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
-; P9LE-NEXT:    xxlxor 4, 4, 4
+; P9LE-NEXT:    xxlxor 2, 2, 2
+; P9LE-NEXT:    vspltisw 4, 8
 ; P9LE-NEXT:    addi 3, 3, .LCPI0_0@toc@l
-; P9LE-NEXT:    lxv 3, 0(3)
+; P9LE-NEXT:    lxv 1, 0(3)
 ; P9LE-NEXT:    addis 3, 2, .LCPI0_1@toc@ha
+; P9LE-NEXT:    vadduwm 4, 4, 4
 ; P9LE-NEXT:    addi 3, 3, .LCPI0_1@toc@l
-; P9LE-NEXT:    vperm 2, 2, 4, 3
+; P9LE-NEXT:    xxperm 2, 0, 1
 ; P9LE-NEXT:    lxsd 3, 4(5)
-; P9LE-NEXT:    lxv 4, 0(3)
-; P9LE-NEXT:    vperm 3, 3, 3, 4
-; P9LE-NEXT:    vspltisw 4, 8
+; P9LE-NEXT:    lxv 0, 0(3)
+; P9LE-NEXT:    xxperm 3, 3, 0
 ; P9LE-NEXT:    vnegw 3, 3
-; P9LE-NEXT:    vadduwm 4, 4, 4
 ; P9LE-NEXT:    vslw 3, 3, 4
 ; P9LE-NEXT:    vsubuwm 2, 3, 2
 ; P9LE-NEXT:    xxswapd 0, 2
 ; P9LE-NEXT:    stxv 0, 0(3)
 ; P9LE-NEXT:    blr
 ;
 ; P9BE-LABEL: test64:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    add 5, 3, 4
 ; P9BE-NEXT:    lxsdx 2, 3, 4
 ; P9BE-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
-; P9BE-NEXT:    xxlxor 4, 4, 4
+; P9BE-NEXT:    xxlxor 0, 0, 0
+; P9BE-NEXT:    vspltisw 4, 8
 ; P9BE-NEXT:    addi 3, 3, .LCPI0_0@toc@l
-; P9BE-NEXT:    lxv 3, 0(3)
+; P9BE-NEXT:    lxv 1, 0(3)
 ; P9BE-NEXT:    addis 3, 2, .LCPI0_1@toc@ha
+; P9BE-NEXT:    vadduwm 4, 4, 4
 ; P9BE-NEXT:    addi 3, 3, .LCPI0_1@toc@l
-; P9BE-NEXT:    vperm 2, 4, 2, 3
+; P9BE-NEXT:    xxperm 2, 0, 1
 ; P9BE-NEXT:    lxsd 3, 4(5)
-; P9BE-NEXT:    lxv 4, 0(3)
-; P9BE-NEXT:    vperm 3, 3, 3, 4
-; P9BE-NEXT:    vspltisw 4, 8
+; P9BE-NEXT:    lxv 0, 0(3)
+; P9BE-NEXT:    xxperm 3, 3, 0
 ; P9BE-NEXT:    vnegw 3, 3
-; P9BE-NEXT:    vadduwm 4, 4, 4
 ; P9BE-NEXT:    vslw 3, 3, 4
 ; P9BE-NEXT:    vsubuwm 2, 3, 2
 ; P9BE-NEXT:    xxswapd 0, 2
 ; P9BE-NEXT:    stxv 0, 0(3)
 ; P9BE-NEXT:    blr
 ;
 ; P9BE-AIX-LABEL: test64:
 ; P9BE-AIX:       # %bb.0: # %entry
 ; P9BE-AIX-NEXT:    add 5, 3, 4
 ; P9BE-AIX-NEXT:    lxsdx 2, 3, 4
 ; P9BE-AIX-NEXT:    ld 3, L..C0(2) # %const.0
-; P9BE-AIX-NEXT:    xxlxor 4, 4, 4
-; P9BE-AIX-NEXT:    lxv 3, 0(3)
+; P9BE-AIX-NEXT:    xxlxor 1, 1, 1
+; P9BE-AIX-NEXT:    vspltisw 4, 8
+; P9BE-AIX-NEXT:    lxv 0, 0(3)
 ; P9BE-AIX-NEXT:    ld 3, L..C1(2) # %const.1
-; P9BE-AIX-NEXT:    vperm 2, 4, 2, 3
+; P9BE-AIX-NEXT:    vadduwm 4, 4, 4
+; P9BE-AIX-NEXT:    xxperm 2, 1, 0
 ; P9BE-AIX-NEXT:    lxsd 3, 4(5)
-; P9BE-AIX-NEXT:    lxv 4, 0(3)
-; P9BE-AIX-NEXT:    vperm 3, 3, 3, 4
-; P9BE-AIX-NEXT:    vspltisw 4, 8
+; P9BE-AIX-NEXT:    lxv 0, 0(3)
+; P9BE-AIX-NEXT:    xxperm 3, 3, 0
 ; P9BE-AIX-NEXT:    vnegw 3, 3
-; P9BE-AIX-NEXT:    vadduwm 4, 4, 4
 ; P9BE-AIX-NEXT:    vslw 3, 3, 4
 ; P9BE-AIX-NEXT:    vsubuwm 2, 3, 2
 ; P9BE-AIX-NEXT:    xxswapd 0, 2
 ; P9BE-AIX-NEXT:    stxv 0, 0(3)
 ; P9BE-AIX-NEXT:    blr
 ;
 ; P9BE-AIX32-LABEL: test64:
 ; P9BE-AIX32:       # %bb.0: # %entry
 ; P9BE-AIX32-NEXT:    lwzux 4, 3, 4
-; P9BE-AIX32-NEXT:    xxlxor 4, 4, 4
+; P9BE-AIX32-NEXT:    xxlxor 2, 2, 2
+; P9BE-AIX32-NEXT:    vspltisw 4, 8
 ; P9BE-AIX32-NEXT:    stw 4, -48(1)
+; P9BE-AIX32-NEXT:    vadduwm 4, 4, 4
 ; P9BE-AIX32-NEXT:    lwz 4, 4(3)
 ; P9BE-AIX32-NEXT:    lxv 0, -48(1)
 ; P9BE-AIX32-NEXT:    stw 4, -32(1)
 ; P9BE-AIX32-NEXT:    lwz 4, L..C0(2) # %const.0
-; P9BE-AIX32-NEXT:    lwz 3, 8(3)
 ; P9BE-AIX32-NEXT:    lxv 1, -32(1)
-; P9BE-AIX32-NEXT:    lxv 3, 0(4)
+; P9BE-AIX32-NEXT:    xxmrghw 2, 0, 1
+; P9BE-AIX32-NEXT:    lxv 0, 0(4)
+; P9BE-AIX32-NEXT:    xxperm 2, 2, 0
+; P9BE-AIX32-NEXT:    lwz 3, 8(3)
 ; P9BE-AIX32-NEXT:    stw 3, -16(1)
 ; P9BE-AIX32-NEXT:    lwz 3, L..C1(2) # %const.1
-; P9BE-AIX32-NEXT:    xxmrghw 2, 0, 1
 ; P9BE-AIX32-NEXT:    lxv 0, -16(1)
-; P9BE-AIX32-NEXT:    vperm 2, 4, 2, 3
-; P9BE-AIX32-NEXT:    lxv 4, 0(3)
 ; P9BE-AIX32-NEXT:    xxmrghw 3, 1, 0
-; P9BE-AIX32-NEXT:    vperm 3, 3, 3, 4
-; P9BE-AIX32-NEXT:    vspltisw 4, 8
+; P9BE-AIX32-NEXT:    lxv 0, 0(3)
+; P9BE-AIX32-NEXT:    xxperm 3, 3, 0
 ; P9BE-AIX32-NEXT:    vnegw 3, 3
-; P9BE-AIX32-NEXT:    vadduwm 4, 4, 4
 ; P9BE-AIX32-NEXT:    vslw 3, 3, 4
 ; P9BE-AIX32-NEXT:    vsubuwm 2, 3, 2
 ; P9BE-AIX32-NEXT:    xxswapd 0, 2
 ; P9BE-AIX32-NEXT:    stxv 0, 0(3)
 ; P9BE-AIX32-NEXT:    blr
 entry:
   %idx.ext63 = sext i32 %i_pix2 to i64
   %add.ptr64 = getelementptr inbounds i8, i8* %pix2, i64 %idx.ext63
entry:
   store <4 x i32> %13, <4 x i32>* undef, align 16
   ret void
 }
 
 define void @test32(i8* nocapture readonly %pix2, i32 signext %i_pix2) {
 ; P9LE-LABEL: test32:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    add 5, 3, 4
-; P9LE-NEXT:    lxsiwzx 2, 3, 4
+; P9LE-NEXT:    lfiwzx 0, 3, 4
 ; P9LE-NEXT:    addis 3, 2, .LCPI1_0@toc@ha
 ; P9LE-NEXT:    xxlxor 3, 3, 3
+; P9LE-NEXT:    vspltisw 4, 8
 ; P9LE-NEXT:    addi 3, 3, .LCPI1_0@toc@l
-; P9LE-NEXT:    lxv 4, 0(3)
+; P9LE-NEXT:    lxv 1, 0(3)
 ; P9LE-NEXT:    li 3, 4
-; P9LE-NEXT:    lxsiwzx 5, 5, 3
-; P9LE-NEXT:    vperm 2, 2, 3, 4
-; P9LE-NEXT:    vperm 3, 5, 3, 4
-; P9LE-NEXT:    vspltisw 4, 8
-; P9LE-NEXT:    vnegw 3, 3
+; P9LE-NEXT:    xxlxor 2, 2, 2
 ; P9LE-NEXT:    vadduwm 4, 4, 4
-; P9LE-NEXT:    vslw 3, 3, 4
-; P9LE-NEXT:    vsubuwm 2, 3, 2
+; P9LE-NEXT:    xxperm 3, 0, 1
+; P9LE-NEXT:    lfiwzx 0, 5, 3
+; P9LE-NEXT:    xxperm 2, 0, 1
+; P9LE-NEXT:    vnegw 2, 2
+; P9LE-NEXT:    vslw 2, 2, 4
+; P9LE-NEXT:    vsubuwm 2, 2, 3
 ; P9LE-NEXT:    xxswapd 0, 2
 ; P9LE-NEXT:    stxv 0, 0(3)
 ; P9LE-NEXT:    blr
 ;
 ; P9BE-LABEL: test32:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    add 5, 3, 4
-; P9BE-NEXT:    lxsiwzx 2, 3, 4
+; P9BE-NEXT:    lfiwzx 0, 3, 4
 ; P9BE-NEXT:    addis 3, 2, .LCPI1_0@toc@ha
 ; P9BE-NEXT:    xxlxor 3, 3, 3
+; P9BE-NEXT:    vspltisw 4, 8
 ; P9BE-NEXT:    addi 3, 3, .LCPI1_0@toc@l
-; P9BE-NEXT:    lxv 4, 0(3)
+; P9BE-NEXT:    lxv 1, 0(3)
 ; P9BE-NEXT:    li 3, 4
-; P9BE-NEXT:    lxsiwzx 5, 5, 3
-; P9BE-NEXT:    vperm 2, 3, 2, 4
-; P9BE-NEXT:    vperm 3, 3, 5, 4
-; P9BE-NEXT:    vspltisw 4, 8
-; P9BE-NEXT:    vnegw 3, 3
+; P9BE-NEXT:    xxlxor 2, 2, 2
 ; P9BE-NEXT:    vadduwm 4, 4, 4
-; P9BE-NEXT:    vslw 3, 3, 4
-; P9BE-NEXT:    vsubuwm 2, 3, 2
+; P9BE-NEXT:    xxperm 3, 0, 1
+; P9BE-NEXT:    lfiwzx 0, 5, 3
+; P9BE-NEXT:    xxperm 2, 0, 1
+; P9BE-NEXT:    vnegw 2, 2
+; P9BE-NEXT:    vslw 2, 2, 4
+; P9BE-NEXT:    vsubuwm 2, 2, 3
 ; P9BE-NEXT:    xxswapd 0, 2
 ; P9BE-NEXT:    stxv 0, 0(3)
 ; P9BE-NEXT:    blr
 ;
 ; P9BE-AIX-LABEL: test32:
 ; P9BE-AIX:       # %bb.0: # %entry
 ; P9BE-AIX-NEXT:    add 5, 3, 4
-; P9BE-AIX-NEXT:    lxsiwzx 2, 3, 4
+; P9BE-AIX-NEXT:    lfiwzx 0, 3, 4
 ; P9BE-AIX-NEXT:    ld 3, L..C2(2) # %const.0
 ; P9BE-AIX-NEXT:    xxlxor 3, 3, 3
-; P9BE-AIX-NEXT:    lxv 4, 0(3)
-; P9BE-AIX-NEXT:    li 3, 4
-; P9BE-AIX-NEXT:    lxsiwzx 5, 5, 3
-; P9BE-AIX-NEXT:    vperm 2, 3, 2, 4
-; P9BE-AIX-NEXT:    vperm 3, 3, 5, 4
+; P9BE-AIX-NEXT:    xxlxor 2, 2, 2
 ; P9BE-AIX-NEXT:    vspltisw 4, 8
-; P9BE-AIX-NEXT:    vnegw 3, 3
 ; P9BE-AIX-NEXT:    vadduwm 4, 4, 4
-; P9BE-AIX-NEXT:    vslw 3, 3, 4
-; P9BE-AIX-NEXT:    vsubuwm 2, 3, 2
+; P9BE-AIX-NEXT:    lxv 1, 0(3)
+; P9BE-AIX-NEXT:    li 3, 4
+; P9BE-AIX-NEXT:    xxperm 3, 0, 1
+; P9BE-AIX-NEXT:    lfiwzx 0, 5, 3
+; P9BE-AIX-NEXT:    xxperm 2, 0, 1
+; P9BE-AIX-NEXT:    vnegw 2, 2
+; P9BE-AIX-NEXT:    vslw 2, 2, 4
+; P9BE-AIX-NEXT:    vsubuwm 2, 2, 3
 ; P9BE-AIX-NEXT:    xxswapd 0, 2
 ; P9BE-AIX-NEXT:    stxv 0, 0(3)
 ; P9BE-AIX-NEXT:    blr
 ;
 ; P9BE-AIX32-LABEL: test32:
 ; P9BE-AIX32:       # %bb.0: # %entry
 ; P9BE-AIX32-NEXT:    add 5, 3, 4
-; P9BE-AIX32-NEXT:    lxsiwzx 2, 3, 4
+; P9BE-AIX32-NEXT:    lfiwzx 0, 3, 4
 ; P9BE-AIX32-NEXT:    lwz 3, L..C2(2) # %const.0
 ; P9BE-AIX32-NEXT:    xxlxor 3, 3, 3
-; P9BE-AIX32-NEXT:    lxv 4, 0(3)
-; P9BE-AIX32-NEXT:    li 3, 4
-; P9BE-AIX32-NEXT:    lxsiwzx 5, 5, 3
-; P9BE-AIX32-NEXT:    vperm 2, 3, 2, 4
-; P9BE-AIX32-NEXT:    vperm 3, 3, 5, 4
+; P9BE-AIX32-NEXT:    xxlxor 2, 2, 2
 ; P9BE-AIX32-NEXT:    vspltisw 4, 8
-; P9BE-AIX32-NEXT:    vnegw 3, 3
 ; P9BE-AIX32-NEXT:    vadduwm 4, 4, 4
-; P9BE-AIX32-NEXT:    vslw 3, 3, 4
-; P9BE-AIX32-NEXT:    vsubuwm 2, 3, 2
+; P9BE-AIX32-NEXT:    lxv 1, 0(3)
+; P9BE-AIX32-NEXT:    li 3, 4
+; P9BE-AIX32-NEXT:    xxperm 3, 0, 1
+; P9BE-AIX32-NEXT:    lfiwzx 0, 5, 3
+; P9BE-AIX32-NEXT:    xxperm 2, 0, 1
+; P9BE-AIX32-NEXT:    vnegw 2, 2
+; P9BE-AIX32-NEXT:    vslw 2, 2, 4
+; P9BE-AIX32-NEXT:    vsubuwm 2, 2, 3
 ; P9BE-AIX32-NEXT:    xxswapd 0, 2
 ; P9BE-AIX32-NEXT:    stxv 0, 0(3)
 ; P9BE-AIX32-NEXT:    blr
 entry:
   %idx.ext63 = sext i32 %i_pix2 to i64
   %add.ptr64 = getelementptr inbounds i8, i8* %pix2, i64 %idx.ext63
   %arrayidx5.1 = getelementptr inbounds i8, i8* %add.ptr64, i64 4
   %0 = bitcast i8* %add.ptr64 to <4 x i8>*

 ; P9LE-NEXT:    li 7, 16
 ; P9LE-NEXT:    add 6, 3, 4
 ; P9LE-NEXT:    lxsihzx 4, 3, 4
 ; P9LE-NEXT:    addis 3, 2, .LCPI2_0@toc@ha
 ; P9LE-NEXT:    lxsihzx 2, 6, 7
 ; P9LE-NEXT:    li 6, 0
 ; P9LE-NEXT:    addi 3, 3, .LCPI2_0@toc@l
 ; P9LE-NEXT:    mtvsrd 3, 6
+; P9LE-NEXT:    lxv 0, 0(3)
+; P9LE-NEXT:    li 3, 0
 ; P9LE-NEXT:    vmrghh 4, 3, 4
 ; P9LE-NEXT:    vmrghh 2, 3, 2
 ; P9LE-NEXT:    vsplth 3, 3, 3
 ; P9LE-NEXT:    xxmrglw 3, 4, 3
-; P9LE-NEXT:    lxv 4, 0(3)
-; P9LE-NEXT:    li 3, 0
-; P9LE-NEXT:    vperm 2, 2, 3, 4
-; P9LE-NEXT:    xxspltw 3, 2, 2
-; P9LE-NEXT:    vadduwm 2, 2, 3
+; P9LE-NEXT:    xxperm 3, 2, 0
+; P9LE-NEXT:    xxspltw 2, 3, 2
+; P9LE-NEXT:    vadduwm 2, 3, 2
 ; P9LE-NEXT:    vextuwrx 3, 3, 2
 ; P9LE-NEXT:    cmpw 3, 5
 ; P9LE-NEXT:    bgelr+ 0
 ; P9LE-NEXT:  # %bb.1: # %if.then
 ;
 ; P9BE-LABEL: test16:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    sldi 4, 4, 1
 ; P9BE-NEXT:    li 7, 16
 ; P9BE-NEXT:    add 6, 3, 4
-; P9BE-NEXT:    lxsihzx 5, 3, 4
-; P9BE-NEXT:    addis 3, 2, .LCPI2_1@toc@ha
-; P9BE-NEXT:    lxsihzx 2, 6, 7
+; P9BE-NEXT:    lxsihzx 0, 6, 7
 ; P9BE-NEXT:    addis 6, 2, .LCPI2_0@toc@ha
-; P9BE-NEXT:    addi 3, 3, .LCPI2_1@toc@l
 ; P9BE-NEXT:    addi 6, 6, .LCPI2_0@toc@l
-; P9BE-NEXT:    lxv 3, 0(6)
+; P9BE-NEXT:    lxv 1, 0(6)
 ; P9BE-NEXT:    li 6, 0
-; P9BE-NEXT:    mtvsrwz 4, 6
-; P9BE-NEXT:    vperm 2, 4, 2, 3
-; P9BE-NEXT:    vperm 3, 4, 5, 3
-; P9BE-NEXT:    vsplth 4, 4, 3
-; P9BE-NEXT:    xxmrghw 3, 4, 3
-; P9BE-NEXT:    lxv 4, 0(3)
+; P9BE-NEXT:    mtvsrwz 2, 6
+; P9BE-NEXT:    xxlor 2, 2, 2
+; P9BE-NEXT:    vsplth 3, 2, 3
+; P9BE-NEXT:    xxperm 2, 0, 1
+; P9BE-NEXT:    lxsihzx 0, 3, 4
+; P9BE-NEXT:    addis 3, 2, .LCPI2_1@toc@ha
+; P9BE-NEXT:    addi 3, 3, .LCPI2_1@toc@l
+; P9BE-NEXT:    xxperm 2, 0, 1
+; P9BE-NEXT:    lxv 1, 0(3)
 ; P9BE-NEXT:    li 3, 0
-; P9BE-NEXT:    vperm 2, 3, 2, 4
+; P9BE-NEXT:    xxmrghw 0, 3, 2
+; P9BE-NEXT:    xxperm 2, 0, 1
 ; P9BE-NEXT:    xxspltw 3, 2, 1
 ; P9BE-NEXT:    vadduwm 2, 2, 3
 ; P9BE-NEXT:    vextuwlx 3, 3, 2
 ; P9BE-NEXT:    cmpw 3, 5
 ; P9BE-NEXT:    bgelr+ 0
 ; P9BE-NEXT:  # %bb.1: # %if.then
 ;
 ; P9BE-AIX-LABEL: test16:
 ; P9BE-AIX:       # %bb.0: # %entry
 ; P9BE-AIX-NEXT:    sldi 4, 4, 1
 ; P9BE-AIX-NEXT:    li 7, 16
 ; P9BE-AIX-NEXT:    add 6, 3, 4
-; P9BE-AIX-NEXT:    lxsihzx 5, 3, 4
-; P9BE-AIX-NEXT:    ld 3, L..C3(2) # %const.1
-; P9BE-AIX-NEXT:    lxsihzx 2, 6, 7
-; P9BE-AIX-NEXT:    ld 6, L..C4(2) # %const.0
-; P9BE-AIX-NEXT:    lxv 3, 0(6)
+; P9BE-AIX-NEXT:    lxsihzx 0, 6, 7
+; P9BE-AIX-NEXT:    ld 6, L..C3(2) # %const.0
+; P9BE-AIX-NEXT:    lxv 1, 0(6)
 ; P9BE-AIX-NEXT:    li 6, 0
-; P9BE-AIX-NEXT:    mtvsrwz 4, 6
-; P9BE-AIX-NEXT:    vperm 2, 4, 2, 3
-; P9BE-AIX-NEXT:    vperm 3, 4, 5, 3
-; P9BE-AIX-NEXT:    vsplth 4, 4, 3
-; P9BE-AIX-NEXT:    xxmrghw 3, 4, 3
-; P9BE-AIX-NEXT:    lxv 4, 0(3)
+; P9BE-AIX-NEXT:    mtvsrwz 2, 6
+; P9BE-AIX-NEXT:    xxlor 2, 2, 2
+; P9BE-AIX-NEXT:    vsplth 3, 2, 3
+; P9BE-AIX-NEXT:    xxperm 2, 0, 1
+; P9BE-AIX-NEXT:    lxsihzx 0, 3, 4
+; P9BE-AIX-NEXT:    ld 3, L..C4(2) # %const.1
+; P9BE-AIX-NEXT:    xxperm 2, 0, 1
+; P9BE-AIX-NEXT:    lxv 1, 0(3)
 ; P9BE-AIX-NEXT:    li 3, 0
-; P9BE-AIX-NEXT:    vperm 2, 3, 2, 4
+; P9BE-AIX-NEXT:    xxmrghw 0, 3, 2
+; P9BE-AIX-NEXT:    xxperm 2, 0, 1
 ; P9BE-AIX-NEXT:    xxspltw 3, 2, 1
 ; P9BE-AIX-NEXT:    vadduwm 2, 2, 3
 ; P9BE-AIX-NEXT:    vextuwlx 3, 3, 2
 ; P9BE-AIX-NEXT:    cmpw 3, 5
 ; P9BE-AIX-NEXT:    bgelr+ 0
 ; P9BE-AIX-NEXT:  # %bb.1: # %if.then
 ;
 ; P9BE-AIX32-LABEL: test16:
 ; P9BE-AIX32:       # %bb.0: # %entry
 ; P9BE-AIX32-NEXT:    slwi 4, 4, 1
 ; P9BE-AIX32-NEXT:    li 6, 0
 ; P9BE-AIX32-NEXT:    lhzux 4, 3, 4
 ; P9BE-AIX32-NEXT:    lhz 3, 16(3)
 ; P9BE-AIX32-NEXT:    sth 6, -64(1)
 ; P9BE-AIX32-NEXT:    lxv 2, -64(1)
 ; P9BE-AIX32-NEXT:    sth 4, -48(1)
 ; P9BE-AIX32-NEXT:    lxv 4, -48(1)
 ; P9BE-AIX32-NEXT:    sth 3, -32(1)
 ; P9BE-AIX32-NEXT:    lwz 3, L..C3(2) # %const.0
 ; P9BE-AIX32-NEXT:    lxv 3, -32(1)
 ; P9BE-AIX32-NEXT:    vmrghh 4, 2, 4
+; P9BE-AIX32-NEXT:    lxv 1, 0(3)
 ; P9BE-AIX32-NEXT:    vmrghh 3, 2, 3
 ; P9BE-AIX32-NEXT:    vsplth 2, 2, 0
-; P9BE-AIX32-NEXT:    xxmrghw 2, 2, 4
-; P9BE-AIX32-NEXT:    lxv 4, 0(3)
-; P9BE-AIX32-NEXT:    vperm 2, 2, 3, 4
-; P9BE-AIX32-NEXT:    xxspltw 3, 2, 1
-; P9BE-AIX32-NEXT:    vadduwm 2, 2, 3
+; P9BE-AIX32-NEXT:    xxmrghw 0, 2, 4
+; P9BE-AIX32-NEXT:    xxperm 3, 0, 1
+; P9BE-AIX32-NEXT:    xxspltw 2, 3, 1
+; P9BE-AIX32-NEXT:    vadduwm 2, 3, 2
 ; P9BE-AIX32-NEXT:    stxv 2, -16(1)
 ; P9BE-AIX32-NEXT:    lwz 3, -16(1)
 ; P9BE-AIX32-NEXT:    cmpw 3, 5
 ; P9BE-AIX32-NEXT:    bgelr+ 0
 ; P9BE-AIX32-NEXT:  # %bb.1: # %if.then
 entry:
   %idxprom = sext i32 %delta to i64
   %add14 = add nsw i32 %delta, 8

 ; P9LE-NEXT:    mtvsrd 3, 3
 ; P9LE-NEXT:    li 3, 8
 ; P9LE-NEXT:    lxsibzx 5, 6, 3
 ; P9LE-NEXT:    vspltb 4, 3, 7
 ; P9LE-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
 ; P9LE-NEXT:    vmrghb 2, 3, 2
 ; P9LE-NEXT:    addi 3, 3, .LCPI3_0@toc@l
 ; P9LE-NEXT:    vmrglh 2, 2, 4
+; P9LE-NEXT:    lxv 1, 0(3)
+; P9LE-NEXT:    li 3, 0
 ; P9LE-NEXT:    vmrghb 3, 3, 5
 ; P9LE-NEXT:    xxmrglw 2, 2, 4
 ; P9LE-NEXT:    vmrglh 3, 3, 4
-; P9LE-NEXT:    xxmrglw 3, 4, 3
-; P9LE-NEXT:    lxv 4, 0(3)
-; P9LE-NEXT:    li 3, 0
-; P9LE-NEXT:    vperm 2, 3, 2, 4
+; P9LE-NEXT:    xxmrglw 0, 4, 3
+; P9LE-NEXT:    xxperm 2, 0, 1
 ; P9LE-NEXT:    xxspltw 3, 2, 2
 ; P9LE-NEXT:    vadduwm 2, 2, 3
 ; P9LE-NEXT:    vextuwrx 3, 3, 2
 ; P9LE-NEXT:    cmpw 3, 5
 ; P9LE-NEXT:    bgelr+ 0
 ; P9LE-NEXT:  # %bb.1: # %if.then
 ;
 ; P9BE-LABEL: test8:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    add 6, 3, 4
 ; P9BE-NEXT:    li 7, 8
-; P9BE-NEXT:    lxsibzx 5, 3, 4
-; P9BE-NEXT:    addis 3, 2, .LCPI3_1@toc@ha
-; P9BE-NEXT:    lxsibzx 2, 6, 7
+; P9BE-NEXT:    lxsibzx 0, 6, 7
 ; P9BE-NEXT:    addis 6, 2, .LCPI3_0@toc@ha
-; P9BE-NEXT:    addi 3, 3, .LCPI3_1@toc@l
 ; P9BE-NEXT:    addi 6, 6, .LCPI3_0@toc@l
-; P9BE-NEXT:    lxv 3, 0(6)
+; P9BE-NEXT:    lxv 1, 0(6)
 ; P9BE-NEXT:    li 6, 0
-; P9BE-NEXT:    mtvsrwz 4, 6
-; P9BE-NEXT:    vperm 2, 4, 2, 3
-; P9BE-NEXT:    vperm 3, 4, 5, 3
-; P9BE-NEXT:    vspltb 4, 4, 7
-; P9BE-NEXT:    vmrghh 3, 3, 4
-; P9BE-NEXT:    xxspltw 4, 4, 0
-; P9BE-NEXT:    xxmrghw 2, 3, 2
-; P9BE-NEXT:    lxv 3, 0(3)
+; P9BE-NEXT:    mtvsrwz 2, 6
+; P9BE-NEXT:    vspltb 3, 2, 7
+; P9BE-NEXT:    xxperm 0, 2, 1
+; P9BE-NEXT:    lxsibzx 1, 3, 4
+; P9BE-NEXT:    addis 3, 2, .LCPI3_1@toc@ha
+; P9BE-NEXT:    addi 3, 3, .LCPI3_1@toc@l
+; P9BE-NEXT:    lxv 2, 0(3)
+; P9BE-NEXT:    addis 3, 2, .LCPI3_2@toc@ha
+; P9BE-NEXT:    addi 3, 3, .LCPI3_2@toc@l
+; P9BE-NEXT:    xxperm 2, 1, 2
+; P9BE-NEXT:    xxspltw 1, 3, 0
+; P9BE-NEXT:    vmrghh 2, 2, 3
+; P9BE-NEXT:    xxmrghw 2, 2, 0
+; P9BE-NEXT:    lxv 0, 0(3)
 ; P9BE-NEXT:    li 3, 0
-; P9BE-NEXT:    vperm 2, 4, 2, 3
+; P9BE-NEXT:    xxperm 2, 1, 0
 ; P9BE-NEXT:    xxspltw 3, 2, 1
 ; P9BE-NEXT:    vadduwm 2, 2, 3
 ; P9BE-NEXT:    vextuwlx 3, 3, 2
 ; P9BE-NEXT:    cmpw 3, 5
 ; P9BE-NEXT:    bgelr+ 0
 ; P9BE-NEXT:  # %bb.1: # %if.then
 ;
 ; P9BE-AIX-LABEL: test8:
 ; P9BE-AIX:       # %bb.0: # %entry
 ; P9BE-AIX-NEXT:    add 6, 3, 4
 ; P9BE-AIX-NEXT:    li 7, 8
-; P9BE-AIX-NEXT:    lxsibzx 5, 3, 4
-; P9BE-AIX-NEXT:    ld 3, L..C5(2) # %const.1
-; P9BE-AIX-NEXT:    lxsibzx 2, 6, 7
-; P9BE-AIX-NEXT:    ld 6, L..C6(2) # %const.0
-; P9BE-AIX-NEXT:    lxv 3, 0(6)
+; P9BE-AIX-NEXT:    lxsibzx 0, 6, 7
+; P9BE-AIX-NEXT:    ld 6, L..C5(2) # %const.0
+; P9BE-AIX-NEXT:    lxv 1, 0(6)
 ; P9BE-AIX-NEXT:    li 6, 0
-; P9BE-AIX-NEXT:    mtvsrwz 4, 6
-; P9BE-AIX-NEXT:    vperm 2, 4, 2, 3
-; P9BE-AIX-NEXT:    vperm 3, 4, 5, 3
-; P9BE-AIX-NEXT:    vspltb 4, 4, 7
-; P9BE-AIX-NEXT:    vmrghh 3, 3, 4
-; P9BE-AIX-NEXT:    xxspltw 4, 4, 0
-; P9BE-AIX-NEXT:    xxmrghw 2, 3, 2
-; P9BE-AIX-NEXT:    lxv 3, 0(3)
+; P9BE-AIX-NEXT:    mtvsrwz 2, 6
+; P9BE-AIX-NEXT:    vspltb 3, 2, 7
+; P9BE-AIX-NEXT:    xxperm 0, 2, 1
+; P9BE-AIX-NEXT:    lxsibzx 1, 3, 4
+; P9BE-AIX-NEXT:    ld 3, L..C6(2) # %const.1
+; P9BE-AIX-NEXT:    lxv 2, 0(3)
+; P9BE-AIX-NEXT:    ld 3, L..C7(2) # %const.2
+; P9BE-AIX-NEXT:    xxperm 2, 1, 2
+; P9BE-AIX-NEXT:    xxspltw 1, 3, 0
+; P9BE-AIX-NEXT:    vmrghh 2, 2, 3
+; P9BE-AIX-NEXT:    xxmrghw 2, 2, 0
+; P9BE-AIX-NEXT:    lxv 0, 0(3)
 ; P9BE-AIX-NEXT:    li 3, 0
-; P9BE-AIX-NEXT:    vperm 2, 4, 2, 3
+; P9BE-AIX-NEXT:    xxperm 2, 1, 0
 ; P9BE-AIX-NEXT:    xxspltw 3, 2, 1
 ; P9BE-AIX-NEXT:    vadduwm 2, 2, 3
 ; P9BE-AIX-NEXT:    vextuwlx 3, 3, 2
 ; P9BE-AIX-NEXT:    cmpw 3, 5
 ; P9BE-AIX-NEXT:    bgelr+ 0
 ; P9BE-AIX-NEXT:  # %bb.1: # %if.then
 ;
 ; P9BE-AIX32-LABEL: test8:
 ; P9BE-AIX32:       # %bb.0: # %entry
 ; P9BE-AIX32-NEXT:    add 6, 3, 4
 ; P9BE-AIX32-NEXT:    li 7, 8
-; P9BE-AIX32-NEXT:    lxsibzx 5, 3, 4
-; P9BE-AIX32-NEXT:    lwz 3, L..C4(2) # %const.1
-; P9BE-AIX32-NEXT:    lxsibzx 2, 6, 7
-; P9BE-AIX32-NEXT:    lwz 6, L..C5(2) # %const.0
-; P9BE-AIX32-NEXT:    lxv 3, 0(6)
+; P9BE-AIX32-NEXT:    lxsibzx 0, 6, 7
+; P9BE-AIX32-NEXT:    lwz 6, L..C4(2) # %const.0
+; P9BE-AIX32-NEXT:    lxv 1, 0(6)
 ; P9BE-AIX32-NEXT:    li 6, 0
-; P9BE-AIX32-NEXT:    mtvsrwz 4, 6
-; P9BE-AIX32-NEXT:    vperm 2, 4, 2, 3
-; P9BE-AIX32-NEXT:    vperm 3, 4, 5, 3
-; P9BE-AIX32-NEXT:    vspltb 4, 4, 7
-; P9BE-AIX32-NEXT:    vmrghh 3, 3, 4
-; P9BE-AIX32-NEXT:    xxspltw 4, 4, 0
-; P9BE-AIX32-NEXT:    xxmrghw 2, 3, 2
-; P9BE-AIX32-NEXT:    lxv 3, 0(3)
-; P9BE-AIX32-NEXT:    vperm 2, 4, 2, 3
+; P9BE-AIX32-NEXT:    mtvsrwz 2, 6
+; P9BE-AIX32-NEXT:    vspltb 3, 2, 7
+; P9BE-AIX32-NEXT:    xxperm 0, 2, 1
+; P9BE-AIX32-NEXT:    lxsibzx 1, 3, 4
+; P9BE-AIX32-NEXT:    lwz 3, L..C5(2) # %const.1
+; P9BE-AIX32-NEXT:    lxv 2, 0(3)
+; P9BE-AIX32-NEXT:    lwz 3, L..C6(2) # %const.2
+; P9BE-AIX32-NEXT:    xxperm 2, 1, 2
+; P9BE-AIX32-NEXT:    xxspltw 1, 3, 0
+; P9BE-AIX32-NEXT:    vmrghh 2, 2, 3
+; P9BE-AIX32-NEXT:    xxmrghw 2, 2, 0
+; P9BE-AIX32-NEXT:    lxv 0, 0(3)
+; P9BE-AIX32-NEXT:    xxperm 2, 1, 0
 ; P9BE-AIX32-NEXT:    xxspltw 3, 2, 1
 ; P9BE-AIX32-NEXT:    vadduwm 2, 2, 3
 ; P9BE-AIX32-NEXT:    stxv 2, -16(1)
 ; P9BE-AIX32-NEXT:    lwz 3, -16(1)
 ; P9BE-AIX32-NEXT:    cmpw 3, 5
 ; P9BE-AIX32-NEXT:    bgelr+ 0
 ; P9BE-AIX32-NEXT:  # %bb.1: # %if.then
 entry:

llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll

 ; P9BE-NEXT:    mulhw r4, r3, r4
 ; P9BE-NEXT:    sub r4, r4, r3
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 6
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, -124
 ; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    lis r4, -21386
-; P9BE-NEXT:    mtvsrwz v3, r3
+; P9BE-NEXT:    mtfprwz f0, r3
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    ori r4, r4, 37253
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    mulhw r4, r3, r4
 ; P9BE-NEXT:    add r4, r4, r3
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 6
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 95
 ; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    lis r4, -16728
-; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    mtfprwz f1, r3
 ; P9BE-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
 ; P9BE-NEXT:    ori r4, r4, 63249
 ; P9BE-NEXT:    addi r3, r3, .LCPI0_0@toc@l
-; P9BE-NEXT:    lxv v5, 0(r3)
+; P9BE-NEXT:    lxv vs2, 0(r3)
 ; P9BE-NEXT:    li r3, 6
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
-; P9BE-NEXT:    vperm v3, v4, v3, v5
+; P9BE-NEXT:    xxperm vs0, vs1, vs2
 ; P9BE-NEXT:    mulhw r4, r3, r4
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 8
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, -1003
 ; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    lis r4, 21399
-; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    mtfprwz f1, r3
 ; P9BE-NEXT:    li r3, 4
 ; P9BE-NEXT:    ori r4, r4, 33437
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    mulhw r4, r3, r4
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 5
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 98
 ; P9BE-NEXT:    sub r3, r3, r4
-; P9BE-NEXT:    mtvsrwz v2, r3
-; P9BE-NEXT:    vperm v2, v2, v4, v5
-; P9BE-NEXT:    xxmrghw v2, v3, v2
+; P9BE-NEXT:    mtfprwz f3, r3
+; P9BE-NEXT:    xxperm vs1, vs3, vs2
+; P9BE-NEXT:    xxmrghw v2, vs0, vs1
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fold_srem_vec_1:
 ; P8LE:       # %bb.0:
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    lis r3, 21399
 ; P8LE-NEXT:    lis r8, -16728
 ; P8LE-NEXT:    lis r9, -21386

 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    mulhw r5, r3, r4
 ; P9BE-NEXT:    add r5, r5, r3
 ; P9BE-NEXT:    srwi r6, r5, 31
 ; P9BE-NEXT:    srawi r5, r5, 6
 ; P9BE-NEXT:    add r5, r5, r6
 ; P9BE-NEXT:    mulli r5, r5, 95
 ; P9BE-NEXT:    sub r3, r3, r5
-; P9BE-NEXT:    mtvsrwz v3, r3
+; P9BE-NEXT:    mtfprwz f0, r3
 ; P9BE-NEXT:    li r3, 4
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    mulhw r5, r3, r4
 ; P9BE-NEXT:    add r5, r5, r3
 ; P9BE-NEXT:    srwi r6, r5, 31
 ; P9BE-NEXT:    srawi r5, r5, 6
 ; P9BE-NEXT:    add r5, r5, r6
 ; P9BE-NEXT:    mulli r5, r5, 95
 ; P9BE-NEXT:    sub r3, r3, r5
-; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    mtfprwz f1, r3
 ; P9BE-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
 ; P9BE-NEXT:    addi r3, r3, .LCPI1_0@toc@l
-; P9BE-NEXT:    lxv v5, 0(r3)
+; P9BE-NEXT:    lxv vs2, 0(r3)
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
-; P9BE-NEXT:    vperm v3, v4, v3, v5
+; P9BE-NEXT:    xxperm vs0, vs1, vs2
 ; P9BE-NEXT:    mulhw r5, r3, r4
 ; P9BE-NEXT:    add r5, r5, r3
 ; P9BE-NEXT:    srwi r6, r5, 31
 ; P9BE-NEXT:    srawi r5, r5, 6
 ; P9BE-NEXT:    add r5, r5, r6
 ; P9BE-NEXT:    mulli r5, r5, 95
 ; P9BE-NEXT:    sub r3, r3, r5
-; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    mtfprwz f1, r3
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    mulhw r4, r3, r4
 ; P9BE-NEXT:    add r4, r4, r3
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 6
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 95
 ; P9BE-NEXT:    sub r3, r3, r4
-; P9BE-NEXT:    mtvsrwz v2, r3
-; P9BE-NEXT:    vperm v2, v2, v4, v5
-; P9BE-NEXT:    xxmrghw v2, v2, v3
+; P9BE-NEXT:    mtfprwz f3, r3
+; P9BE-NEXT:    xxperm vs1, vs3, vs2
+; P9BE-NEXT:    xxmrghw v2, vs1, vs0
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fold_srem_vec_2:
 ; P8LE:       # %bb.0:
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    lis r3, -21386
 ; P8LE-NEXT:    ori r3, r3, 37253
 ; P8LE-NEXT:    mffprd r4, f0

 ; P9BE-NEXT:    extsh r4, r3
 ; P9BE-NEXT:    mulhw r6, r4, r5
 ; P9BE-NEXT:    add r4, r6, r4
 ; P9BE-NEXT:    srwi r6, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 6
 ; P9BE-NEXT:    add r4, r4, r6
 ; P9BE-NEXT:    mulli r6, r4, 95
 ; P9BE-NEXT:    sub r3, r3, r6
-; P9BE-NEXT:    mtvsrwz v3, r3
+; P9BE-NEXT:    mtfprwz f0, r3
 ; P9BE-NEXT:    li r3, 4
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r6, r3
 ; P9BE-NEXT:    mulhw r7, r6, r5
 ; P9BE-NEXT:    add r6, r7, r6
 ; P9BE-NEXT:    srwi r7, r6, 31
 ; P9BE-NEXT:    srawi r6, r6, 6
 ; P9BE-NEXT:    add r6, r6, r7
 ; P9BE-NEXT:    mulli r7, r6, 95
 ; P9BE-NEXT:    sub r3, r3, r7
-; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    mtfprwz f1, r3
 ; P9BE-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
 ; P9BE-NEXT:    addi r3, r3, .LCPI2_0@toc@l
-; P9BE-NEXT:    lxv v5, 0(r3)
+; P9BE-NEXT:    lxv vs2, 0(r3)
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r7, r3
-; P9BE-NEXT:    vperm v3, v4, v3, v5
+; P9BE-NEXT:    xxperm vs0, vs1, vs2
 ; P9BE-NEXT:    mulhw r8, r7, r5
 ; P9BE-NEXT:    add r7, r8, r7
 ; P9BE-NEXT:    srwi r8, r7, 31
 ; P9BE-NEXT:    srawi r7, r7, 6
 ; P9BE-NEXT:    add r7, r7, r8
 ; P9BE-NEXT:    mulli r8, r7, 95
 ; P9BE-NEXT:    sub r3, r3, r8
-; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    mtfprwz f1, r3
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    mulhw r5, r3, r5
 ; P9BE-NEXT:    add r5, r5, r3
 ; P9BE-NEXT:    srwi r8, r5, 31
 ; P9BE-NEXT:    srawi r5, r5, 6
 ; P9BE-NEXT:    add r5, r5, r8
 ; P9BE-NEXT:    mulli r8, r5, 95
-; P9BE-NEXT:    mtvsrwz v0, r5
 ; P9BE-NEXT:    sub r3, r3, r8
-; P9BE-NEXT:    mtvsrwz v2, r3
-; P9BE-NEXT:    vperm v2, v2, v4, v5
-; P9BE-NEXT:    mtvsrwz v4, r6
-; P9BE-NEXT:    xxmrghw v2, v2, v3
-; P9BE-NEXT:    mtvsrwz v3, r4
-; P9BE-NEXT:    vperm v3, v4, v3, v5
-; P9BE-NEXT:    mtvsrwz v4, r7
-; P9BE-NEXT:    vperm v4, v0, v4, v5
-; P9BE-NEXT:    xxmrghw v3, v4, v3
+; P9BE-NEXT:    mtfprwz f3, r3
+; P9BE-NEXT:    xxperm vs1, vs3, vs2
+; P9BE-NEXT:    mtfprwz f3, r5
+; P9BE-NEXT:    xxmrghw v2, vs1, vs0
+; P9BE-NEXT:    mtfprwz f0, r4
+; P9BE-NEXT:    mtfprwz f1, r6
+; P9BE-NEXT:    xxperm vs0, vs1, vs2
+; P9BE-NEXT:    mtfprwz f1, r7
+; P9BE-NEXT:    xxperm vs1, vs3, vs2
+; P9BE-NEXT:    xxmrghw v3, vs1, vs0
 ; P9BE-NEXT:    vadduhm v2, v2, v3
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: combine_srem_sdiv:
 ; P8LE:       # %bb.0:
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    lis r3, -21386
 ; P8LE-NEXT:    ori r3, r3, 37253

 ; P9BE:       # %bb.0:
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    srawi r4, r3, 5
 ; P9BE-NEXT:    addze r4, r4
 ; P9BE-NEXT:    slwi r4, r4, 5
 ; P9BE-NEXT:    sub r3, r3, r4
-; P9BE-NEXT:    mtvsrwz v3, r3
+; P9BE-NEXT:    mtfprwz f0, r3
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    srawi r4, r3, 6
 ; P9BE-NEXT:    addze r4, r4
 ; P9BE-NEXT:    slwi r4, r4, 6
 ; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    lis r4, -21386
-; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    mtfprwz f1, r3
 ; P9BE-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
 ; P9BE-NEXT:    ori r4, r4, 37253
 ; P9BE-NEXT:    addi r3, r3, .LCPI3_0@toc@l
-; P9BE-NEXT:    lxv v5, 0(r3)
+; P9BE-NEXT:    lxv vs2, 0(r3)
 ; P9BE-NEXT:    li r3, 6
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
-; P9BE-NEXT:    vperm v3, v4, v3, v5
+; P9BE-NEXT:    xxperm vs0, vs1, vs2
 ; P9BE-NEXT:    mulhw r4, r3, r4
 ; P9BE-NEXT:    add r4, r4, r3
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 6
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 95
 ; P9BE-NEXT:    sub r3, r3, r4
-; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    mtfprwz f1, r3
 ; P9BE-NEXT:    li r3, 4
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    srawi r4, r3, 3
 ; P9BE-NEXT:    addze r4, r4
 ; P9BE-NEXT:    slwi r4, r4, 3
 ; P9BE-NEXT:    sub r3, r3, r4
-; P9BE-NEXT:    mtvsrwz v2, r3
-; P9BE-NEXT:    vperm v2, v2, v4, v5
-; P9BE-NEXT:    xxmrghw v2, v3, v2
+; P9BE-NEXT:    mtfprwz f3, r3
+; P9BE-NEXT:    xxperm vs1, vs3, vs2
+; P9BE-NEXT:    xxmrghw v2, vs0, vs1
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: dont_fold_srem_power_of_two:
 ; P8LE:       # %bb.0:
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    lis r3, -21386
 ; P8LE-NEXT:    ori r3, r3, 37253
 ; P8LE-NEXT:    mffprd r4, f0

 ; P9BE-NEXT:    mulhw r4, r3, r4
 ; P9BE-NEXT:    add r4, r4, r3
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 4
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 23
 ; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    lis r4, 24749
-; P9BE-NEXT:    mtvsrwz v3, r3
+; P9BE-NEXT:    mtfprwz f0, r3
 ; P9BE-NEXT:    li r3, 6
 ; P9BE-NEXT:    ori r4, r4, 47143
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    mulhw r4, r3, r4
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 11
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 5423
 ; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    lis r4, -14230
-; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    mtfprwz f1, r3
 ; P9BE-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
 ; P9BE-NEXT:    ori r4, r4, 30865
 ; P9BE-NEXT:    addi r3, r3, .LCPI4_0@toc@l
-; P9BE-NEXT:    lxv v5, 0(r3)
+; P9BE-NEXT:    lxv vs2, 0(r3)
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
-; P9BE-NEXT:    vperm v3, v3, v4, v5
+; P9BE-NEXT:    xxperm vs1, vs0, vs2
 ; P9BE-NEXT:    mulhw r4, r3, r4
 ; P9BE-NEXT:    add r4, r4, r3
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 9
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 654
 ; P9BE-NEXT:    sub r3, r3, r4
-; P9BE-NEXT:    mtvsrwz v2, r3
+; P9BE-NEXT:    mtfprwz f0, r3
 ; P9BE-NEXT:    li r3, 0
-; P9BE-NEXT:    mtvsrwz v4, r3
-; P9BE-NEXT:    vperm v2, v4, v2, v5
-; P9BE-NEXT:    xxmrghw v2, v2, v3
+; P9BE-NEXT:    mtfprwz f3, r3
+; P9BE-NEXT:    xxperm vs0, vs3, vs2
+; P9BE-NEXT:    xxmrghw v2, vs0, vs1
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: dont_fold_srem_one:
 ; P8LE:       # %bb.0:
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    lis r5, 24749
 ; P8LE-NEXT:    lis r6, -19946
 ; P8LE-NEXT:    lis r8, -14230

 ; P9BE-NEXT:    mulhw r4, r3, r4
 ; P9BE-NEXT:    add r4, r4, r3
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 4
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 23
 ; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    lis r4, 24749
-; P9BE-NEXT:    mtvsrwz v3, r3
+; P9BE-NEXT:    mtfprwz f0, r3
 ; P9BE-NEXT:    li r3, 6
 ; P9BE-NEXT:    ori r4, r4, 47143
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    mulhw r4, r3, r4
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 11
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 5423
 ; P9BE-NEXT:    sub r3, r3, r4
-; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    mtfprwz f1, r3
 ; P9BE-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
 ; P9BE-NEXT:    addi r3, r3, .LCPI5_0@toc@l
-; P9BE-NEXT:    lxv v5, 0(r3)
+; P9BE-NEXT:    lxv vs2, 0(r3)
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
-; P9BE-NEXT:    vperm v3, v3, v4, v5
+; P9BE-NEXT:    xxperm vs1, vs0, vs2
 ; P9BE-NEXT:    srawi r4, r3, 15
 ; P9BE-NEXT:    addze r4, r4
 ; P9BE-NEXT:    slwi r4, r4, 15
 ; P9BE-NEXT:    sub r3, r3, r4
-; P9BE-NEXT:    mtvsrwz v2, r3
+; P9BE-NEXT:    mtfprwz f0, r3
 ; P9BE-NEXT:    li r3, 0
-; P9BE-NEXT:    mtvsrwz v4, r3
-; P9BE-NEXT:    vperm v2, v4, v2, v5
-; P9BE-NEXT:    xxmrghw v2, v2, v3
+; P9BE-NEXT:    mtfprwz f3, r3
+; P9BE-NEXT:    xxperm vs0, vs3, vs2
+; P9BE-NEXT:    xxmrghw v2, vs0, vs1
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: dont_fold_urem_i16_smax:
 ; P8LE:       # %bb.0:
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    lis r4, 24749
 ; P8LE-NEXT:    lis r5, -19946
 ; P8LE-NEXT:    ori r4, r4, 47143

llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll

 ; P9BE-NEXT:    ori r4, r4, 2287
 ; P9BE-NEXT:    ori r5, r5, 16913
 ; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    mulhwu r4, r3, r4
 ; P9BE-NEXT:    srwi r4, r4, 8
 ; P9BE-NEXT:    mulli r4, r4, 1003
 ; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    lis r4, 21399
-; P9BE-NEXT:    mtvsrwz v3, r3
+; P9BE-NEXT:    mtfprwz f0, r3
 ; P9BE-NEXT:    li r3, 4
 ; P9BE-NEXT:    ori r4, r4, 33437
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    mulhwu r4, r3, r4
 ; P9BE-NEXT:    srwi r4, r4, 5
 ; P9BE-NEXT:    mulli r4, r4, 98
 ; P9BE-NEXT:    sub r3, r3, r4
-; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    mtfprwz f1, r3
 ; P9BE-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
 ; P9BE-NEXT:    addi r3, r3, .LCPI0_0@toc@l
-; P9BE-NEXT:    lxv v5, 0(r3)
+; P9BE-NEXT:    lxv vs2, 0(r3)
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r4, r3, 16
 ; P9BE-NEXT:    rlwinm r3, r3, 30, 18, 31
-; P9BE-NEXT:    vperm v3, v4, v3, v5
+; P9BE-NEXT:    xxperm vs0, vs1, vs2
 ; P9BE-NEXT:    mulhwu r3, r3, r5
 ; P9BE-NEXT:    srwi r3, r3, 2
 ; P9BE-NEXT:    mulli r3, r3, 124
 ; P9BE-NEXT:    sub r3, r4, r3
 ; P9BE-NEXT:    lis r4, 22765
-; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    mtfprwz f1, r3
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    ori r4, r4, 8969
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    mulhwu r4, r3, r4
 ; P9BE-NEXT:    sub r5, r3, r4
 ; P9BE-NEXT:    srwi r5, r5, 1
 ; P9BE-NEXT:    add r4, r5, r4
 ; P9BE-NEXT:    srwi r4, r4, 6
 ; P9BE-NEXT:    mulli r4, r4, 95
 ; P9BE-NEXT:    sub r3, r3, r4
-; P9BE-NEXT:    mtvsrwz v2, r3
-; P9BE-NEXT:    vperm v2, v2, v4, v5
-; P9BE-NEXT:    xxmrghw v2, v2, v3
+; P9BE-NEXT:    mtfprwz f3, r3
+; P9BE-NEXT:    xxperm vs1, vs3, vs2
+; P9BE-NEXT:    xxmrghw v2, vs1, vs0
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fold_urem_vec_1:
 ; P8LE:       # %bb.0:
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    lis r3, 22765
 ; P8LE-NEXT:    lis r7, 21399
 ; P8LE-NEXT:    lis r9, 16727

 ; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    mulhwu r5, r3, r4
 ; P9BE-NEXT:    sub r6, r3, r5
 ; P9BE-NEXT:    srwi r6, r6, 1
 ; P9BE-NEXT:    add r5, r6, r5
 ; P9BE-NEXT:    srwi r5, r5, 6
 ; P9BE-NEXT:    mulli r5, r5, 95
 ; P9BE-NEXT:    sub r3, r3, r5
-; P9BE-NEXT:    mtvsrwz v3, r3
+; P9BE-NEXT:    mtfprwz f0, r3
 ; P9BE-NEXT:    li r3, 4
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    mulhwu r5, r3, r4
 ; P9BE-NEXT:    sub r6, r3, r5
 ; P9BE-NEXT:    srwi r6, r6, 1
 ; P9BE-NEXT:    add r5, r6, r5
 ; P9BE-NEXT:    srwi r5, r5, 6
 ; P9BE-NEXT:    mulli r5, r5, 95
 ; P9BE-NEXT:    sub r3, r3, r5
-; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    mtfprwz f1, r3
 ; P9BE-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
 ; P9BE-NEXT:    addi r3, r3, .LCPI1_0@toc@l
-; P9BE-NEXT:    lxv v5, 0(r3)
+; P9BE-NEXT:    lxv vs2, 0(r3)
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r3, r3, 16
-; P9BE-NEXT:    vperm v3, v4, v3, v5
+; P9BE-NEXT:    xxperm vs0, vs1, vs2
 ; P9BE-NEXT:    mulhwu r5, r3, r4
 ; P9BE-NEXT:    sub r6, r3, r5
 ; P9BE-NEXT:    srwi r6, r6, 1
 ; P9BE-NEXT:    add r5, r6, r5
 ; P9BE-NEXT:    srwi r5, r5, 6
 ; P9BE-NEXT:    mulli r5, r5, 95
 ; P9BE-NEXT:    sub r3, r3, r5
-; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    mtfprwz f1, r3
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    mulhwu r4, r3, r4
 ; P9BE-NEXT:    sub r5, r3, r4
 ; P9BE-NEXT:    srwi r5, r5, 1
 ; P9BE-NEXT:    add r4, r5, r4
 ; P9BE-NEXT:    srwi r4, r4, 6
 ; P9BE-NEXT:    mulli r4, r4, 95
 ; P9BE-NEXT:    sub r3, r3, r4
-; P9BE-NEXT:    mtvsrwz v2, r3
-; P9BE-NEXT:    vperm v2, v2, v4, v5
-; P9BE-NEXT:    xxmrghw v2, v2, v3
+; P9BE-NEXT:    mtfprwz f3, r3
+; P9BE-NEXT:    xxperm vs1, vs3, vs2
+; P9BE-NEXT:    xxmrghw v2, vs1, vs0
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fold_urem_vec_2:
 ; P8LE:       # %bb.0:
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    lis r3, 22765
 ; P8LE-NEXT:    ori r3, r3, 8969
 ; P8LE-NEXT:    mffprd r4, f0

 ; P9BE-NEXT:    clrlwi r4, r3, 16
 ; P9BE-NEXT:    mulhwu r6, r4, r5
 ; P9BE-NEXT:    sub r4, r4, r6
 ; P9BE-NEXT:    srwi r4, r4, 1
 ; P9BE-NEXT:    add r4, r4, r6
 ; P9BE-NEXT:    srwi r4, r4, 6
 ; P9BE-NEXT:    mulli r6, r4, 95
 ; P9BE-NEXT:    sub r3, r3, r6
-; P9BE-NEXT:    mtvsrwz v3, r3
+; P9BE-NEXT:    mtfprwz f0, r3
 ; P9BE-NEXT:    li r3, 4
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r6, r3, 16
 ; P9BE-NEXT:    mulhwu r7, r6, r5
 ; P9BE-NEXT:    sub r6, r6, r7
 ; P9BE-NEXT:    srwi r6, r6, 1
 ; P9BE-NEXT:    add r6, r6, r7
 ; P9BE-NEXT:    srwi r6, r6, 6
 ; P9BE-NEXT:    mulli r7, r6, 95
 ; P9BE-NEXT:    sub r3, r3, r7
-; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    mtfprwz f1, r3
 ; P9BE-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
 ; P9BE-NEXT:    addi r3, r3, .LCPI2_0@toc@l
-; P9BE-NEXT:    lxv v5, 0(r3)
+; P9BE-NEXT:    lxv vs2, 0(r3)
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r7, r3, 16
-; P9BE-NEXT:    vperm v3, v4, v3, v5
+; P9BE-NEXT:    xxperm vs0, vs1, vs2
 ; P9BE-NEXT:    mulhwu r8, r7, r5
 ; P9BE-NEXT:    sub r7, r7, r8
 ; P9BE-NEXT:    srwi r7, r7, 1
 ; P9BE-NEXT:    add r7, r7, r8
 ; P9BE-NEXT:    srwi r7, r7, 6
 ; P9BE-NEXT:    mulli r8, r7, 95
 ; P9BE-NEXT:    sub r3, r3, r8
-; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    mtfprwz f1, r3
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    mulhwu r5, r3, r5
 ; P9BE-NEXT:    sub r8, r3, r5
 ; P9BE-NEXT:    srwi r8, r8, 1
 ; P9BE-NEXT:    add r5, r8, r5
 ; P9BE-NEXT:    srwi r5, r5, 6
 ; P9BE-NEXT:    mulli r8, r5, 95
-; P9BE-NEXT:    mtvsrwz v0, r5
 ; P9BE-NEXT:    sub r3, r3, r8
-; P9BE-NEXT:    mtvsrwz v2, r3
-; P9BE-NEXT:    vperm v2, v2, v4, v5
-; P9BE-NEXT:    mtvsrwz v4, r6
-; P9BE-NEXT:    xxmrghw v2, v2, v3
-; P9BE-NEXT:    mtvsrwz v3, r4
-; P9BE-NEXT:    vperm v3, v4, v3, v5
-; P9BE-NEXT:    mtvsrwz v4, r7
-; P9BE-NEXT:    vperm v4, v0, v4, v5
-; P9BE-NEXT:    xxmrghw v3, v4, v3
+; P9BE-NEXT:    mtfprwz f3, r3
+; P9BE-NEXT:    xxperm vs1, vs3, vs2
+; P9BE-NEXT:    mtfprwz f3, r5
+; P9BE-NEXT:    xxmrghw v2, vs1, vs0
+; P9BE-NEXT:    mtfprwz f0, r4
+; P9BE-NEXT:    mtfprwz f1, r6
+; P9BE-NEXT:    xxperm vs0, vs1, vs2
+; P9BE-NEXT:    mtfprwz f1, r7
+; P9BE-NEXT:    xxperm vs1, vs3, vs2
+; P9BE-NEXT:    xxmrghw v3, vs1, vs0
 ; P9BE-NEXT:    vadduhm v2, v2, v3
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: combine_urem_udiv:
 ; P8LE:       # %bb.0:
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    lis r3, 22765
 ; P8LE-NEXT:    std r30, -16(r1) # 8-byte Folded Spill

 ;
 ; P9BE-LABEL: dont_fold_urem_power_of_two:
 ; P9BE:       # %bb.0:
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    lis r4, 22765
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    ori r4, r4, 8969
 ; P9BE-NEXT:    clrlwi r3, r3, 27
-; P9BE-NEXT:    mtvsrwz v3, r3
+; P9BE-NEXT:    mtfprwz f0, r3
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r3, r3, 26
-; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    mtfprwz f1, r3
 ; P9BE-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
 ; P9BE-NEXT:    addi r3, r3, .LCPI3_0@toc@l
-; P9BE-NEXT:    lxv v5, 0(r3)
+; P9BE-NEXT:    lxv vs2, 0(r3)
 ; P9BE-NEXT:    li r3, 6
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r3, r3, 16
-; P9BE-NEXT:    vperm v3, v4, v3, v5
+; P9BE-NEXT:    xxperm vs0, vs1, vs2
 ; P9BE-NEXT:    mulhwu r4, r3, r4
 ; P9BE-NEXT:    sub r5, r3, r4
 ; P9BE-NEXT:    srwi r5, r5, 1
 ; P9BE-NEXT:    add r4, r5, r4
 ; P9BE-NEXT:    srwi r4, r4, 6
 ; P9BE-NEXT:    mulli r4, r4, 95
 ; P9BE-NEXT:    sub r3, r3, r4
-; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    mtfprwz f1, r3
 ; P9BE-NEXT:    li r3, 4
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r3, r3, 29
-; P9BE-NEXT:    mtvsrwz v2, r3
-; P9BE-NEXT:    vperm v2, v2, v4, v5
-; P9BE-NEXT:    xxmrghw v2, v3, v2
+; P9BE-NEXT:    mtfprwz f3, r3
+; P9BE-NEXT:    xxperm vs1, vs3, vs2
+; P9BE-NEXT:    xxmrghw v2, vs0, vs1
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: dont_fold_urem_power_of_two:
 ; P8LE:       # %bb.0:
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    lis r3, 22765
 ; P8LE-NEXT:    ori r3, r3, 8969
 ; P8LE-NEXT:    mffprd r4, f0

 ; P9BE-NEXT:    ori r4, r4, 47143
 ; P9BE-NEXT:    ori r5, r5, 30865
 ; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    mulhwu r4, r3, r4
 ; P9BE-NEXT:    srwi r4, r4, 11
 ; P9BE-NEXT:    mulli r4, r4, 5423
 ; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    lis r4, -19946
-; P9BE-NEXT:    mtvsrwz v3, r3
+; P9BE-NEXT:    mtfprwz f0, r3
 ; P9BE-NEXT:    li r3, 4
 ; P9BE-NEXT:    ori r4, r4, 17097
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    mulhwu r4, r3, r4
 ; P9BE-NEXT:    srwi r4, r4, 4
 ; P9BE-NEXT:    mulli r4, r4, 23
 ; P9BE-NEXT:    sub r3, r3, r4
-; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    mtfprwz f1, r3
 ; P9BE-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
 ; P9BE-NEXT:    addi r3, r3, .LCPI4_0@toc@l
-; P9BE-NEXT:    lxv v5, 0(r3)
+; P9BE-NEXT:    lxv vs2, 0(r3)
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r4, r3, 16
 ; P9BE-NEXT:    rlwinm r3, r3, 31, 17, 31
-; P9BE-NEXT:    vperm v3, v4, v3, v5
+; P9BE-NEXT:    xxperm vs0, vs1, vs2
 ; P9BE-NEXT:    mulhwu r3, r3, r5
 ; P9BE-NEXT:    srwi r3, r3, 8
 ; P9BE-NEXT:    mulli r3, r3, 654
 ; P9BE-NEXT:    sub r3, r4, r3
-; P9BE-NEXT:    mtvsrwz v2, r3
+; P9BE-NEXT:    mtfprwz f1, r3
 ; P9BE-NEXT:    li r3, 0
-; P9BE-NEXT:    mtvsrwz v4, r3
-; P9BE-NEXT:    vperm v2, v4, v2, v5
-; P9BE-NEXT:    xxmrghw v2, v2, v3
+; P9BE-NEXT:    mtfprwz f3, r3
+; P9BE-NEXT:    xxperm vs1, vs3, vs2
+; P9BE-NEXT:    xxmrghw v2, vs1, vs0
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: dont_fold_urem_one:
 ; P8LE:       # %bb.0:
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    lis r3, -14230
 ; P8LE-NEXT:    lis r7, -19946
 ; P8LE-NEXT:    lis r9, 24749

llvm/test/CodeGen/PowerPC/v16i8_scalar_to_vector_shuffle.ll

 ; CHECK-BE-P8-NEXT:    mtvsrwz v3, r4
 ; CHECK-BE-P8-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-P8-NEXT:    vperm v2, v4, v3, v2
 ; CHECK-BE-P8-NEXT:    blr
 ;
 ; CHECK-BE-P9-LABEL: test_v16i8_v16i8:
 ; CHECK-BE-P9:       # %bb.0: # %entry
 ; CHECK-BE-P9-NEXT:    addis r5, r2, .LCPI0_0@toc@ha
-; CHECK-BE-P9-NEXT:    lxsibzx v3, 0, r4
-; CHECK-BE-P9-NEXT:    lxsibzx v4, 0, r3
+; CHECK-BE-P9-NEXT:    lxsibzx v2, 0, r4
+; CHECK-BE-P9-NEXT:    lxsibzx f1, 0, r3
 ; CHECK-BE-P9-NEXT:    addi r5, r5, .LCPI0_0@toc@l
-; CHECK-BE-P9-NEXT:    lxv v2, 0(r5)
-; CHECK-BE-P9-NEXT:    vperm v2, v4, v3, v2
+; CHECK-BE-P9-NEXT:    lxv vs0, 0(r5)
+; CHECK-BE-P9-NEXT:    xxperm v2, vs1, vs0
 ; CHECK-BE-P9-NEXT:    blr
 ;
 ; CHECK-AIX-64-P8-LABEL: test_v16i8_v16i8:
 ; CHECK-AIX-64-P8:       # %bb.0: # %entry
 ; CHECK-AIX-64-P8-NEXT:    ld r5, L..C0(r2) # %const.0
 ; CHECK-AIX-64-P8-NEXT:    lbz r4, 0(r4)
 ; CHECK-AIX-64-P8-NEXT:    lbz r3, 0(r3)
 ; CHECK-AIX-64-P8-NEXT:    mtvsrwz v3, r4
 ; CHECK-AIX-64-P8-NEXT:    lxvw4x v2, 0, r5
 ; CHECK-AIX-64-P8-NEXT:    mtvsrwz v4, r3
 ; CHECK-AIX-64-P8-NEXT:    vperm v2, v4, v3, v2
 ; CHECK-AIX-64-P8-NEXT:    blr
 ;
 ; CHECK-AIX-64-P9-LABEL: test_v16i8_v16i8:
 ; CHECK-AIX-64-P9:       # %bb.0: # %entry
 ; CHECK-AIX-64-P9-NEXT:    ld r5, L..C0(r2) # %const.0
-; CHECK-AIX-64-P9-NEXT:    lxsibzx v3, 0, r4
-; CHECK-AIX-64-P9-NEXT:    lxsibzx v4, 0, r3
-; CHECK-AIX-64-P9-NEXT:    lxv v2, 0(r5)
-; CHECK-AIX-64-P9-NEXT:    vperm v2, v4, v3, v2
+; CHECK-AIX-64-P9-NEXT:    lxsibzx v2, 0, r4
+; CHECK-AIX-64-P9-NEXT:    lxsibzx f1, 0, r3
+; CHECK-AIX-64-P9-NEXT:    lxv vs0, 0(r5)
+; CHECK-AIX-64-P9-NEXT:    xxperm v2, vs1, vs0
 ; CHECK-AIX-64-P9-NEXT:    blr
 ;
 ; CHECK-AIX-32-P8-LABEL: test_v16i8_v16i8:
 ; CHECK-AIX-32-P8:       # %bb.0: # %entry
 ; CHECK-AIX-32-P8-NEXT:    lwz r5, L..C0(r2) # %const.0
 ; CHECK-AIX-32-P8-NEXT:    lbz r4, 0(r4)
 ; CHECK-AIX-32-P8-NEXT:    lbz r3, 0(r3)
 ; CHECK-AIX-32-P8-NEXT:    mtvsrwz v3, r4
 ; CHECK-AIX-32-P8-NEXT:    lxvw4x v2, 0, r5
 ; CHECK-AIX-32-P8-NEXT:    mtvsrwz v4, r3
 ; CHECK-AIX-32-P8-NEXT:    vperm v2, v4, v3, v2
 ; CHECK-AIX-32-P8-NEXT:    blr
 ;
 ; CHECK-AIX-32-P9-LABEL: test_v16i8_v16i8:
 ; CHECK-AIX-32-P9:       # %bb.0: # %entry
 ; CHECK-AIX-32-P9-NEXT:    lwz r5, L..C0(r2) # %const.0
-; CHECK-AIX-32-P9-NEXT:    lxsibzx v3, 0, r4
-; CHECK-AIX-32-P9-NEXT:    lxsibzx v4, 0, r3
-; CHECK-AIX-32-P9-NEXT:    lxv v2, 0(r5)
-; CHECK-AIX-32-P9-NEXT:    vperm v2, v4, v3, v2
+; CHECK-AIX-32-P9-NEXT:    lxsibzx v2, 0, r4
+; CHECK-AIX-32-P9-NEXT:    lxsibzx f1, 0, r3
+; CHECK-AIX-32-P9-NEXT:    lxv vs0, 0(r5)
+; CHECK-AIX-32-P9-NEXT:    xxperm v2, vs1, vs0
 ; CHECK-AIX-32-P9-NEXT:    blr
 entry:
   %0 = load <1 x i8>, ptr %a, align 4
   %bc1 = bitcast <1 x i8> %0 to i8
   %vecinit3 = insertelement <16 x i8> poison, i8 %bc1, i64 0
   %1 = load <1 x i8>, ptr %b, align 8
   %bc2 = bitcast <1 x i8> %1 to i8
   %vecinit6 = insertelement <16 x i8> undef, i8 %bc2, i64 0
entry:
   %vecins = insertelement <16 x i8> %a, i8 %b, i32 0
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @test_none_v16i8(i8 %arg, ptr nocapture noundef readonly %b) {
 ; CHECK-LE-P8-LABEL: test_none_v16i8:
 ; CHECK-LE-P8:       # %bb.0: # %entry
 ; CHECK-LE-P8-NEXT:    addis r5, r2, .LCPI2_0@toc@ha
-; CHECK-LE-P8-NEXT:    lxvd2x vs0, 0, r4
+; CHECK-LE-P8-NEXT:    lxvd2x v3, 0, r4
 ; CHECK-LE-P8-NEXT:    mtvsrd v4, r3
 ; CHECK-LE-P8-NEXT:    addi r5, r5, .LCPI2_0@toc@l
-; CHECK-LE-P8-NEXT:    lxvd2x vs1, 0, r5
+; CHECK-LE-P8-NEXT:    lxvd2x vs0, 0, r5
 ; CHECK-LE-P8-NEXT:    xxswapd v2, vs0
-; CHECK-LE-P8-NEXT:    xxswapd v3, vs1
-; CHECK-LE-P8-NEXT:    vperm v2, v4, v2, v3
+; CHECK-LE-P8-NEXT:    vperm v2, v4, v3, v2
 ; CHECK-LE-P8-NEXT:    blr
 ;
 ; CHECK-LE-P9-LABEL: test_none_v16i8:
 ; CHECK-LE-P9:       # %bb.0: # %entry
-; CHECK-LE-P9-NEXT:    mtvsrd v3, r3
+; CHECK-LE-P9-NEXT:    mtfprd f0, r3
 ; CHECK-LE-P9-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
 ; CHECK-LE-P9-NEXT:    lxv v2, 0(r4)
 ; CHECK-LE-P9-NEXT:    addi r3, r3, .LCPI2_0@toc@l
-; CHECK-LE-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-LE-P9-NEXT:    vperm v2, v3, v2, v4
+; CHECK-LE-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-LE-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-LE-P9-NEXT:    blr
 ;
 ; CHECK-BE-P8-LABEL: test_none_v16i8:
 ; CHECK-BE-P8:       # %bb.0: # %entry
 ; CHECK-BE-P8-NEXT:    addis r5, r2, .LCPI2_0@toc@ha
 ; CHECK-BE-P8-NEXT:    lxvw4x v2, 0, r4
 ; CHECK-BE-P8-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-P8-NEXT:    addi r5, r5, .LCPI2_0@toc@l
 ; CHECK-BE-P8-NEXT:    lxvw4x v3, 0, r5
 ; CHECK-BE-P8-NEXT:    vperm v2, v2, v4, v3
 ; CHECK-BE-P8-NEXT:    blr
 ;
 ; CHECK-BE-P9-LABEL: test_none_v16i8:
 ; CHECK-BE-P9:       # %bb.0: # %entry
-; CHECK-BE-P9-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-P9-NEXT:    mtfprwz f0, r3
 ; CHECK-BE-P9-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
 ; CHECK-BE-P9-NEXT:    lxv v2, 0(r4)
 ; CHECK-BE-P9-NEXT:    addi r3, r3, .LCPI2_0@toc@l
-; CHECK-BE-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-BE-P9-NEXT:    vperm v2, v2, v3, v4
+; CHECK-BE-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-BE-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-BE-P9-NEXT:    blr
 ;
 ; CHECK-AIX-64-P8-LABEL: test_none_v16i8:
 ; CHECK-AIX-64-P8:       # %bb.0: # %entry
 ; CHECK-AIX-64-P8-NEXT:    ld r5, L..C2(r2) # %const.0
 ; CHECK-AIX-64-P8-NEXT:    lxvw4x v2, 0, r4
 ; CHECK-AIX-64-P8-NEXT:    mtvsrwz v4, r3
 ; CHECK-AIX-64-P8-NEXT:    lxvw4x v3, 0, r5
 ; CHECK-AIX-64-P8-NEXT:    vperm v2, v2, v4, v3
 ; CHECK-AIX-64-P8-NEXT:    blr
 ;
 ; CHECK-AIX-64-P9-LABEL: test_none_v16i8:
 ; CHECK-AIX-64-P9:       # %bb.0: # %entry
-; CHECK-AIX-64-P9-NEXT:    mtvsrwz v3, r3
+; CHECK-AIX-64-P9-NEXT:    mtfprwz f0, r3
 ; CHECK-AIX-64-P9-NEXT:    ld r3, L..C1(r2) # %const.0
 ; CHECK-AIX-64-P9-NEXT:    lxv v2, 0(r4)
-; CHECK-AIX-64-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-AIX-64-P9-NEXT:    vperm v2, v2, v3, v4
+; CHECK-AIX-64-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-AIX-64-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-AIX-64-P9-NEXT:    blr
 ;
 ; CHECK-AIX-32-P8-LABEL: test_none_v16i8:
 ; CHECK-AIX-32-P8:       # %bb.0: # %entry
 ; CHECK-AIX-32-P8-NEXT:    addi r5, r1, -16
 ; CHECK-AIX-32-P8-NEXT:    lxvw4x v2, 0, r4
 ; CHECK-AIX-32-P8-NEXT:    stb r3, -16(r1)
 ; CHECK-AIX-32-P8-NEXT:    lxvw4x v3, 0, r5
entry:
   %shuffle = shufflevector <16 x i8> %lhs, <16 x i8> %rhs, <16 x i32> <i32 0, i32 1, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
   ret <16 x i8> %shuffle
 }
 
 define <16 x i8> @test_none_v8i16(i16 %arg, ptr nocapture noundef readonly %b) {
 ; CHECK-LE-P8-LABEL: test_none_v8i16:
 ; CHECK-LE-P8:       # %bb.0: # %entry
 ; CHECK-LE-P8-NEXT:    addis r5, r2, .LCPI5_0@toc@ha
-; CHECK-LE-P8-NEXT:    lxvd2x vs0, 0, r4
+; CHECK-LE-P8-NEXT:    lxvd2x v2, 0, r4
 ; CHECK-LE-P8-NEXT:    mtvsrd v4, r3
 ; CHECK-LE-P8-NEXT:    addi r5, r5, .LCPI5_0@toc@l
-; CHECK-LE-P8-NEXT:    lxvd2x vs1, 0, r5
-; CHECK-LE-P8-NEXT:    xxswapd v2, vs0
-; CHECK-LE-P8-NEXT:    xxswapd v3, vs1
+; CHECK-LE-P8-NEXT:    lxvd2x vs0, 0, r5
+; CHECK-LE-P8-NEXT:    xxswapd v3, vs0
 ; CHECK-LE-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-LE-P8-NEXT:    blr
 ;
 ; CHECK-LE-P9-LABEL: test_none_v8i16:
 ; CHECK-LE-P9:       # %bb.0: # %entry
-; CHECK-LE-P9-NEXT:    mtvsrd v3, r3
+; CHECK-LE-P9-NEXT:    mtfprd f0, r3
 ; CHECK-LE-P9-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
 ; CHECK-LE-P9-NEXT:    lxv v2, 0(r4)
 ; CHECK-LE-P9-NEXT:    addi r3, r3, .LCPI5_0@toc@l
-; CHECK-LE-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-LE-P9-NEXT:    vperm v2, v3, v2, v4
+; CHECK-LE-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-LE-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-LE-P9-NEXT:    blr
 ;
 ; CHECK-BE-P8-LABEL: test_none_v8i16:
 ; CHECK-BE-P8:       # %bb.0: # %entry
 ; CHECK-BE-P8-NEXT:    addis r5, r2, .LCPI5_0@toc@ha
 ; CHECK-BE-P8-NEXT:    lxvw4x v2, 0, r4
 ; CHECK-BE-P8-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-P8-NEXT:    addi r5, r5, .LCPI5_0@toc@l
 ; CHECK-BE-P8-NEXT:    lxvw4x v3, 0, r5
 ; CHECK-BE-P8-NEXT:    vperm v2, v2, v4, v3
 ; CHECK-BE-P8-NEXT:    blr
 ;
 ; CHECK-BE-P9-LABEL: test_none_v8i16:
 ; CHECK-BE-P9:       # %bb.0: # %entry
-; CHECK-BE-P9-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-P9-NEXT:    mtfprwz f0, r3
 ; CHECK-BE-P9-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
 ; CHECK-BE-P9-NEXT:    lxv v2, 0(r4)
 ; CHECK-BE-P9-NEXT:    addi r3, r3, .LCPI5_0@toc@l
-; CHECK-BE-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-BE-P9-NEXT:    vperm v2, v2, v3, v4
+; CHECK-BE-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-BE-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-BE-P9-NEXT:    blr
 ;
 ; CHECK-AIX-64-P8-LABEL: test_none_v8i16:
 ; CHECK-AIX-64-P8:       # %bb.0: # %entry
 ; CHECK-AIX-64-P8-NEXT:    ld r5, L..C3(r2) # %const.0
 ; CHECK-AIX-64-P8-NEXT:    lxvw4x v2, 0, r4
 ; CHECK-AIX-64-P8-NEXT:    mtvsrwz v4, r3
 ; CHECK-AIX-64-P8-NEXT:    lxvw4x v3, 0, r5
 ; CHECK-AIX-64-P8-NEXT:    vperm v2, v2, v4, v3
 ; CHECK-AIX-64-P8-NEXT:    blr
 ;
 ; CHECK-AIX-64-P9-LABEL: test_none_v8i16:
 ; CHECK-AIX-64-P9:       # %bb.0: # %entry
-; CHECK-AIX-64-P9-NEXT:    mtvsrwz v3, r3
+; CHECK-AIX-64-P9-NEXT:    mtfprwz f0, r3
 ; CHECK-AIX-64-P9-NEXT:    ld r3, L..C2(r2) # %const.0
 ; CHECK-AIX-64-P9-NEXT:    lxv v2, 0(r4)
-; CHECK-AIX-64-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-AIX-64-P9-NEXT:    vperm v2, v2, v3, v4
+; CHECK-AIX-64-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-AIX-64-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-AIX-64-P9-NEXT:    blr
 ;
 ; CHECK-AIX-32-P8-LABEL: test_none_v8i16:
 ; CHECK-AIX-32-P8:       # %bb.0: # %entry
 ; CHECK-AIX-32-P8-NEXT:    addi r5, r1, -16
 ; CHECK-AIX-32-P8-NEXT:    lxvw4x v2, 0, r4
 ; CHECK-AIX-32-P8-NEXT:    sth r3, -16(r1)
 ; CHECK-AIX-32-P8-NEXT:    lxvw4x v3, 0, r5

 ; CHECK-LE-P8-NEXT:    blr
 ;
 ; CHECK-LE-P9-LABEL: test_v4i32_none:
 ; CHECK-LE-P9:       # %bb.0: # %entry
 ; CHECK-LE-P9-NEXT:    lxsiwzx v2, 0, r3
 ; CHECK-LE-P9-NEXT:    addis r3, r2, .LCPI10_0@toc@ha
 ; CHECK-LE-P9-NEXT:    lxsibzx v3, 0, r4
 ; CHECK-LE-P9-NEXT:    addi r3, r3, .LCPI10_0@toc@l
-; CHECK-LE-P9-NEXT:    lxv v4, 0(r3)
+; CHECK-LE-P9-NEXT:    lxv vs0, 0(r3)
 ; CHECK-LE-P9-NEXT:    vspltb v3, v3, 7
-; CHECK-LE-P9-NEXT:    vperm v2, v3, v2, v4
+; CHECK-LE-P9-NEXT:    xxperm v2, v3, vs0
 ; CHECK-LE-P9-NEXT:    blr
 ;
 ; CHECK-BE-P8-LABEL: test_v4i32_none:
 ; CHECK-BE-P8:       # %bb.0: # %entry
 ; CHECK-BE-P8-NEXT:    lbzx r4, 0, r4
 ; CHECK-BE-P8-NEXT:    addis r5, r2, .LCPI10_0@toc@ha
 ; CHECK-BE-P8-NEXT:    lxsiwzx v3, 0, r3
 ; CHECK-BE-P8-NEXT:    mtvsrwz v2, r4
 ; CHECK-BE-P8-NEXT:    addi r4, r5, .LCPI10_0@toc@l
 ; CHECK-BE-P8-NEXT:    lxvw4x v4, 0, r4
 ; CHECK-BE-P8-NEXT:    vspltb v2, v2, 7
 ; CHECK-BE-P8-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-BE-P8-NEXT:    blr
 ;
 ; CHECK-BE-P9-LABEL: test_v4i32_none:
 ; CHECK-BE-P9:       # %bb.0: # %entry
-; CHECK-BE-P9-NEXT:    lxsiwzx v2, 0, r3
+; CHECK-BE-P9-NEXT:    lfiwzx f0, 0, r3
 ; CHECK-BE-P9-NEXT:    addis r3, r2, .LCPI10_0@toc@ha
-; CHECK-BE-P9-NEXT:    lxsibzx v3, 0, r4
+; CHECK-BE-P9-NEXT:    lxsibzx v2, 0, r4
 ; CHECK-BE-P9-NEXT:    addi r3, r3, .LCPI10_0@toc@l
-; CHECK-BE-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-BE-P9-NEXT:    vspltb v3, v3, 7
-; CHECK-BE-P9-NEXT:    vperm v2, v2, v3, v4
+; CHECK-BE-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-BE-P9-NEXT:    vspltb v2, v2, 7
+; CHECK-BE-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-BE-P9-NEXT:    blr
 ;
 ; CHECK-AIX-64-P8-LABEL: test_v4i32_none:
 ; CHECK-AIX-64-P8:       # %bb.0: # %entry
 ; CHECK-AIX-64-P8-NEXT:    lbzx r4, 0, r4
 ; CHECK-AIX-64-P8-NEXT:    ld r5, L..C7(r2) # %const.0
 ; CHECK-AIX-64-P8-NEXT:    lxsiwzx v3, 0, r3
 ; CHECK-AIX-64-P8-NEXT:    mtvsrwz v2, r4
 ; CHECK-AIX-64-P8-NEXT:    lxvw4x v4, 0, r5
 ; CHECK-AIX-64-P8-NEXT:    vspltb v2, v2, 7
 ; CHECK-AIX-64-P8-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-AIX-64-P8-NEXT:    blr
 ;
 ; CHECK-AIX-64-P9-LABEL: test_v4i32_none:
 ; CHECK-AIX-64-P9:       # %bb.0: # %entry
-; CHECK-AIX-64-P9-NEXT:    lxsiwzx v2, 0, r3
+; CHECK-AIX-64-P9-NEXT:    lfiwzx f0, 0, r3
 ; CHECK-AIX-64-P9-NEXT:    ld r3, L..C3(r2) # %const.0
-; CHECK-AIX-64-P9-NEXT:    lxsibzx v3, 0, r4
-; CHECK-AIX-64-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-AIX-64-P9-NEXT:    vspltb v3, v3, 7
-; CHECK-AIX-64-P9-NEXT:    vperm v2, v2, v3, v4
+; CHECK-AIX-64-P9-NEXT:    lxsibzx v2, 0, r4
+; CHECK-AIX-64-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-AIX-64-P9-NEXT:    vspltb v2, v2, 7
+; CHECK-AIX-64-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-AIX-64-P9-NEXT:    blr
 ;
 ; CHECK-AIX-32-P8-LABEL: test_v4i32_none:
 ; CHECK-AIX-32-P8:       # %bb.0: # %entry
 ; CHECK-AIX-32-P8-NEXT:    lbzx r4, 0, r4
 ; CHECK-AIX-32-P8-NEXT:    lwz r5, L..C5(r2) # %const.0
 ; CHECK-AIX-32-P8-NEXT:    lxsiwzx v3, 0, r3
 ; CHECK-AIX-32-P8-NEXT:    mtvsrwz v2, r4
 ; CHECK-AIX-32-P8-NEXT:    lxvw4x v4, 0, r5
 ; CHECK-AIX-32-P8-NEXT:    vspltb v2, v2, 7
 ; CHECK-AIX-32-P8-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-AIX-32-P8-NEXT:    blr
 ;
 ; CHECK-AIX-32-P9-LABEL: test_v4i32_none:
 ; CHECK-AIX-32-P9:       # %bb.0: # %entry
-; CHECK-AIX-32-P9-NEXT:    lxsiwzx v2, 0, r3
+; CHECK-AIX-32-P9-NEXT:    lfiwzx f0, 0, r3
 ; CHECK-AIX-32-P9-NEXT:    lwz r3, L..C1(r2) # %const.0
-; CHECK-AIX-32-P9-NEXT:    lxsibzx v3, 0, r4
-; CHECK-AIX-32-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-AIX-32-P9-NEXT:    vspltb v3, v3, 7
-; CHECK-AIX-32-P9-NEXT:    vperm v2, v2, v3, v4
+; CHECK-AIX-32-P9-NEXT:    lxsibzx v2, 0, r4
+; CHECK-AIX-32-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-AIX-32-P9-NEXT:    vspltb v2, v2, 7
+; CHECK-AIX-32-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-AIX-32-P9-NEXT:    blr
 entry:
   %0 = load <4 x i8>, ptr %a, align 4
   %bc1 = bitcast <4 x i8> %0 to i32
   %vecinit3 = insertelement <4 x i32> poison, i32 %bc1, i64 0
   %1 = load <1 x i8>, ptr %b, align 8
   %bc2 = bitcast <1 x i8> %1 to i8
   %vecinit6 = insertelement <16 x i8> undef, i8 %bc2, i64 0

 ; CHECK-LE-P8-NEXT:    xxswapd v4, vs0
 ; CHECK-LE-P8-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-LE-P8-NEXT:    blr
 ;
 ; CHECK-LE-P9-LABEL: test_1_2:
 ; CHECK-LE-P9:       # %bb.0: # %entry
 ; CHECK-LE-P9-NEXT:    lxsibzx v2, 0, r3
 ; CHECK-LE-P9-NEXT:    addis r3, r2, .LCPI13_0@toc@ha
-; CHECK-LE-P9-NEXT:    lxsd v3, 0(r4)
+; CHECK-LE-P9-NEXT:    lfd f0, 0(r4)
 ; CHECK-LE-P9-NEXT:    addi r3, r3, .LCPI13_0@toc@l
-; CHECK-LE-P9-NEXT:    lxv v4, 0(r3)
+; CHECK-LE-P9-NEXT:    lxv vs1, 0(r3)
 ; CHECK-LE-P9-NEXT:    vspltb v2, v2, 7
-; CHECK-LE-P9-NEXT:    vperm v2, v3, v2, v4
+; CHECK-LE-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-LE-P9-NEXT:    blr
 ;
 ; CHECK-BE-P8-LABEL: test_1_2:
 ; CHECK-BE-P8:       # %bb.0: # %entry
 ; CHECK-BE-P8-NEXT:    lbzx r3, 0, r3
 ; CHECK-BE-P8-NEXT:    lxsdx v3, 0, r4
 ; CHECK-BE-P8-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-P8-NEXT:    vspltb v2, v2, 7

 ; CHECK-AIX-32-P8-NEXT:    vspltb v2, v2, 7
 ; CHECK-AIX-32-P8-NEXT:    vperm v2, v2, v3, v4
 ; CHECK-AIX-32-P8-NEXT:    blr
 ;
 ; CHECK-AIX-32-P9-LABEL: test_1_2:
 ; CHECK-AIX-32-P9:       # %bb.0: # %entry
 ; CHECK-AIX-32-P9-NEXT:    lxsibzx v2, 0, r3
 ; CHECK-AIX-32-P9-NEXT:    lwz r3, L..C2(r2) # %const.0
-; CHECK-AIX-32-P9-NEXT:    lxsiwzx v3, 0, r4
-; CHECK-AIX-32-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-AIX-32-P9-NEXT:    vspltb v2, v2, 7
-; CHECK-AIX-32-P9-NEXT:    vperm v2, v2, v3, v4
+; CHECK-AIX-32-P9-NEXT:    vspltb v3, v2, 7
+; CHECK-AIX-32-P9-NEXT:    lxsiwzx v2, 0, r4
+; CHECK-AIX-32-P9-NEXT:    lxv vs0, 0(r3)
+; CHECK-AIX-32-P9-NEXT:    xxperm v2, v3, vs0
 ; CHECK-AIX-32-P9-NEXT:    blr
 entry:
   %0 = load <1 x i8>, ptr %a, align 4
   %bc1 = bitcast <1 x i8> %0 to i8
   %vecinit3 = insertelement <16 x i8> poison, i8 %bc1, i64 0
   %1 = load <2 x i8>, ptr %b, align 8
   %bc2 = bitcast <2 x i8> %1 to i16
   %vecinit6 = insertelement <8 x i16> undef, i16 %bc2, i64 0

 ; CHECK-LE-P8-NEXT:    xxswapd v4, vs0
 ; CHECK-LE-P8-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-LE-P8-NEXT:    blr
 ;
 ; CHECK-LE-P9-LABEL: test_none_v2i64:
 ; CHECK-LE-P9:       # %bb.0: # %entry
 ; CHECK-LE-P9-NEXT:    lxsibzx v2, 0, r3
 ; CHECK-LE-P9-NEXT:    addis r3, r2, .LCPI14_0@toc@ha
-; CHECK-LE-P9-NEXT:    lxsd v3, 0(r4)
+; CHECK-LE-P9-NEXT:    lfd f0, 0(r4)
 ; CHECK-LE-P9-NEXT:    addi r3, r3, .LCPI14_0@toc@l
-; CHECK-LE-P9-NEXT:    lxv v4, 0(r3)
+; CHECK-LE-P9-NEXT:    lxv vs1, 0(r3)
 ; CHECK-LE-P9-NEXT:    vspltb v2, v2, 7
-; CHECK-LE-P9-NEXT:    vperm v2, v3, v2, v4
+; CHECK-LE-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-LE-P9-NEXT:    blr
 ;
 ; CHECK-BE-P8-LABEL: test_none_v2i64:
 ; CHECK-BE-P8:       # %bb.0: # %entry
 ; CHECK-BE-P8-NEXT:    lbzx r3, 0, r3
 ; CHECK-BE-P8-NEXT:    lxsdx v3, 0, r4
 ; CHECK-BE-P8-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-P8-NEXT:    vspltb v2, v2, 7

 ; CHECK-AIX-32-P8-NEXT:    vspltb v2, v2, 7
 ; CHECK-AIX-32-P8-NEXT:    vperm v2, v2, v3, v4
 ; CHECK-AIX-32-P8-NEXT:    blr
 ;
 ; CHECK-AIX-32-P9-LABEL: test_none_v2i64:
 ; CHECK-AIX-32-P9:       # %bb.0: # %entry
 ; CHECK-AIX-32-P9-NEXT:    lxsibzx v2, 0, r3
 ; CHECK-AIX-32-P9-NEXT:    lwz r3, L..C3(r2) # %const.0
-; CHECK-AIX-32-P9-NEXT:    lxsiwzx v3, 0, r4
-; CHECK-AIX-32-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-AIX-32-P9-NEXT:    vspltb v2, v2, 7
-; CHECK-AIX-32-P9-NEXT:    vperm v2, v2, v3, v4
+; CHECK-AIX-32-P9-NEXT:    vspltb v3, v2, 7
+; CHECK-AIX-32-P9-NEXT:    lxsiwzx v2, 0, r4
+; CHECK-AIX-32-P9-NEXT:    lxv vs0, 0(r3)
+; CHECK-AIX-32-P9-NEXT:    xxperm v2, v3, vs0
 ; CHECK-AIX-32-P9-NEXT:    blr
 entry:
   %0 = load <1 x i8>, ptr %a, align 4
   %bc1 = bitcast <1 x i8> %0 to i8
   %vecinit3 = insertelement <16 x i8> poison, i8 %bc1, i64 0
   %1 = load <2 x i8>, ptr %b, align 8
   %bc2 = bitcast <2 x i8> %1 to i16
   %vecinit6 = insertelement <8 x i16> undef, i16 %bc2, i64 0

 ; CHECK-LE-P8-NEXT:    blr
 ;
 ; CHECK-LE-P9-LABEL: test_v2i64_none:
 ; CHECK-LE-P9:       # %bb.0: # %entry
 ; CHECK-LE-P9-NEXT:    lxsd v2, 0(r3)
 ; CHECK-LE-P9-NEXT:    addis r3, r2, .LCPI15_0@toc@ha
 ; CHECK-LE-P9-NEXT:    lxsibzx v3, 0, r4
 ; CHECK-LE-P9-NEXT:    addi r3, r3, .LCPI15_0@toc@l
-; CHECK-LE-P9-NEXT:    lxv v4, 0(r3)
+; CHECK-LE-P9-NEXT:    lxv vs0, 0(r3)
 ; CHECK-LE-P9-NEXT:    vspltb v3, v3, 7
-; CHECK-LE-P9-NEXT:    vperm v2, v3, v2, v4
+; CHECK-LE-P9-NEXT:    xxperm v2, v3, vs0
 ; CHECK-LE-P9-NEXT:    blr
 ;
 ; CHECK-BE-P8-LABEL: test_v2i64_none:
 ; CHECK-BE-P8:       # %bb.0: # %entry
 ; CHECK-BE-P8-NEXT:    lbzx r4, 0, r4
 ; CHECK-BE-P8-NEXT:    lxsdx v3, 0, r3
 ; CHECK-BE-P8-NEXT:    mtvsrwz v2, r4
 ; CHECK-BE-P8-NEXT:    vspltb v2, v2, 7

 ; CHECK-BE-P8-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-P8-NEXT:    lxvw4x v2, 0, r5
 ; CHECK-BE-P8-NEXT:    vperm v2, v4, v3, v2
 ; CHECK-BE-P8-NEXT:    blr
 ;
 ; CHECK-BE-P9-LABEL: test_v8i16_v8i16rhs:
 ; CHECK-BE-P9:       # %bb.0: # %entry
 ; CHECK-BE-P9-NEXT:    addis r5, r2, .LCPI16_0@toc@ha
-; CHECK-BE-P9-NEXT:    mtvsrwz v3, r4
-; CHECK-BE-P9-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-P9-NEXT:    mtvsrwz v2, r4
+; CHECK-BE-P9-NEXT:    mtfprwz f1, r3
 ; CHECK-BE-P9-NEXT:    addi r5, r5, .LCPI16_0@toc@l
-; CHECK-BE-P9-NEXT:    lxv v2, 0(r5)
-; CHECK-BE-P9-NEXT:    vperm v2, v4, v3, v2
+; CHECK-BE-P9-NEXT:    lxv vs0, 0(r5)
+; CHECK-BE-P9-NEXT:    xxperm v2, vs1, vs0
 ; CHECK-BE-P9-NEXT:    blr
 ;
 ; CHECK-AIX-64-P8-LABEL: test_v8i16_v8i16rhs:
 ; CHECK-AIX-64-P8:       # %bb.0: # %entry
 ; CHECK-AIX-64-P8-NEXT:    ld r5, L..C8(r2) # %const.0
 ; CHECK-AIX-64-P8-NEXT:    mtvsrwz v2, r4
 ; CHECK-AIX-64-P8-NEXT:    mtvsrwz v4, r3
 ; CHECK-AIX-64-P8-NEXT:    lxvw4x v3, 0, r5
 ; CHECK-AIX-64-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-AIX-64-P8-NEXT:    blr
 ;
 ; CHECK-AIX-64-P9-LABEL: test_v8i16_v8i16rhs:
 ; CHECK-AIX-64-P9:       # %bb.0: # %entry
 ; CHECK-AIX-64-P9-NEXT:    ld r5, L..C4(r2) # %const.0
-; CHECK-AIX-64-P9-NEXT:    mtvsrwz v3, r4
-; CHECK-AIX-64-P9-NEXT:    mtvsrwz v4, r3
-; CHECK-AIX-64-P9-NEXT:    lxv v2, 0(r5)
-; CHECK-AIX-64-P9-NEXT:    vperm v2, v4, v3, v2
+; CHECK-AIX-64-P9-NEXT:    mtvsrwz v2, r4
+; CHECK-AIX-64-P9-NEXT:    mtfprwz f1, r3
+; CHECK-AIX-64-P9-NEXT:    lxv vs0, 0(r5)
+; CHECK-AIX-64-P9-NEXT:    xxperm v2, vs1, vs0
 ; CHECK-AIX-64-P9-NEXT:    blr
 ;
 ; CHECK-AIX-32-P8-LABEL: test_v8i16_v8i16rhs:
 ; CHECK-AIX-32-P8:       # %bb.0: # %entry
 ; CHECK-AIX-32-P8-NEXT:    sth r4, -16(r1)
 ; CHECK-AIX-32-P8-NEXT:    sth r3, -32(r1)
 ; CHECK-AIX-32-P8-NEXT:    addi r3, r1, -16
 ; CHECK-AIX-32-P8-NEXT:    addi r4, r1, -32

 ; CHECK-AIX-32-P8-NEXT:    lxsiwzx v3, 0, r4
 ; CHECK-AIX-32-P8-NEXT:    xxspltw v2, vs0, 1
 ; CHECK-AIX-32-P8-NEXT:    lxvw4x v4, 0, r5
 ; CHECK-AIX-32-P8-NEXT:    vperm v2, v2, v3, v4
 ; CHECK-AIX-32-P8-NEXT:    blr
 ;
 ; CHECK-AIX-32-P9-LABEL: test_v2i64_v2i64:
 ; CHECK-AIX-32-P9:       # %bb.0: # %entry
-; CHECK-AIX-32-P9-NEXT:    lxvwsx v2, 0, r3
+; CHECK-AIX-32-P9-NEXT:    lxvwsx vs0, 0, r3
 ; CHECK-AIX-32-P9-NEXT:    lwz r3, L..C4(r2) # %const.0
-; CHECK-AIX-32-P9-NEXT:    lxsiwzx v3, 0, r4
-; CHECK-AIX-32-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-AIX-32-P9-NEXT:    vperm v2, v2, v3, v4
+; CHECK-AIX-32-P9-NEXT:    lxsiwzx v2, 0, r4
+; CHECK-AIX-32-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-AIX-32-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-AIX-32-P9-NEXT:    blr
 entry:
   %0 = load <8 x i8>, ptr %a, align 4
   %bc1 = bitcast <8 x i8> %0 to i64
   %vecinit3 = insertelement <2 x i64> poison, i64 %bc1, i64 0
   %1 = load <2 x i8>, ptr %b, align 8
   %bc2 = bitcast <2 x i8> %1 to i16
   %vecinit6 = insertelement <8 x i16> undef, i16 %bc2, i64 0

 ;
 ; CHECK-LE-P9-LABEL: test_v4i32_v2i64:
 ; CHECK-LE-P9:       # %bb.0: # %entry
 ; CHECK-LE-P9-NEXT:    lfiwzx f0, 0, r3
 ; CHECK-LE-P9-NEXT:    addis r3, r2, .LCPI24_0@toc@ha
 ; CHECK-LE-P9-NEXT:    addi r3, r3, .LCPI24_0@toc@l
 ; CHECK-LE-P9-NEXT:    xxswapd v2, f0
 ; CHECK-LE-P9-NEXT:    lfd f0, 0(r4)
-; CHECK-LE-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-LE-P9-NEXT:    xxswapd v3, f0
-; CHECK-LE-P9-NEXT:    vperm v2, v3, v2, v4
+; CHECK-LE-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-LE-P9-NEXT:    xxswapd vs0, f0
+; CHECK-LE-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-LE-P9-NEXT:    blr
 ;
 ; CHECK-BE-P8-LABEL: test_v4i32_v2i64:
 ; CHECK-BE-P8:       # %bb.0: # %entry
 ; CHECK-BE-P8-NEXT:    lfiwzx f0, 0, r3
 ; CHECK-BE-P8-NEXT:    addis r5, r2, .LCPI24_0@toc@ha
 ; CHECK-BE-P8-NEXT:    lxsdx v3, 0, r4
 ; CHECK-BE-P8-NEXT:    addi r3, r5, .LCPI24_0@toc@l
 ; CHECK-BE-P8-NEXT:    lxvw4x v4, 0, r3
 ; CHECK-BE-P8-NEXT:    xxsldwi v2, f0, f0, 1
 ; CHECK-BE-P8-NEXT:    vperm v2, v2, v3, v4
 ; CHECK-BE-P8-NEXT:    blr
 ;
 ; CHECK-BE-P9-LABEL: test_v4i32_v2i64:
 ; CHECK-BE-P9:       # %bb.0: # %entry
 ; CHECK-BE-P9-NEXT:    lfiwzx f0, 0, r3
 ; CHECK-BE-P9-NEXT:    addis r3, r2, .LCPI24_0@toc@ha
-; CHECK-BE-P9-NEXT:    lxsd v3, 0(r4)
+; CHECK-BE-P9-NEXT:    lxsd v2, 0(r4)
 ; CHECK-BE-P9-NEXT:    addi r3, r3, .LCPI24_0@toc@l
-; CHECK-BE-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-BE-P9-NEXT:    xxsldwi v2, f0, f0, 1
-; CHECK-BE-P9-NEXT:    vperm v2, v2, v3, v4
+; CHECK-BE-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-BE-P9-NEXT:    xxsldwi vs0, f0, f0, 1
+; CHECK-BE-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-BE-P9-NEXT:    blr
 ;
 ; CHECK-AIX-64-P8-LABEL: test_v4i32_v2i64:
 ; CHECK-AIX-64-P8:       # %bb.0: # %entry
 ; CHECK-AIX-64-P8-NEXT:    ld r5, L..C9(r2) # %const.0
 ; CHECK-AIX-64-P8-NEXT:    lfiwzx f0, 0, r3
 ; CHECK-AIX-64-P8-NEXT:    lxsdx v3, 0, r4
 ; CHECK-AIX-64-P8-NEXT:    xxsldwi v2, f0, f0, 1
 ; CHECK-AIX-64-P8-NEXT:    lxvw4x v4, 0, r5
 ; CHECK-AIX-64-P8-NEXT:    vperm v2, v2, v3, v4
 ; CHECK-AIX-64-P8-NEXT:    blr
 ;
 ; CHECK-AIX-64-P9-LABEL: test_v4i32_v2i64:
 ; CHECK-AIX-64-P9:       # %bb.0: # %entry
 ; CHECK-AIX-64-P9-NEXT:    lfiwzx f0, 0, r3
 ; CHECK-AIX-64-P9-NEXT:    ld r3, L..C5(r2) # %const.0
-; CHECK-AIX-64-P9-NEXT:    lxsd v3, 0(r4)
-; CHECK-AIX-64-P9-NEXT:    xxsldwi v2, f0, f0, 1
-; CHECK-AIX-64-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-AIX-64-P9-NEXT:    vperm v2, v2, v3, v4
+; CHECK-AIX-64-P9-NEXT:    lxsd v2, 0(r4)
+; CHECK-AIX-64-P9-NEXT:    xxsldwi vs0, f0, f0, 1
+; CHECK-AIX-64-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-AIX-64-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-AIX-64-P9-NEXT:    blr
 ;
 ; CHECK-AIX-32-P8-LABEL: test_v4i32_v2i64:
 ; CHECK-AIX-32-P8:       # %bb.0: # %entry
 ; CHECK-AIX-32-P8-NEXT:    lwz r5, 4(r4)
 ; CHECK-AIX-32-P8-NEXT:    lxsiwzx v2, 0, r3
 ; CHECK-AIX-32-P8-NEXT:    stw r5, -16(r1)
 ; CHECK-AIX-32-P8-NEXT:    lwz r3, 0(r4)
 ; CHECK-AIX-32-P8-NEXT:    addi r4, r1, -32
 ; CHECK-AIX-32-P8-NEXT:    stw r3, -32(r1)
 ; CHECK-AIX-32-P8-NEXT:    addi r3, r1, -16
 ; CHECK-AIX-32-P8-NEXT:    lxvw4x vs0, 0, r3
 ; CHECK-AIX-32-P8-NEXT:    lwz r3, L..C9(r2) # %const.0
 ; CHECK-AIX-32-P8-NEXT:    lxvw4x vs1, 0, r4
 ; CHECK-AIX-32-P8-NEXT:    lxvw4x v4, 0, r3
 ; CHECK-AIX-32-P8-NEXT:    xxmrghw v3, vs1, vs0
 ; CHECK-AIX-32-P8-NEXT:    vperm v2, v2, v3, v4
 ; CHECK-AIX-32-P8-NEXT:    blr
 ;
 ; CHECK-AIX-32-P9-LABEL: test_v4i32_v2i64:
 ; CHECK-AIX-32-P9:       # %bb.0: # %entry
-; CHECK-AIX-32-P9-NEXT:    lxsiwzx v2, 0, r3
+; CHECK-AIX-32-P9-NEXT:    lfiwzx f0, 0, r3
 ; CHECK-AIX-32-P9-NEXT:    lwz r3, 4(r4)
 ; CHECK-AIX-32-P9-NEXT:    stw r3, -16(r1)
 ; CHECK-AIX-32-P9-NEXT:    lwz r3, 0(r4)
-; CHECK-AIX-32-P9-NEXT:    lxv vs0, -16(r1)
+; CHECK-AIX-32-P9-NEXT:    lxv vs1, -16(r1)
 ; CHECK-AIX-32-P9-NEXT:    stw r3, -32(r1)
 ; CHECK-AIX-32-P9-NEXT:    lwz r3, L..C5(r2) # %const.0
-; CHECK-AIX-32-P9-NEXT:    lxv vs1, -32(r1)
-; CHECK-AIX-32-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-AIX-32-P9-NEXT:    xxmrghw v3, vs1, vs0
-; CHECK-AIX-32-P9-NEXT:    vperm v2, v2, v3, v4
+; CHECK-AIX-32-P9-NEXT:    lxv vs2, -32(r1)
+; CHECK-AIX-32-P9-NEXT:    xxmrghw v2, vs2, vs1
+; CHECK-AIX-32-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-AIX-32-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-AIX-32-P9-NEXT:    blr
 entry:
   %0 = load <4 x i8>, ptr %a, align 4
   %bc1 = bitcast <4 x i8> %0 to i32
   %vecinit3 = insertelement <4 x i32> poison, i32 %bc1, i64 0
   %1 = load <8 x i8>, ptr %b, align 8
   %bc2 = bitcast <8 x i8> %1 to i64
   %vecinit6 = insertelement <2 x i64> undef, i64 %bc2, i64 0
   %2 = bitcast <4 x i32> %vecinit3 to <16 x i8>
   %3 = bitcast <2 x i64> %vecinit6 to <16 x i8>
   %shuffle = shufflevector <16 x i8> %2, <16 x i8> %3, <16 x i32> <i32 0, i32 1, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
   ret <16 x i8> %shuffle
 }

llvm/test/CodeGen/PowerPC/v2i64_scalar_to_vector_shuffle.ll

 ; CHECK-AIX-32-P8-NEXT:    lxvw4x v4, 0, r4
 ; CHECK-AIX-32-P8-NEXT:    lxvw4x v3, 0, r3
 ; CHECK-AIX-32-P8-NEXT:    xxmrghw v2, vs1, vs0
 ; CHECK-AIX-32-P8-NEXT:    vperm v2, v2, v4, v3
 ; CHECK-AIX-32-P8-NEXT:    blr
 ;
 ; CHECK-AIX-32-P9-LABEL: test_v4i32_v2i64:
 ; CHECK-AIX-32-P9:       # %bb.0: # %entry
+; CHECK-AIX-32-P9-NEXT:    stw r4, -32(r1)
 ; CHECK-AIX-32-P9-NEXT:    stw r3, -48(r1)
 ; CHECK-AIX-32-P9-NEXT:    lwz r3, L..C0(r2) # %const.0
-; CHECK-AIX-32-P9-NEXT:    stw r4, -32(r1)
 ; CHECK-AIX-32-P9-NEXT:    lxv vs0, -32(r1)
 ; CHECK-AIX-32-P9-NEXT:    lxv vs1, -48(r1)
 ; CHECK-AIX-32-P9-NEXT:    stw r5, -16(r1)
-; CHECK-AIX-32-P9-NEXT:    lxv v4, -16(r1)
-; CHECK-AIX-32-P9-NEXT:    lxv v3, 0(r3)
-; CHECK-AIX-32-P9-NEXT:    xxmrghw v2, vs1, vs0
-; CHECK-AIX-32-P9-NEXT:    vperm v2, v2, v4, v3
+; CHECK-AIX-32-P9-NEXT:    lxv v2, -16(r1)
+; CHECK-AIX-32-P9-NEXT:    xxmrghw vs0, vs1, vs0
+; CHECK-AIX-32-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-AIX-32-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-AIX-32-P9-NEXT:    blr
 entry:
   %lhs.tmp = insertelement <4 x i32> undef, i32 %arg1, i32 0
   %lhs = bitcast <4 x i32> %lhs.tmp to <2 x i64>
   %rhs = insertelement <2 x i64> undef, i64 %arg, i32 0
   %shuffle = shufflevector <2 x i64> %lhs, <2 x i64> %rhs, <2 x i32> <i32 0, i32 2>
   ret <2 x i64> %shuffle
 }

llvm/test/CodeGen/PowerPC/v4i32_scalar_to_vector_shuffle.ll

 ; CHECK-LE-P8-NEXT:    xxswapd v3, vs0
 ; CHECK-LE-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-LE-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-LE-P8-NEXT:    stfdx f0, 0, r3
 ; CHECK-LE-P8-NEXT:    blr
 ;
 ; CHECK-LE-P9-LABEL: test_none_v8i16:
 ; CHECK-LE-P9:       # %bb.0: # %entry
-; CHECK-LE-P9-NEXT:    lxsihzx v2, 0, r3
-; CHECK-LE-P9-NEXT:    lxsd v3, 0(r3)
+; CHECK-LE-P9-NEXT:    lxsihzx f0, 0, r3
+; CHECK-LE-P9-NEXT:    lfd f1, 0(r3)
 ; CHECK-LE-P9-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
 ; CHECK-LE-P9-NEXT:    addi r3, r3, .LCPI0_0@toc@l
-; CHECK-LE-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-LE-P9-NEXT:    vperm v2, v2, v3, v4
-; CHECK-LE-P9-NEXT:    xxswapd vs0, v2
+; CHECK-LE-P9-NEXT:    lxv vs2, 0(r3)
+; CHECK-LE-P9-NEXT:    xxperm vs1, vs0, vs2
+; CHECK-LE-P9-NEXT:    xxswapd vs0, vs1
 ; CHECK-LE-P9-NEXT:    stfd f0, 0(r3)
 ; CHECK-LE-P9-NEXT:    blr
 ;
 ; CHECK-BE-P8-LABEL: test_none_v8i16:
 ; CHECK-BE-P8:       # %bb.0: # %entry
 ; CHECK-BE-P8-NEXT:    lhz r4, 0(r3)
 ; CHECK-BE-P8-NEXT:    lfdx f0, 0, r3
 ; CHECK-BE-P8-NEXT:    sldi r3, r4, 48

 ; CHECK-LE-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-LE-P8-NEXT:    stxvd2x vs0, 0, r5
 ; CHECK-LE-P8-NEXT:    blr
 ;
 ; CHECK-LE-P9-LABEL: test_none_v4i32:
 ; CHECK-LE-P9:       # %bb.0: # %entry
 ; CHECK-LE-P9-NEXT:    li r3, 0
 ; CHECK-LE-P9-NEXT:    vextuwrx r3, r3, v2
-; CHECK-LE-P9-NEXT:    mtvsrwz v3, r3
+; CHECK-LE-P9-NEXT:    mtfprwz f0, r3
 ; CHECK-LE-P9-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
 ; CHECK-LE-P9-NEXT:    addi r3, r3, .LCPI2_0@toc@l
-; CHECK-LE-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-LE-P9-NEXT:    vperm v2, v3, v2, v4
+; CHECK-LE-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-LE-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-LE-P9-NEXT:    stxv v2, 0(r5)
 ; CHECK-LE-P9-NEXT:    blr
 ;
 ; CHECK-BE-P8-LABEL: test_none_v4i32:
 ; CHECK-BE-P8:       # %bb.0: # %entry
 ; CHECK-BE-P8-NEXT:    xxsldwi vs0, v2, v2, 3
 ; CHECK-BE-P8-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
 ; CHECK-BE-P8-NEXT:    addi r3, r3, .LCPI2_0@toc@l
 ; CHECK-BE-P8-NEXT:    lxvw4x v3, 0, r3
 ; CHECK-BE-P8-NEXT:    mffprwz r4, f0
 ; CHECK-BE-P8-NEXT:    mtvsrwz v4, r4
 ; CHECK-BE-P8-NEXT:    vperm v2, v2, v4, v3
 ; CHECK-BE-P8-NEXT:    stxvw4x v2, 0, r5
 ; CHECK-BE-P8-NEXT:    blr
 ;
 ; CHECK-BE-P9-LABEL: test_none_v4i32:
 ; CHECK-BE-P9:       # %bb.0: # %entry
 ; CHECK-BE-P9-NEXT:    li r3, 0
 ; CHECK-BE-P9-NEXT:    vextuwlx r3, r3, v2
-; CHECK-BE-P9-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-P9-NEXT:    mtfprwz f0, r3
 ; CHECK-BE-P9-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
 ; CHECK-BE-P9-NEXT:    addi r3, r3, .LCPI2_0@toc@l
-; CHECK-BE-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-BE-P9-NEXT:    vperm v2, v2, v3, v4
-; CHECK-BE-P9-NEXT:    stxv v2, 0(r5)
+; CHECK-BE-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-BE-P9-NEXT:    xxperm vs0, v2, vs1
+; CHECK-BE-P9-NEXT:    stxv vs0, 0(r5)
 ; CHECK-BE-P9-NEXT:    blr
 ;
 ; CHECK-AIX-64-P8-LABEL: test_none_v4i32:
 ; CHECK-AIX-64-P8:       # %bb.0: # %entry
 ; CHECK-AIX-64-P8-NEXT:    xxsldwi vs0, v2, v2, 3
 ; CHECK-AIX-64-P8-NEXT:    ld r4, L..C0(r2) # %const.0
 ; CHECK-AIX-64-P8-NEXT:    mffprwz r5, f0
 ; CHECK-AIX-64-P8-NEXT:    lxvw4x v3, 0, r4
 ; CHECK-AIX-64-P8-NEXT:    mtvsrwz v4, r5
 ; CHECK-AIX-64-P8-NEXT:    vperm v2, v2, v4, v3
 ; CHECK-AIX-64-P8-NEXT:    stxvw4x v2, 0, r3
 ; CHECK-AIX-64-P8-NEXT:    blr
 ;
 ; CHECK-AIX-64-P9-LABEL: test_none_v4i32:
 ; CHECK-AIX-64-P9:       # %bb.0: # %entry
 ; CHECK-AIX-64-P9-NEXT:    li r4, 0
 ; CHECK-AIX-64-P9-NEXT:    vextuwlx r4, r4, v2
-; CHECK-AIX-64-P9-NEXT:    mtvsrwz v3, r4
+; CHECK-AIX-64-P9-NEXT:    mtfprwz f0, r4
 ; CHECK-AIX-64-P9-NEXT:    ld r4, L..C0(r2) # %const.0
-; CHECK-AIX-64-P9-NEXT:    lxv v4, 0(r4)
-; CHECK-AIX-64-P9-NEXT:    vperm v2, v2, v3, v4
-; CHECK-AIX-64-P9-NEXT:    stxv v2, 0(r3)
+; CHECK-AIX-64-P9-NEXT:    lxv vs1, 0(r4)
+; CHECK-AIX-64-P9-NEXT:    xxperm vs0, v2, vs1
+; CHECK-AIX-64-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-AIX-64-P9-NEXT:    blr
 ;
 ; CHECK-AIX-32-P8-LABEL: test_none_v4i32:
 ; CHECK-AIX-32-P8:       # %bb.0: # %entry
 ; CHECK-AIX-32-P8-NEXT:    lwz r4, L..C0(r2) # %const.0
 ; CHECK-AIX-32-P8-NEXT:    addi r5, r1, -16
 ; CHECK-AIX-32-P8-NEXT:    stxvw4x v2, 0, r5
 ; CHECK-AIX-32-P8-NEXT:    lxsiwzx v3, 0, r5
 ; CHECK-AIX-32-P8-NEXT:    lxvw4x v4, 0, r4
 ; CHECK-AIX-32-P8-NEXT:    vperm v2, v2, v3, v4
 ; CHECK-AIX-32-P8-NEXT:    stxvw4x v2, 0, r3
 ; CHECK-AIX-32-P8-NEXT:    blr
 ;
 ; CHECK-AIX-32-P9-LABEL: test_none_v4i32:
 ; CHECK-AIX-32-P9:       # %bb.0: # %entry
 ; CHECK-AIX-32-P9-NEXT:    addi r4, r1, -16
 ; CHECK-AIX-32-P9-NEXT:    stxv v2, -16(r1)
-; CHECK-AIX-32-P9-NEXT:    lxsiwzx v3, 0, r4
+; CHECK-AIX-32-P9-NEXT:    lfiwzx f0, 0, r4
 ; CHECK-AIX-32-P9-NEXT:    lwz r4, L..C0(r2) # %const.0
-; CHECK-AIX-32-P9-NEXT:    lxv v4, 0(r4)
-; CHECK-AIX-32-P9-NEXT:    vperm v2, v2, v3, v4
-; CHECK-AIX-32-P9-NEXT:    stxv v2, 0(r3)
+; CHECK-AIX-32-P9-NEXT:    lxv vs1, 0(r4)
+; CHECK-AIX-32-P9-NEXT:    xxperm vs0, v2, vs1
+; CHECK-AIX-32-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-AIX-32-P9-NEXT:    blr
 entry:
   %0 = extractelement <2 x i32> %vec, i64 0
   %1 = bitcast i32 %0 to <2 x i16>
   %2 = shufflevector <2 x i16> %1, <2 x i16> %1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
   %3 = shufflevector <2 x i32> %vec, <2 x i32> %vec, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   %4 = bitcast <4 x i32> %3 to <8 x i16>
   %5 = shufflevector <8 x i16> %4, <8 x i16> %2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 9>

 ; CHECK-LE-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-LE-P8-NEXT:    stxvd2x vs0, 0, r5
 ; CHECK-LE-P8-NEXT:    blr
 ;
 ; CHECK-LE-P9-LABEL: test_v4i32_none:
 ; CHECK-LE-P9:       # %bb.0: # %entry
 ; CHECK-LE-P9-NEXT:    li r3, 0
 ; CHECK-LE-P9-NEXT:    vextuwrx r3, r3, v2
-; CHECK-LE-P9-NEXT:    mtvsrwz v3, r3
+; CHECK-LE-P9-NEXT:    mtfprwz f0, r3
 ; CHECK-LE-P9-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
 ; CHECK-LE-P9-NEXT:    addi r3, r3, .LCPI3_0@toc@l
-; CHECK-LE-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-LE-P9-NEXT:    vperm v2, v2, v3, v4
-; CHECK-LE-P9-NEXT:    stxv v2, 0(r5)
+; CHECK-LE-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-LE-P9-NEXT:    xxperm vs0, v2, vs1
+; CHECK-LE-P9-NEXT:    stxv vs0, 0(r5)
 ; CHECK-LE-P9-NEXT:    blr
 ;
 ; CHECK-BE-P8-LABEL: test_v4i32_none:
 ; CHECK-BE-P8:       # %bb.0: # %entry
 ; CHECK-BE-P8-NEXT:    xxsldwi vs0, v2, v2, 3
 ; CHECK-BE-P8-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
 ; CHECK-BE-P8-NEXT:    addi r3, r3, .LCPI3_0@toc@l
 ; CHECK-BE-P8-NEXT:    lxvw4x v3, 0, r3
 ; CHECK-BE-P8-NEXT:    mffprwz r4, f0
 ; CHECK-BE-P8-NEXT:    mtvsrwz v4, r4
 ; CHECK-BE-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-BE-P8-NEXT:    stxvw4x v2, 0, r5
 ; CHECK-BE-P8-NEXT:    blr
 ;
 ; CHECK-BE-P9-LABEL: test_v4i32_none:
 ; CHECK-BE-P9:       # %bb.0: # %entry
 ; CHECK-BE-P9-NEXT:    li r3, 0
 ; CHECK-BE-P9-NEXT:    vextuwlx r3, r3, v2
-; CHECK-BE-P9-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-P9-NEXT:    mtfprwz f0, r3
 ; CHECK-BE-P9-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
 ; CHECK-BE-P9-NEXT:    addi r3, r3, .LCPI3_0@toc@l
-; CHECK-BE-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-BE-P9-NEXT:    vperm v2, v3, v2, v4
+; CHECK-BE-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-BE-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-BE-P9-NEXT:    stxv v2, 0(r5)
 ; CHECK-BE-P9-NEXT:    blr
 ;
 ; CHECK-AIX-64-P8-LABEL: test_v4i32_none:
 ; CHECK-AIX-64-P8:       # %bb.0: # %entry
 ; CHECK-AIX-64-P8-NEXT:    xxsldwi vs0, v2, v2, 3
 ; CHECK-AIX-64-P8-NEXT:    ld r4, L..C1(r2) # %const.0
 ; CHECK-AIX-64-P8-NEXT:    mffprwz r5, f0
 ; CHECK-AIX-64-P8-NEXT:    lxvw4x v3, 0, r4
 ; CHECK-AIX-64-P8-NEXT:    mtvsrwz v4, r5
 ; CHECK-AIX-64-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-AIX-64-P8-NEXT:    stxvw4x v2, 0, r3
 ; CHECK-AIX-64-P8-NEXT:    blr
 ;
 ; CHECK-AIX-64-P9-LABEL: test_v4i32_none:
 ; CHECK-AIX-64-P9:       # %bb.0: # %entry
 ; CHECK-AIX-64-P9-NEXT:    li r4, 0
 ; CHECK-AIX-64-P9-NEXT:    vextuwlx r4, r4, v2
-; CHECK-AIX-64-P9-NEXT:    mtvsrwz v3, r4
+; CHECK-AIX-64-P9-NEXT:    mtfprwz f0, r4
 ; CHECK-AIX-64-P9-NEXT:    ld r4, L..C1(r2) # %const.0
-; CHECK-AIX-64-P9-NEXT:    lxv v4, 0(r4)
-; CHECK-AIX-64-P9-NEXT:    vperm v2, v3, v2, v4
+; CHECK-AIX-64-P9-NEXT:    lxv vs1, 0(r4)
+; CHECK-AIX-64-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-AIX-64-P9-NEXT:    stxv v2, 0(r3)
 ; CHECK-AIX-64-P9-NEXT:    blr
 ;
 ; CHECK-AIX-32-P8-LABEL: test_v4i32_none:
 ; CHECK-AIX-32-P8:       # %bb.0: # %entry
 ; CHECK-AIX-32-P8-NEXT:    lwz r4, L..C1(r2) # %const.0
 ; CHECK-AIX-32-P8-NEXT:    addi r5, r1, -16
 ; CHECK-AIX-32-P8-NEXT:    stxvw4x v2, 0, r5
 ; CHECK-AIX-32-P8-NEXT:    lxsiwzx v3, 0, r5
 ; CHECK-AIX-32-P8-NEXT:    lxvw4x v4, 0, r4
 ; CHECK-AIX-32-P8-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-AIX-32-P8-NEXT:    stxvw4x v2, 0, r3
 ; CHECK-AIX-32-P8-NEXT:    blr
 ;
 ; CHECK-AIX-32-P9-LABEL: test_v4i32_none:
 ; CHECK-AIX-32-P9:       # %bb.0: # %entry
 ; CHECK-AIX-32-P9-NEXT:    addi r4, r1, -16
 ; CHECK-AIX-32-P9-NEXT:    stxv v2, -16(r1)
-; CHECK-AIX-32-P9-NEXT:    lxsiwzx v3, 0, r4
+; CHECK-AIX-32-P9-NEXT:    lfiwzx f0, 0, r4
 ; CHECK-AIX-32-P9-NEXT:    lwz r4, L..C1(r2) # %const.0
-; CHECK-AIX-32-P9-NEXT:    lxv v4, 0(r4)
-; CHECK-AIX-32-P9-NEXT:    vperm v2, v3, v2, v4
+; CHECK-AIX-32-P9-NEXT:    lxv vs1, 0(r4)
+; CHECK-AIX-32-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-AIX-32-P9-NEXT:    stxv v2, 0(r3)
 ; CHECK-AIX-32-P9-NEXT:    blr
 entry:
   %0 = extractelement <2 x i32> %vec, i64 0
   %1 = bitcast i32 %0 to <2 x i16>
   %2 = shufflevector <2 x i16> %1, <2 x i16> %1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
   %3 = shufflevector <2 x i32> %vec, <2 x i32> %vec, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   %4 = bitcast <4 x i32> %3 to <8 x i16>

 ; CHECK-LE-P8-NEXT:    lxsdx v3, 0, r3
 ; CHECK-LE-P8-NEXT:    xxswapd v4, vs0
 ; CHECK-LE-P8-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-LE-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-LE-P8-NEXT:    stxvd2x vs0, 0, r3
 ;
 ; CHECK-LE-P9-LABEL: test_none_v2i64:
 ; CHECK-LE-P9:       # %bb.0: # %entry
-; CHECK-LE-P9-NEXT:    lxsd v3, 0(r3)
+; CHECK-LE-P9-NEXT:    lfd f0, 0(r3)
 ; CHECK-LE-P9-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
-; CHECK-LE-P9-NEXT:    mtfprwz f0, r4
+; CHECK-LE-P9-NEXT:    mtfprwz f1, r4
 ; CHECK-LE-P9-NEXT:    addi r3, r3, .LCPI4_0@toc@l
-; CHECK-LE-P9-NEXT:    xxinsertw v2, vs0, 12
-; CHECK-LE-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-LE-P9-NEXT:    vperm v2, v3, v2, v4
+; CHECK-LE-P9-NEXT:    xxinsertw v2, vs1, 12
+; CHECK-LE-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-LE-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-LE-P9-NEXT:    stxv v2, 0(r3)
 ;
 ; CHECK-BE-P8-LABEL: test_none_v2i64:
 ; CHECK-BE-P8:       # %bb.0: # %entry
 ; CHECK-BE-P8-NEXT:    addis r5, r2, .LCPI4_0@toc@ha
 ; CHECK-BE-P8-NEXT:    mtvsrwz v4, r4
 ; CHECK-BE-P8-NEXT:    addis r4, r2, .LCPI4_1@toc@ha
 ; CHECK-BE-P8-NEXT:    addi r5, r5, .LCPI4_0@toc@l
 ; CHECK-BE-P8-NEXT:    addi r4, r4, .LCPI4_1@toc@l
 ; CHECK-BE-P8-NEXT:    lxvw4x v3, 0, r5
 ; CHECK-BE-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-BE-P8-NEXT:    lxsdx v3, 0, r3
 ; CHECK-BE-P8-NEXT:    lxvw4x v4, 0, r4
 ; CHECK-BE-P8-NEXT:    vperm v2, v2, v3, v4
 ; CHECK-BE-P8-NEXT:    stxvw4x v2, 0, r3
 ;
 ; CHECK-BE-P9-LABEL: test_none_v2i64:
 ; CHECK-BE-P9:       # %bb.0: # %entry
-; CHECK-BE-P9-NEXT:    lxsd v3, 0(r3)
+; CHECK-BE-P9-NEXT:    lfd f0, 0(r3)
 ; CHECK-BE-P9-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
-; CHECK-BE-P9-NEXT:    mtfprwz f0, r4
+; CHECK-BE-P9-NEXT:    mtfprwz f1, r4
 ; CHECK-BE-P9-NEXT:    addi r3, r3, .LCPI4_0@toc@l
-; CHECK-BE-P9-NEXT:    xxinsertw v2, vs0, 0
-; CHECK-BE-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-BE-P9-NEXT:    vperm v2, v2, v3, v4
-; CHECK-BE-P9-NEXT:    stxv v2, 0(r3)
+; CHECK-BE-P9-NEXT:    xxinsertw v2, vs1, 0
+; CHECK-BE-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-BE-P9-NEXT:    xxperm vs0, v2, vs1
+; CHECK-BE-P9-NEXT:    stxv vs0, 0(r3)
 ;
 ; CHECK-AIX-64-P8-LABEL: test_none_v2i64:
 ; CHECK-AIX-64-P8:       # %bb.0: # %entry
 ; CHECK-AIX-64-P8-NEXT:    ld r5, L..C2(r2) # %const.0
 ; CHECK-AIX-64-P8-NEXT:    mtvsrwz v4, r4
 ; CHECK-AIX-64-P8-NEXT:    ld r4, L..C3(r2) # %const.1
 ; CHECK-AIX-64-P8-NEXT:    lxvw4x v3, 0, r5
 ; CHECK-AIX-64-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-AIX-64-P8-NEXT:    lxsdx v3, 0, r3
 ; CHECK-AIX-64-P8-NEXT:    lxvw4x v4, 0, r4
 ; CHECK-AIX-64-P8-NEXT:    vperm v2, v2, v3, v4
 ; CHECK-AIX-64-P8-NEXT:    stxvw4x v2, 0, r3
 ;
 ; CHECK-AIX-64-P9-LABEL: test_none_v2i64:
 ; CHECK-AIX-64-P9:       # %bb.0: # %entry
-; CHECK-AIX-64-P9-NEXT:    lxsd v3, 0(r3)
+; CHECK-AIX-64-P9-NEXT:    lfd f0, 0(r3)
 ; CHECK-AIX-64-P9-NEXT:    ld r3, L..C2(r2) # %const.0
-; CHECK-AIX-64-P9-NEXT:    mtfprwz f0, r4
-; CHECK-AIX-64-P9-NEXT:    xxinsertw v2, vs0, 0
-; CHECK-AIX-64-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-AIX-64-P9-NEXT:    vperm v2, v2, v3, v4
-; CHECK-AIX-64-P9-NEXT:    stxv v2, 0(r3)
+; CHECK-AIX-64-P9-NEXT:    mtfprwz f1, r4
+; CHECK-AIX-64-P9-NEXT:    xxinsertw v2, vs1, 0
+; CHECK-AIX-64-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-AIX-64-P9-NEXT:    xxperm vs0, v2, vs1
+; CHECK-AIX-64-P9-NEXT:    stxv vs0, 0(r3)
 ;
 ; CHECK-AIX-32-P8-LABEL: test_none_v2i64:
 ; CHECK-AIX-32-P8:       # %bb.0: # %entry
 ; CHECK-AIX-32-P8-NEXT:    lwz r5, L..C2(r2) # %const.0
 ; CHECK-AIX-32-P8-NEXT:    lxsiwzx v3, 0, r3
 ; CHECK-AIX-32-P8-NEXT:    stw r4, -16(r1)
 ; CHECK-AIX-32-P8-NEXT:    addi r3, r1, -16
 ; CHECK-AIX-32-P8-NEXT:    lxvw4x v5, 0, r3
 ; CHECK-AIX-32-P8-NEXT:    lwz r3, L..C3(r2) # %const.1
 ; CHECK-AIX-32-P8-NEXT:    lxvw4x v4, 0, r5
 ; CHECK-AIX-32-P8-NEXT:    vperm v2, v5, v2, v4
 ; CHECK-AIX-32-P8-NEXT:    lxvw4x v4, 0, r3
 ; CHECK-AIX-32-P8-NEXT:    vperm v2, v2, v3, v4
 ; CHECK-AIX-32-P8-NEXT:    stxvw4x v2, 0, r3
 ;
 ; CHECK-AIX-32-P9-LABEL: test_none_v2i64:
 ; CHECK-AIX-32-P9:       # %bb.0: # %entry
-; CHECK-AIX-32-P9-NEXT:    lxsiwzx v3, 0, r3
+; CHECK-AIX-32-P9-NEXT:    lfiwzx f0, 0, r3
 ; CHECK-AIX-32-P9-NEXT:    lwz r3, L..C2(r2) # %const.0
-; CHECK-AIX-32-P9-NEXT:    mtfprwz f0, r4
-; CHECK-AIX-32-P9-NEXT:    xxinsertw v2, vs0, 0
-; CHECK-AIX-32-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-AIX-32-P9-NEXT:    vperm v2, v2, v3, v4
-; CHECK-AIX-32-P9-NEXT:    stxv v2, 0(r3)
+; CHECK-AIX-32-P9-NEXT:    mtfprwz f1, r4
+; CHECK-AIX-32-P9-NEXT:    xxinsertw v2, vs1, 0
+; CHECK-AIX-32-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-AIX-32-P9-NEXT:    xxperm vs0, v2, vs1
+; CHECK-AIX-32-P9-NEXT:    stxv vs0, 0(r3)
 entry:
   %0 = load <2 x i32>, ptr %ptr, align 4
   %tmp = insertelement <2 x i32> %vec, i32 %v1, i32 0
   %1 = shufflevector <2 x i32> %0, <2 x i32> %tmp, <4 x i32> <i32 3, i32 2, i32 2, i32 0>
   store <4 x i32> %1, ptr undef, align 4
   unreachable
 }
 

 ; CHECK-LE-P8-NEXT:    xxswapd v4, vs0
 ; CHECK-LE-P8-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-LE-P8-NEXT:    blr
 ;
 ; CHECK-LE-P9-LABEL: test_v4i32_v4i32:
 ; CHECK-LE-P9:       # %bb.0: # %entry
 ; CHECK-LE-P9-NEXT:    lxsiwzx v2, 0, r3
 ; CHECK-LE-P9-NEXT:    addis r3, r2, .LCPI9_0@toc@ha
-; CHECK-LE-P9-NEXT:    lxsiwzx v3, 0, r4
+; CHECK-LE-P9-NEXT:    lfiwzx f0, 0, r4
 ; CHECK-LE-P9-NEXT:    addi r3, r3, .LCPI9_0@toc@l
-; CHECK-LE-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-LE-P9-NEXT:    vperm v2, v3, v2, v4
+; CHECK-LE-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-LE-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-LE-P9-NEXT:    blr
 ;
 ; CHECK-BE-P8-LABEL: test_v4i32_v4i32:
 ; CHECK-BE-P8:       # %bb.0: # %entry
 ; CHECK-BE-P8-NEXT:    addis r5, r2, .LCPI9_0@toc@ha
 ; CHECK-BE-P8-NEXT:    lxsiwzx v2, 0, r3
 ; CHECK-BE-P8-NEXT:    lxsiwzx v3, 0, r4
 ; CHECK-BE-P8-NEXT:    addi r5, r5, .LCPI9_0@toc@l
 ; CHECK-BE-P8-NEXT:    lxvw4x v4, 0, r5
 ; CHECK-BE-P8-NEXT:    vperm v2, v2, v3, v4
 ; CHECK-BE-P8-NEXT:    blr
 ;
 ; CHECK-BE-P9-LABEL: test_v4i32_v4i32:
 ; CHECK-BE-P9:       # %bb.0: # %entry
-; CHECK-BE-P9-NEXT:    lxsiwzx v2, 0, r3
+; CHECK-BE-P9-NEXT:    lfiwzx f0, 0, r3
 ; CHECK-BE-P9-NEXT:    addis r3, r2, .LCPI9_0@toc@ha
-; CHECK-BE-P9-NEXT:    lxsiwzx v3, 0, r4
+; CHECK-BE-P9-NEXT:    lxsiwzx v2, 0, r4
 ; CHECK-BE-P9-NEXT:    addi r3, r3, .LCPI9_0@toc@l
-; CHECK-BE-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-BE-P9-NEXT:    vperm v2, v2, v3, v4
+; CHECK-BE-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-BE-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-BE-P9-NEXT:    blr
 ;
 ; CHECK-AIX-64-P8-LABEL: test_v4i32_v4i32:
 ; CHECK-AIX-64-P8:       # %bb.0: # %entry
 ; CHECK-AIX-64-P8-NEXT:    ld r5, L..C4(r2) # %const.0
 ; CHECK-AIX-64-P8-NEXT:    lxsiwzx v2, 0, r3
 ; CHECK-AIX-64-P8-NEXT:    lxsiwzx v3, 0, r4
 ; CHECK-AIX-64-P8-NEXT:    lxvw4x v4, 0, r5
 ; CHECK-AIX-64-P8-NEXT:    vperm v2, v2, v3, v4
 ; CHECK-AIX-64-P8-NEXT:    blr
 ;
 ; CHECK-AIX-64-P9-LABEL: test_v4i32_v4i32:
 ; CHECK-AIX-64-P9:       # %bb.0: # %entry
-; CHECK-AIX-64-P9-NEXT:    lxsiwzx v2, 0, r3
+; CHECK-AIX-64-P9-NEXT:    lfiwzx f0, 0, r3
 ; CHECK-AIX-64-P9-NEXT:    ld r3, L..C3(r2) # %const.0
-; CHECK-AIX-64-P9-NEXT:    lxsiwzx v3, 0, r4
-; CHECK-AIX-64-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-AIX-64-P9-NEXT:    vperm v2, v2, v3, v4
+; CHECK-AIX-64-P9-NEXT:    lxsiwzx v2, 0, r4
+; CHECK-AIX-64-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-AIX-64-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-AIX-64-P9-NEXT:    blr
 ;
 ; CHECK-AIX-32-P8-LABEL: test_v4i32_v4i32:
 ; CHECK-AIX-32-P8:       # %bb.0: # %entry
 ; CHECK-AIX-32-P8-NEXT:    lwz r5, L..C4(r2) # %const.0
 ; CHECK-AIX-32-P8-NEXT:    lxsiwzx v2, 0, r3
 ; CHECK-AIX-32-P8-NEXT:    lxsiwzx v3, 0, r4
 ; CHECK-AIX-32-P8-NEXT:    lxvw4x v4, 0, r5
 ; CHECK-AIX-32-P8-NEXT:    vperm v2, v2, v3, v4
 ; CHECK-AIX-32-P8-NEXT:    blr
 ;
 ; CHECK-AIX-32-P9-LABEL: test_v4i32_v4i32:
 ; CHECK-AIX-32-P9:       # %bb.0: # %entry
-; CHECK-AIX-32-P9-NEXT:    lxsiwzx v2, 0, r3
+; CHECK-AIX-32-P9-NEXT:    lfiwzx f0, 0, r3
 ; CHECK-AIX-32-P9-NEXT:    lwz r3, L..C3(r2) # %const.0
-; CHECK-AIX-32-P9-NEXT:    lxsiwzx v3, 0, r4
-; CHECK-AIX-32-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-AIX-32-P9-NEXT:    vperm v2, v2, v3, v4
+; CHECK-AIX-32-P9-NEXT:    lxsiwzx v2, 0, r4
+; CHECK-AIX-32-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-AIX-32-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-AIX-32-P9-NEXT:    blr
 entry:
   %load1 = load <4 x i8>, ptr %a
   %load2 = load <4 x i8>, ptr %b
   %shuffle1 = shufflevector <4 x i8> %load1, <4 x i8> %load2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   %shuffle2 = shufflevector <8 x i8> %shuffle1, <8 x i8> %shuffle1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %shuffle2
 }

llvm/test/CodeGen/PowerPC/v8i16_scalar_to_vector_shuffle.ll

 ; CHECK-LE-P8-NEXT:    xxswapd v3, vs0
 ; CHECK-LE-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-LE-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-LE-P8-NEXT:    stxvd2x vs0, 0, r3
 ; CHECK-LE-P8-NEXT:    blr
 ;
 ; CHECK-LE-P9-LABEL: test_none_v8i16:
 ; CHECK-LE-P9:       # %bb.0: # %entry
-; CHECK-LE-P9-NEXT:    lxsihzx v3, 0, r3
+; CHECK-LE-P9-NEXT:    lxsihzx f0, 0, r3
 ; CHECK-LE-P9-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
 ; CHECK-LE-P9-NEXT:    addi r3, r3, .LCPI0_0@toc@l
-; CHECK-LE-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-LE-P9-NEXT:    vperm v2, v3, v2, v4
+; CHECK-LE-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-LE-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-LE-P9-NEXT:    stxv v2, 0(r3)
 ; CHECK-LE-P9-NEXT:    blr
 ;
 ; CHECK-BE-P8-LABEL: test_none_v8i16:
 ; CHECK-BE-P8:       # %bb.0: # %entry
 ; CHECK-BE-P8-NEXT:    addis r4, r2, .LCPI0_0@toc@ha
 ; CHECK-BE-P8-NEXT:    lhz r3, 0(r3)
 ; CHECK-BE-P8-NEXT:    addi r4, r4, .LCPI0_0@toc@l
 ; CHECK-BE-P8-NEXT:    lxvw4x v3, 0, r4
 ; CHECK-BE-P8-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-P8-NEXT:    vperm v2, v2, v4, v3
 ; CHECK-BE-P8-NEXT:    stxvw4x v2, 0, r3
 ; CHECK-BE-P8-NEXT:    blr
 ;
 ; CHECK-BE-P9-LABEL: test_none_v8i16:
 ; CHECK-BE-P9:       # %bb.0: # %entry
-; CHECK-BE-P9-NEXT:    lxsihzx v3, 0, r3
+; CHECK-BE-P9-NEXT:    lxsihzx f0, 0, r3
 ; CHECK-BE-P9-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
 ; CHECK-BE-P9-NEXT:    addi r3, r3, .LCPI0_0@toc@l
-; CHECK-BE-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-BE-P9-NEXT:    vperm v2, v2, v3, v4
-; CHECK-BE-P9-NEXT:    stxv v2, 0(r3)
+; CHECK-BE-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-BE-P9-NEXT:    xxperm vs0, v2, vs1
+; CHECK-BE-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-P9-NEXT:    blr
 ;
 ; CHECK-AIX-64-P8-LABEL: test_none_v8i16:
 ; CHECK-AIX-64-P8:       # %bb.0: # %entry
 ; CHECK-AIX-64-P8-NEXT:    ld r4, L..C0(r2) # %const.0
 ; CHECK-AIX-64-P8-NEXT:    lhz r3, 0(r3)
 ; CHECK-AIX-64-P8-NEXT:    mtvsrwz v4, r3
 ; CHECK-AIX-64-P8-NEXT:    lxvw4x v3, 0, r4
 ; CHECK-AIX-64-P8-NEXT:    vperm v2, v2, v4, v3
 ; CHECK-AIX-64-P8-NEXT:    stxvw4x v2, 0, r3
 ; CHECK-AIX-64-P8-NEXT:    blr
 ;
 ; CHECK-AIX-64-P9-LABEL: test_none_v8i16:
 ; CHECK-AIX-64-P9:       # %bb.0: # %entry
-; CHECK-AIX-64-P9-NEXT:    lxsihzx v3, 0, r3
+; CHECK-AIX-64-P9-NEXT:    lxsihzx f0, 0, r3
 ; CHECK-AIX-64-P9-NEXT:    ld r3, L..C0(r2) # %const.0
-; CHECK-AIX-64-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-AIX-64-P9-NEXT:    vperm v2, v2, v3, v4
-; CHECK-AIX-64-P9-NEXT:    stxv v2, 0(r3)
+; CHECK-AIX-64-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-AIX-64-P9-NEXT:    xxperm vs0, v2, vs1
+; CHECK-AIX-64-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-AIX-64-P9-NEXT:    blr
 ;
 ; CHECK-AIX-32-P8-LABEL: test_none_v8i16:
 ; CHECK-AIX-32-P8:       # %bb.0: # %entry
 ; CHECK-AIX-32-P8-NEXT:    lwz r4, L..C0(r2) # %const.0
 ; CHECK-AIX-32-P8-NEXT:    lhz r3, 0(r3)
 ; CHECK-AIX-32-P8-NEXT:    mtvsrwz v4, r3
 ; CHECK-AIX-32-P8-NEXT:    lxvw4x v3, 0, r4
 ; CHECK-AIX-32-P8-NEXT:    vperm v2, v2, v4, v3
 ; CHECK-AIX-32-P8-NEXT:    stxvw4x v2, 0, r3
 ; CHECK-AIX-32-P8-NEXT:    blr
 ;
 ; CHECK-AIX-32-P9-LABEL: test_none_v8i16:
 ; CHECK-AIX-32-P9:       # %bb.0: # %entry
-; CHECK-AIX-32-P9-NEXT:    lxsihzx v3, 0, r3
+; CHECK-AIX-32-P9-NEXT:    lxsihzx f0, 0, r3
 ; CHECK-AIX-32-P9-NEXT:    lwz r3, L..C0(r2) # %const.0
-; CHECK-AIX-32-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-AIX-32-P9-NEXT:    vperm v2, v2, v3, v4
-; CHECK-AIX-32-P9-NEXT:    stxv v2, 0(r3)
+; CHECK-AIX-32-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-AIX-32-P9-NEXT:    xxperm vs0, v2, vs1
+; CHECK-AIX-32-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-AIX-32-P9-NEXT:    blr
 entry:
   %load0.tmp = load <2 x i8>, ptr %a0
   %load0.tmp1 = bitcast <2 x i8> %load0.tmp to i16
   %load0 = insertelement <8 x i16> %b, i16 %load0.tmp1, i64 0
   %load1.tmp = insertelement <16 x i8> %a, i8 %arg, i32 0
   %load1 = bitcast <16 x i8> %load1.tmp to <8 x i16>
   %shuff = shufflevector <8 x i16> %load0, <8 x i16> %load1, <8 x i32> <i32 9, i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>

 ; CHECK-LE-P8-NEXT:    mtvsrd v4, r3
 ; CHECK-LE-P8-NEXT:    vperm v2, v2, v4, v3
 ; CHECK-LE-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-LE-P8-NEXT:    stxvd2x vs0, 0, r3
 ; CHECK-LE-P8-NEXT:    blr
 ;
 ; CHECK-LE-P9-LABEL: test_v8i16_none:
 ; CHECK-LE-P9:       # %bb.0: # %entry
-; CHECK-LE-P9-NEXT:    lxsihzx v3, 0, r3
+; CHECK-LE-P9-NEXT:    lxsihzx f0, 0, r3
 ; CHECK-LE-P9-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
-; CHECK-LE-P9-NEXT:    mtvsrwz v4, r9
+; CHECK-LE-P9-NEXT:    mtvsrwz v3, r9
 ; CHECK-LE-P9-NEXT:    addi r3, r3, .LCPI1_0@toc@l
-; CHECK-LE-P9-NEXT:    vinsertb v2, v4, 15
-; CHECK-LE-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-LE-P9-NEXT:    vperm v2, v2, v3, v4
-; CHECK-LE-P9-NEXT:    stxv v2, 0(r3)
+; CHECK-LE-P9-NEXT:    vinsertb v2, v3, 15
+; CHECK-LE-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-LE-P9-NEXT:    xxperm vs0, v2, vs1
+; CHECK-LE-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-LE-P9-NEXT:    blr
 ;
 ; CHECK-BE-P8-LABEL: test_v8i16_none:
 ; CHECK-BE-P8:       # %bb.0: # %entry
 ; CHECK-BE-P8-NEXT:    addis r4, r2, .LCPI1_0@toc@ha
 ; CHECK-BE-P8-NEXT:    mtvsrwz v4, r9
 ; CHECK-BE-P8-NEXT:    lhz r3, 0(r3)
 ; CHECK-BE-P8-NEXT:    addi r4, r4, .LCPI1_0@toc@l
 ; CHECK-BE-P8-NEXT:    lxvw4x v3, 0, r4
 ; CHECK-BE-P8-NEXT:    addis r4, r2, .LCPI1_1@toc@ha
 ; CHECK-BE-P8-NEXT:    addi r4, r4, .LCPI1_1@toc@l
 ; CHECK-BE-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-BE-P8-NEXT:    lxvw4x v3, 0, r4
 ; CHECK-BE-P8-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-BE-P8-NEXT:    stxvw4x v2, 0, r3
 ; CHECK-BE-P8-NEXT:    blr
 ;
 ; CHECK-BE-P9-LABEL: test_v8i16_none:
 ; CHECK-BE-P9:       # %bb.0: # %entry
-; CHECK-BE-P9-NEXT:    lxsihzx v3, 0, r3
+; CHECK-BE-P9-NEXT:    lxsihzx f0, 0, r3
 ; CHECK-BE-P9-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
-; CHECK-BE-P9-NEXT:    mtvsrwz v4, r9
+; CHECK-BE-P9-NEXT:    mtvsrwz v3, r9
 ; CHECK-BE-P9-NEXT:    addi r3, r3, .LCPI1_0@toc@l
-; CHECK-BE-P9-NEXT:    vinsertb v2, v4, 0
-; CHECK-BE-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-BE-P9-NEXT:    vperm v2, v3, v2, v4
+; CHECK-BE-P9-NEXT:    vinsertb v2, v3, 0
+; CHECK-BE-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-BE-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-BE-P9-NEXT:    stxv v2, 0(r3)
 ; CHECK-BE-P9-NEXT:    blr
 ;
 ; CHECK-AIX-64-P8-LABEL: test_v8i16_none:
 ; CHECK-AIX-64-P8:       # %bb.0: # %entry
 ; CHECK-AIX-64-P8-NEXT:    ld r4, L..C1(r2) # %const.0
 ; CHECK-AIX-64-P8-NEXT:    mtvsrwz v4, r5
 ; CHECK-AIX-64-P8-NEXT:    lhz r3, 0(r3)
 ; CHECK-AIX-64-P8-NEXT:    lxvw4x v3, 0, r4
 ; CHECK-AIX-64-P8-NEXT:    ld r4, L..C2(r2) # %const.1
 ; CHECK-AIX-64-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-AIX-64-P8-NEXT:    lxvw4x v3, 0, r4
 ; CHECK-AIX-64-P8-NEXT:    mtvsrwz v4, r3
 ; CHECK-AIX-64-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-AIX-64-P8-NEXT:    stxvw4x v2, 0, r3
 ; CHECK-AIX-64-P8-NEXT:    blr
 ;
 ; CHECK-AIX-64-P9-LABEL: test_v8i16_none:
 ; CHECK-AIX-64-P9:       # %bb.0: # %entry
-; CHECK-AIX-64-P9-NEXT:    lxsihzx v3, 0, r3
+; CHECK-AIX-64-P9-NEXT:    lxsihzx f0, 0, r3
 ; CHECK-AIX-64-P9-NEXT:    ld r3, L..C1(r2) # %const.0
-; CHECK-AIX-64-P9-NEXT:    mtvsrwz v4, r5
-; CHECK-AIX-64-P9-NEXT:    vinsertb v2, v4, 0
-; CHECK-AIX-64-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-AIX-64-P9-NEXT:    vperm v2, v3, v2, v4
+; CHECK-AIX-64-P9-NEXT:    mtvsrwz v3, r5
+; CHECK-AIX-64-P9-NEXT:    vinsertb v2, v3, 0
+; CHECK-AIX-64-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-AIX-64-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-AIX-64-P9-NEXT:    stxv v2, 0(r3)
 ; CHECK-AIX-64-P9-NEXT:    blr
 ;
 ; CHECK-AIX-32-P8-LABEL: test_v8i16_none:
 ; CHECK-AIX-32-P8:       # %bb.0: # %entry
 ; CHECK-AIX-32-P8-NEXT:    lwz r4, L..C1(r2) # %const.0
 ; CHECK-AIX-32-P8-NEXT:    mtvsrwz v4, r5
 ; CHECK-AIX-32-P8-NEXT:    lhz r3, 0(r3)
 ; CHECK-AIX-32-P8-NEXT:    lxvw4x v3, 0, r4
 ; CHECK-AIX-32-P8-NEXT:    lwz r4, L..C2(r2) # %const.1
 ; CHECK-AIX-32-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-AIX-32-P8-NEXT:    lxvw4x v3, 0, r4
 ; CHECK-AIX-32-P8-NEXT:    mtvsrwz v4, r3
 ; CHECK-AIX-32-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-AIX-32-P8-NEXT:    stxvw4x v2, 0, r3
 ; CHECK-AIX-32-P8-NEXT:    blr
 ;
 ; CHECK-AIX-32-P9-LABEL: test_v8i16_none:
 ; CHECK-AIX-32-P9:       # %bb.0: # %entry
-; CHECK-AIX-32-P9-NEXT:    lxsihzx v3, 0, r3
+; CHECK-AIX-32-P9-NEXT:    lxsihzx f0, 0, r3
 ; CHECK-AIX-32-P9-NEXT:    lwz r3, L..C1(r2) # %const.0
-; CHECK-AIX-32-P9-NEXT:    mtvsrwz v4, r5
-; CHECK-AIX-32-P9-NEXT:    vinsertb v2, v4, 0
-; CHECK-AIX-32-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-AIX-32-P9-NEXT:    vperm v2, v3, v2, v4
+; CHECK-AIX-32-P9-NEXT:    mtvsrwz v3, r5
+; CHECK-AIX-32-P9-NEXT:    vinsertb v2, v3, 0
+; CHECK-AIX-32-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-AIX-32-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-AIX-32-P9-NEXT:    stxv v2, 0(r3)
 ; CHECK-AIX-32-P9-NEXT:    blr
 entry:
   %load0.tmp = load <2 x i8>, ptr %a0
   %load0.tmp1 = bitcast <2 x i8> %load0.tmp to i16
   %load0 = insertelement <8 x i16> %b, i16 %load0.tmp1, i64 0
   %load1.tmp = insertelement <16 x i8> %a, i8 %arg, i32 0
   %load1 = bitcast <16 x i8> %load1.tmp to <8 x i16>

 ; CHECK-LE-P8-NEXT:    blr
 ;
 ; CHECK-LE-P9-LABEL: test_none_v4i32:
 ; CHECK-LE-P9:       # %bb.0: # %entry
 ; CHECK-LE-P9-NEXT:    lxsiwzx v2, 0, r3
 ; CHECK-LE-P9-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
 ; CHECK-LE-P9-NEXT:    mtvsrd v3, r5
 ; CHECK-LE-P9-NEXT:    addi r3, r3, .LCPI2_0@toc@l
-; CHECK-LE-P9-NEXT:    lxv v4, 0(r3)
+; CHECK-LE-P9-NEXT:    lxv vs0, 0(r3)
 ; CHECK-LE-P9-NEXT:    addis r3, r2, .LCPI2_1@toc@ha
 ; CHECK-LE-P9-NEXT:    addi r3, r3, .LCPI2_1@toc@l
-; CHECK-LE-P9-NEXT:    vperm v3, v3, v3, v4
 ; CHECK-LE-P9-NEXT:    lxv v4, 0(r3)
+; CHECK-LE-P9-NEXT:    xxperm v3, v3, vs0
 ; CHECK-LE-P9-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-LE-P9-NEXT:    xxswapd vs0, v2
 ; CHECK-LE-P9-NEXT:    stfd f0, 0(r3)
 ; CHECK-LE-P9-NEXT:    blr
 ;
 ; CHECK-BE-P8-LABEL: test_none_v4i32:
 ; CHECK-BE-P8:       # %bb.0: # %entry
 ; CHECK-BE-P8-NEXT:    addis r4, r2, .LCPI2_0@toc@ha

 ; CHECK-BE-P8-NEXT:    blr
 ;
 ; CHECK-BE-P9-LABEL: test_none_v4i32:
 ; CHECK-BE-P9:       # %bb.0: # %entry
 ; CHECK-BE-P9-NEXT:    lxsiwzx v2, 0, r3
 ; CHECK-BE-P9-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
 ; CHECK-BE-P9-NEXT:    mtvsrwz v3, r5
 ; CHECK-BE-P9-NEXT:    addi r3, r3, .LCPI2_0@toc@l
-; CHECK-BE-P9-NEXT:    lxv v4, 0(r3)
+; CHECK-BE-P9-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-P9-NEXT:    addis r3, r2, .LCPI2_1@toc@ha
 ; CHECK-BE-P9-NEXT:    addi r3, r3, .LCPI2_1@toc@l
-; CHECK-BE-P9-NEXT:    vperm v3, v3, v3, v4
 ; CHECK-BE-P9-NEXT:    lxv v4, 0(r3)
+; CHECK-BE-P9-NEXT:    xxperm v3, v3, vs0
 ; CHECK-BE-P9-NEXT:    vperm v2, v2, v3, v4
 ; CHECK-BE-P9-NEXT:    stxsd v2, 0(r3)
 ; CHECK-BE-P9-NEXT:    blr
 ;
 ; CHECK-AIX-64-P8-LABEL: test_none_v4i32:
 ; CHECK-AIX-64-P8:       # %bb.0: # %entry
 ; CHECK-AIX-64-P8-NEXT:    ld r4, L..C3(r2) # %const.0
 ; CHECK-AIX-64-P8-NEXT:    mtvsrwz v3, r5
 ; CHECK-AIX-64-P8-NEXT:    lxvw4x v2, 0, r4
 ; CHECK-AIX-64-P8-NEXT:    ld r4, L..C4(r2) # %const.1
 ; CHECK-AIX-64-P8-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-AIX-64-P8-NEXT:    lxsiwzx v3, 0, r3
 ; CHECK-AIX-64-P8-NEXT:    lxvw4x v4, 0, r4
 ; CHECK-AIX-64-P8-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-AIX-64-P8-NEXT:    stxsdx v2, 0, r3
 ; CHECK-AIX-64-P8-NEXT:    blr
 ;
 ; CHECK-AIX-64-P9-LABEL: test_none_v4i32:
 ; CHECK-AIX-64-P9:       # %bb.0: # %entry
 ; CHECK-AIX-64-P9-NEXT:    lxsiwzx v2, 0, r3
 ; CHECK-AIX-64-P9-NEXT:    ld r3, L..C2(r2) # %const.0
 ; CHECK-AIX-64-P9-NEXT:    mtvsrwz v3, r5
-; CHECK-AIX-64-P9-NEXT:    lxv v4, 0(r3)
+; CHECK-AIX-64-P9-NEXT:    lxv vs0, 0(r3)
 ; CHECK-AIX-64-P9-NEXT:    ld r3, L..C3(r2) # %const.1
-; CHECK-AIX-64-P9-NEXT:    vperm v3, v3, v3, v4
 ; CHECK-AIX-64-P9-NEXT:    lxv v4, 0(r3)
+; CHECK-AIX-64-P9-NEXT:    xxperm v3, v3, vs0
 ; CHECK-AIX-64-P9-NEXT:    vperm v2, v2, v3, v4
 ; CHECK-AIX-64-P9-NEXT:    stxsd v2, 0(r3)
 ; CHECK-AIX-64-P9-NEXT:    blr
 ;
 ; CHECK-AIX-32-P8-LABEL: test_none_v4i32:
 ; CHECK-AIX-32-P8:       # %bb.0: # %entry
 ; CHECK-AIX-32-P8-NEXT:    addi r4, r1, -32
 ; CHECK-AIX-32-P8-NEXT:    lxsiwzx v2, 0, r3

 ; CHECK-LE-P8-NEXT:    xxswapd v3, vs0
 ; CHECK-LE-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-LE-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-LE-P8-NEXT:    stxvd2x vs0, 0, r3
 ; CHECK-LE-P8-NEXT:    blr
 ;
 ; CHECK-LE-P9-LABEL: test_v4i32_none:
 ; CHECK-LE-P9:       # %bb.0: # %entry
-; CHECK-LE-P9-NEXT:    lxsiwzx v2, 0, r3
+; CHECK-LE-P9-NEXT:    lfiwzx f0, 0, r3
 ; CHECK-LE-P9-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
-; CHECK-LE-P9-NEXT:    xxlxor v4, v4, v4
+; CHECK-LE-P9-NEXT:    xxlxor vs1, vs1, vs1
 ; CHECK-LE-P9-NEXT:    addi r3, r3, .LCPI3_0@toc@l
-; CHECK-LE-P9-NEXT:    lxv v3, 0(r3)
-; CHECK-LE-P9-NEXT:    vperm v2, v4, v2, v3
-; CHECK-LE-P9-NEXT:    stxv v2, 0(r3)
+; CHECK-LE-P9-NEXT:    lxv vs2, 0(r3)
+; CHECK-LE-P9-NEXT:    xxperm vs0, vs1, vs2
+; CHECK-LE-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-LE-P9-NEXT:    blr
 ;
 ; CHECK-BE-P8-LABEL: test_v4i32_none:
 ; CHECK-BE-P8:       # %bb.0: # %entry
 ; CHECK-BE-P8-NEXT:    addis r4, r2, .LCPI3_0@toc@ha
 ; CHECK-BE-P8-NEXT:    lxsiwzx v2, 0, r3
 ; CHECK-BE-P8-NEXT:    xxlxor v4, v4, v4
 ; CHECK-BE-P8-NEXT:    addi r4, r4, .LCPI3_0@toc@l
 ; CHECK-BE-P8-NEXT:    lxvw4x v3, 0, r4
 ; CHECK-BE-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-BE-P8-NEXT:    stxvw4x v2, 0, r3
 ; CHECK-BE-P8-NEXT:    blr
 ;
 ; CHECK-BE-P9-LABEL: test_v4i32_none:
 ; CHECK-BE-P9:       # %bb.0: # %entry
-; CHECK-BE-P9-NEXT:    lxsiwzx v2, 0, r3
+; CHECK-BE-P9-NEXT:    lfiwzx f0, 0, r3
 ; CHECK-BE-P9-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
-; CHECK-BE-P9-NEXT:    xxlxor v4, v4, v4
+; CHECK-BE-P9-NEXT:    xxlxor vs1, vs1, vs1
 ; CHECK-BE-P9-NEXT:    addi r3, r3, .LCPI3_0@toc@l
-; CHECK-BE-P9-NEXT:    lxv v3, 0(r3)
-; CHECK-BE-P9-NEXT:    vperm v2, v4, v2, v3
-; CHECK-BE-P9-NEXT:    stxv v2, 0(r3)
+; CHECK-BE-P9-NEXT:    lxv vs2, 0(r3)
+; CHECK-BE-P9-NEXT:    xxperm vs0, vs1, vs2
+; CHECK-BE-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-P9-NEXT:    blr
 ;
 ; CHECK-AIX-64-P8-LABEL: test_v4i32_none:
 ; CHECK-AIX-64-P8:       # %bb.0: # %entry
 ; CHECK-AIX-64-P8-NEXT:    ld r4, L..C5(r2) # %const.0
 ; CHECK-AIX-64-P8-NEXT:    lxsiwzx v2, 0, r3
 ; CHECK-AIX-64-P8-NEXT:    xxlxor v4, v4, v4
 ; CHECK-AIX-64-P8-NEXT:    lxvw4x v3, 0, r4
 ; CHECK-AIX-64-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-AIX-64-P8-NEXT:    stxvw4x v2, 0, r3
 ; CHECK-AIX-64-P8-NEXT:    blr
 ;
 ; CHECK-AIX-64-P9-LABEL: test_v4i32_none:
 ; CHECK-AIX-64-P9:       # %bb.0: # %entry
-; CHECK-AIX-64-P9-NEXT:    lxsiwzx v2, 0, r3
+; CHECK-AIX-64-P9-NEXT:    lfiwzx f0, 0, r3
 ; CHECK-AIX-64-P9-NEXT:    ld r3, L..C4(r2) # %const.0
-; CHECK-AIX-64-P9-NEXT:    xxlxor v4, v4, v4
-; CHECK-AIX-64-P9-NEXT:    lxv v3, 0(r3)
-; CHECK-AIX-64-P9-NEXT:    vperm v2, v4, v2, v3
-; CHECK-AIX-64-P9-NEXT:    stxv v2, 0(r3)
+; CHECK-AIX-64-P9-NEXT:    xxlxor vs2, vs2, vs2
+; CHECK-AIX-64-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-AIX-64-P9-NEXT:    xxperm vs0, vs2, vs1
+; CHECK-AIX-64-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-AIX-64-P9-NEXT:    blr
 ;
 ; CHECK-AIX-32-P8-LABEL: test_v4i32_none:
 ; CHECK-AIX-32-P8:       # %bb.0: # %entry
 ; CHECK-AIX-32-P8-NEXT:    lwz r4, L..C4(r2) # %const.0
 ; CHECK-AIX-32-P8-NEXT:    lxsiwzx v2, 0, r3
 ; CHECK-AIX-32-P8-NEXT:    xxlxor v4, v4, v4
 ; CHECK-AIX-32-P8-NEXT:    lxvw4x v3, 0, r4
 ; CHECK-AIX-32-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-AIX-32-P8-NEXT:    stxvw4x v2, 0, r3
 ; CHECK-AIX-32-P8-NEXT:    blr
 ;
 ; CHECK-AIX-32-P9-LABEL: test_v4i32_none:
 ; CHECK-AIX-32-P9:       # %bb.0: # %entry
-; CHECK-AIX-32-P9-NEXT:    lxsiwzx v2, 0, r3
+; CHECK-AIX-32-P9-NEXT:    lfiwzx f0, 0, r3
 ; CHECK-AIX-32-P9-NEXT:    lwz r3, L..C3(r2) # %const.0
-; CHECK-AIX-32-P9-NEXT:    xxlxor v4, v4, v4
-; CHECK-AIX-32-P9-NEXT:    lxv v3, 0(r3)
-; CHECK-AIX-32-P9-NEXT:    vperm v2, v4, v2, v3
-; CHECK-AIX-32-P9-NEXT:    stxv v2, 0(r3)
+; CHECK-AIX-32-P9-NEXT:    xxlxor vs2, vs2, vs2
+; CHECK-AIX-32-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-AIX-32-P9-NEXT:    xxperm vs0, vs2, vs1
+; CHECK-AIX-32-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-AIX-32-P9-NEXT:    blr
 entry:
   %0 = load <2 x i16>, ptr %ptr1, align 1
   %1 = load <2 x i16>, ptr %ptr2, align 1
   %shuffle1 = shufflevector <2 x i16> %0, <2 x i16> %1, <4 x i32> <i32 1, i32 0, i32 1, i32 0>
   %2 = zext <4 x i16> %shuffle1 to <4 x i32>
   store <4 x i32> %2, ptr undef, align 16
   ret void
 }
 
 define void @test_none_v2i64(ptr nocapture readonly %ptr1, ptr nocapture readonly %ptr2) {
 ; CHECK-LE-P8-LABEL: test_none_v2i64:
 ; CHECK-LE-P8:       # %bb.0: # %entry
 ; CHECK-LE-P8-NEXT:    addis r5, r2, .LCPI4_0@toc@ha
-; CHECK-LE-P8-NEXT:    lxvd2x vs0, 0, r4
-; CHECK-LE-P8-NEXT:    lxsdx v2, 0, r3
+; CHECK-LE-P8-NEXT:    lxsdx v3, 0, r3
+; CHECK-LE-P8-NEXT:    lxvd2x v4, 0, r4
 ; CHECK-LE-P8-NEXT:    addis r3, r2, .LCPI4_1@toc@ha
 ; CHECK-LE-P8-NEXT:    addi r5, r5, .LCPI4_0@toc@l
 ; CHECK-LE-P8-NEXT:    addi r3, r3, .LCPI4_1@toc@l
-; CHECK-LE-P8-NEXT:    lxvd2x vs1, 0, r5
-; CHECK-LE-P8-NEXT:    xxswapd v3, vs0
+; CHECK-LE-P8-NEXT:    lxvd2x vs0, 0, r5
+; CHECK-LE-P8-NEXT:    xxswapd v2, vs0
 ; CHECK-LE-P8-NEXT:    lxvd2x vs0, 0, r3
-; CHECK-LE-P8-NEXT:    xxswapd v4, vs1
-; CHECK-LE-P8-NEXT:    vperm v2, v2, v3, v4
+; CHECK-LE-P8-NEXT:    vperm v2, v3, v4, v2
 ; CHECK-LE-P8-NEXT:    xxswapd v3, vs0
 ; CHECK-LE-P8-NEXT:    xxlxor v4, v4, v4
 ; CHECK-LE-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-LE-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-LE-P8-NEXT:    stxvd2x vs0, 0, r3
 ; CHECK-LE-P8-NEXT:    blr
 ;
 ; CHECK-LE-P9-LABEL: test_none_v2i64:
 ; CHECK-LE-P9:       # %bb.0: # %entry
-; CHECK-LE-P9-NEXT:    lxsd v2, 0(r3)
+; CHECK-LE-P9-NEXT:    lfd f0, 0(r3)
 ; CHECK-LE-P9-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
-; CHECK-LE-P9-NEXT:    lxv v3, 0(r4)
+; CHECK-LE-P9-NEXT:    lxv v2, 0(r4)
+; CHECK-LE-P9-NEXT:    xxlxor v4, v4, v4
 ; CHECK-LE-P9-NEXT:    addi r3, r3, .LCPI4_0@toc@l
-; CHECK-LE-P9-NEXT:    lxv v4, 0(r3)
+; CHECK-LE-P9-NEXT:    lxv vs1, 0(r3)
 ; CHECK-LE-P9-NEXT:    addis r3, r2, .LCPI4_1@toc@ha
 ; CHECK-LE-P9-NEXT:    addi r3, r3, .LCPI4_1@toc@l
-; CHECK-LE-P9-NEXT:    vperm v2, v2, v3, v4
 ; CHECK-LE-P9-NEXT:    lxv v3, 0(r3)
-; CHECK-LE-P9-NEXT:    xxlxor v4, v4, v4
+; CHECK-LE-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-LE-P9-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-LE-P9-NEXT:    stxv v2, 0(r3)
 ; CHECK-LE-P9-NEXT:    blr
 ;
 ; CHECK-BE-P8-LABEL: test_none_v2i64:
 ; CHECK-BE-P8:       # %bb.0: # %entry
 ; CHECK-BE-P8-NEXT:    addis r5, r2, .LCPI4_0@toc@ha
 ; CHECK-BE-P8-NEXT:    lxsdx v2, 0, r3
 ; CHECK-BE-P8-NEXT:    lxvw4x v3, 0, r4
 ; CHECK-BE-P8-NEXT:    addi r5, r5, .LCPI4_0@toc@l
 ; CHECK-BE-P8-NEXT:    lxvw4x v4, 0, r5
 ; CHECK-BE-P8-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-BE-P8-NEXT:    xxlxor v3, v3, v3
 ; CHECK-BE-P8-NEXT:    vmrghh v2, v3, v2
 ; CHECK-BE-P8-NEXT:    stxvw4x v2, 0, r3
 ; CHECK-BE-P8-NEXT:    blr
 ;
 ; CHECK-BE-P9-LABEL: test_none_v2i64:
 ; CHECK-BE-P9:       # %bb.0: # %entry
 ; CHECK-BE-P9-NEXT:    lxsd v2, 0(r3)
 ; CHECK-BE-P9-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
-; CHECK-BE-P9-NEXT:    lxv v3, 0(r4)
-; CHECK-BE-P9-NEXT:    addi r3, r3, .LCPI4_0@toc@l
-; CHECK-BE-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-BE-P9-NEXT:    vperm v2, v3, v2, v4
+; CHECK-BE-P9-NEXT:    lxv vs0, 0(r4)
 ; CHECK-BE-P9-NEXT:    xxlxor v3, v3, v3
+; CHECK-BE-P9-NEXT:    addi r3, r3, .LCPI4_0@toc@l
+; CHECK-BE-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-BE-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-BE-P9-NEXT:    vmrghh v2, v3, v2
 ; CHECK-BE-P9-NEXT:    stxv v2, 0(r3)
 ; CHECK-BE-P9-NEXT:    blr
 ;
 ; CHECK-AIX-64-P8-LABEL: test_none_v2i64:
 ; CHECK-AIX-64-P8:       # %bb.0: # %entry
 ; CHECK-AIX-64-P8-NEXT:    ld r5, L..C6(r2) # %const.0
 ; CHECK-AIX-64-P8-NEXT:    lxsdx v2, 0, r3
 ; CHECK-AIX-64-P8-NEXT:    lxvw4x v3, 0, r4
 ; CHECK-AIX-64-P8-NEXT:    lxvw4x v4, 0, r5
 ; CHECK-AIX-64-P8-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-AIX-64-P8-NEXT:    xxlxor v3, v3, v3
 ; CHECK-AIX-64-P8-NEXT:    vmrghh v2, v3, v2
 ; CHECK-AIX-64-P8-NEXT:    stxvw4x v2, 0, r3
 ; CHECK-AIX-64-P8-NEXT:    blr
 ;
 ; CHECK-AIX-64-P9-LABEL: test_none_v2i64:
 ; CHECK-AIX-64-P9:       # %bb.0: # %entry
 ; CHECK-AIX-64-P9-NEXT:    lxsd v2, 0(r3)
 ; CHECK-AIX-64-P9-NEXT:    ld r3, L..C5(r2) # %const.0
-; CHECK-AIX-64-P9-NEXT:    lxv v3, 0(r4)
-; CHECK-AIX-64-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-AIX-64-P9-NEXT:    vperm v2, v3, v2, v4
+; CHECK-AIX-64-P9-NEXT:    lxv vs1, 0(r4)
 ; CHECK-AIX-64-P9-NEXT:    xxlxor v3, v3, v3
+; CHECK-AIX-64-P9-NEXT:    lxv vs0, 0(r3)
+; CHECK-AIX-64-P9-NEXT:    xxperm v2, vs1, vs0
 ; CHECK-AIX-64-P9-NEXT:    vmrghh v2, v3, v2
 ; CHECK-AIX-64-P9-NEXT:    stxv v2, 0(r3)
 ; CHECK-AIX-64-P9-NEXT:    blr
 ;
 ; CHECK-AIX-32-P8-LABEL: test_none_v2i64:
 ; CHECK-AIX-32-P8:       # %bb.0: # %entry
 ; CHECK-AIX-32-P8-NEXT:    lwz r5, L..C5(r2) # %const.0
 ; CHECK-AIX-32-P8-NEXT:    lxsiwzx v2, 0, r3
 ; CHECK-AIX-32-P8-NEXT:    lxvw4x v3, 0, r4
 ; CHECK-AIX-32-P8-NEXT:    lxvw4x v4, 0, r5
 ; CHECK-AIX-32-P8-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-AIX-32-P8-NEXT:    xxlxor v3, v3, v3
 ; CHECK-AIX-32-P8-NEXT:    vmrghh v2, v3, v2
 ; CHECK-AIX-32-P8-NEXT:    stxvw4x v2, 0, r3
 ; CHECK-AIX-32-P8-NEXT:    blr
 ;
 ; CHECK-AIX-32-P9-LABEL: test_none_v2i64:
 ; CHECK-AIX-32-P9:       # %bb.0: # %entry
 ; CHECK-AIX-32-P9-NEXT:    lxsiwzx v2, 0, r3
 ; CHECK-AIX-32-P9-NEXT:    lwz r3, L..C4(r2) # %const.0
-; CHECK-AIX-32-P9-NEXT:    lxv v3, 0(r4)
-; CHECK-AIX-32-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-AIX-32-P9-NEXT:    vperm v2, v3, v2, v4
+; CHECK-AIX-32-P9-NEXT:    lxv vs0, 0(r4)
 ; CHECK-AIX-32-P9-NEXT:    xxlxor v3, v3, v3
+; CHECK-AIX-32-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-AIX-32-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-AIX-32-P9-NEXT:    vmrghh v2, v3, v2
 ; CHECK-AIX-32-P9-NEXT:    stxv v2, 0(r3)
 ; CHECK-AIX-32-P9-NEXT:    blr
 entry:
   %0 = load <4 x i16>, ptr %ptr1, align 1
   %1 = load <4 x i32>, ptr %ptr2, align 1
   %bc = trunc <4 x i32> %1 to <4 x i16>
   %shuffle1 = shufflevector <4 x i16> %0, <4 x i16> %bc, <4 x i32> <i32 4, i32 5, i32 1, i32 0>

 ; CHECK-LE-P8-NEXT:    xxswapd v3, vs0
 ; CHECK-LE-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-LE-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-LE-P8-NEXT:    stxvd2x vs0, 0, r3
 ; CHECK-LE-P8-NEXT:    blr
 ;
 ; CHECK-LE-P9-LABEL: test_v2i64_none:
 ; CHECK-LE-P9:       # %bb.0: # %entry
-; CHECK-LE-P9-NEXT:    lxsd v2, 0(r3)
+; CHECK-LE-P9-NEXT:    lfd f0, 0(r3)
 ; CHECK-LE-P9-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
-; CHECK-LE-P9-NEXT:    xxlxor v4, v4, v4
+; CHECK-LE-P9-NEXT:    xxlxor vs1, vs1, vs1
 ; CHECK-LE-P9-NEXT:    addi r3, r3, .LCPI5_0@toc@l
-; CHECK-LE-P9-NEXT:    lxv v3, 0(r3)
-; CHECK-LE-P9-NEXT:    vperm v2, v4, v2, v3
-; CHECK-LE-P9-NEXT:    stxv v2, 0(r3)
+; CHECK-LE-P9-NEXT:    lxv vs2, 0(r3)
+; CHECK-LE-P9-NEXT:    xxperm vs0, vs1, vs2
+; CHECK-LE-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-LE-P9-NEXT:    blr
 ;
 ; CHECK-BE-P8-LABEL: test_v2i64_none:
 ; CHECK-BE-P8:       # %bb.0: # %entry
 ; CHECK-BE-P8-NEXT:    addis r4, r2, .LCPI5_0@toc@ha
 ; CHECK-BE-P8-NEXT:    lxsdx v2, 0, r3
 ; CHECK-BE-P8-NEXT:    xxlxor v4, v4, v4
 ; CHECK-BE-P8-NEXT:    addi r4, r4, .LCPI5_0@toc@l
 ; CHECK-BE-P8-NEXT:    lxvw4x v3, 0, r4
 ; CHECK-BE-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-BE-P8-NEXT:    stxvw4x v2, 0, r3
 ; CHECK-BE-P8-NEXT:    blr
 ;
 ; CHECK-BE-P9-LABEL: test_v2i64_none:
 ; CHECK-BE-P9:       # %bb.0: # %entry
-; CHECK-BE-P9-NEXT:    lxsd v2, 0(r3)
+; CHECK-BE-P9-NEXT:    lfd f0, 0(r3)
 ; CHECK-BE-P9-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
-; CHECK-BE-P9-NEXT:    xxlxor v4, v4, v4
+; CHECK-BE-P9-NEXT:    xxlxor vs1, vs1, vs1
 ; CHECK-BE-P9-NEXT:    addi r3, r3, .LCPI5_0@toc@l
-; CHECK-BE-P9-NEXT:    lxv v3, 0(r3)
-; CHECK-BE-P9-NEXT:    vperm v2, v4, v2, v3
-; CHECK-BE-P9-NEXT:    stxv v2, 0(r3)
+; CHECK-BE-P9-NEXT:    lxv vs2, 0(r3)
+; CHECK-BE-P9-NEXT:    xxperm vs0, vs1, vs2
+; CHECK-BE-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-P9-NEXT:    blr
 ;
 ; CHECK-AIX-64-P8-LABEL: test_v2i64_none:
 ; CHECK-AIX-64-P8:       # %bb.0: # %entry
 ; CHECK-AIX-64-P8-NEXT:    ld r4, L..C7(r2) # %const.0
 ; CHECK-AIX-64-P8-NEXT:    lxsdx v2, 0, r3
 ; CHECK-AIX-64-P8-NEXT:    xxlxor v4, v4, v4
 ; CHECK-AIX-64-P8-NEXT:    lxvw4x v3, 0, r4
 ; CHECK-AIX-64-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-AIX-64-P8-NEXT:    stxvw4x v2, 0, r3
 ; CHECK-AIX-64-P8-NEXT:    blr
 ;
 ; CHECK-AIX-64-P9-LABEL: test_v2i64_none:
 ; CHECK-AIX-64-P9:       # %bb.0: # %entry
-; CHECK-AIX-64-P9-NEXT:    lxsd v2, 0(r3)
+; CHECK-AIX-64-P9-NEXT:    lfd f0, 0(r3)
 ; CHECK-AIX-64-P9-NEXT:    ld r3, L..C6(r2) # %const.0
-; CHECK-AIX-64-P9-NEXT:    xxlxor v4, v4, v4
-; CHECK-AIX-64-P9-NEXT:    lxv v3, 0(r3)
-; CHECK-AIX-64-P9-NEXT:    vperm v2, v4, v2, v3
-; CHECK-AIX-64-P9-NEXT:    stxv v2, 0(r3)
+; CHECK-AIX-64-P9-NEXT:    xxlxor vs2, vs2, vs2
+; CHECK-AIX-64-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-AIX-64-P9-NEXT:    xxperm vs0, vs2, vs1
+; CHECK-AIX-64-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-AIX-64-P9-NEXT:    blr
 ;
 ; CHECK-AIX-32-P8-LABEL: test_v2i64_none:
 ; CHECK-AIX-32-P8:       # %bb.0: # %entry
 ; CHECK-AIX-32-P8-NEXT:    lwz r4, 4(r3)
 ; CHECK-AIX-32-P8-NEXT:    xxlxor v4, v4, v4
 ; CHECK-AIX-32-P8-NEXT:    stw r4, -16(r1)
 ; CHECK-AIX-32-P8-NEXT:    addi r4, r1, -32
 ; CHECK-AIX-32-P8-NEXT:    lwz r3, 0(r3)
 ; CHECK-AIX-32-P8-NEXT:    stw r3, -32(r1)
 ; CHECK-AIX-32-P8-NEXT:    addi r3, r1, -16
 ; CHECK-AIX-32-P8-NEXT:    lxvw4x vs0, 0, r3
 ; CHECK-AIX-32-P8-NEXT:    lwz r3, L..C6(r2) # %const.0
 ; CHECK-AIX-32-P8-NEXT:    lxvw4x vs1, 0, r4
 ; CHECK-AIX-32-P8-NEXT:    lxvw4x v3, 0, r3
 ; CHECK-AIX-32-P8-NEXT:    xxmrghw v2, vs1, vs0
 ; CHECK-AIX-32-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-AIX-32-P8-NEXT:    stxvw4x v2, 0, r3
 ; CHECK-AIX-32-P8-NEXT:    blr
 ;
 ; CHECK-AIX-32-P9-LABEL: test_v2i64_none:
 ; CHECK-AIX-32-P9:       # %bb.0: # %entry
 ; CHECK-AIX-32-P9-NEXT:    lwz r4, 4(r3)
-; CHECK-AIX-32-P9-NEXT:    xxlxor v4, v4, v4
+; CHECK-AIX-32-P9-NEXT:    xxlxor vs2, vs2, vs2
 ; CHECK-AIX-32-P9-NEXT:    stw r4, -16(r1)
 ; CHECK-AIX-32-P9-NEXT:    lwz r3, 0(r3)
 ; CHECK-AIX-32-P9-NEXT:    lxv vs0, -16(r1)
 ; CHECK-AIX-32-P9-NEXT:    stw r3, -32(r1)
 ; CHECK-AIX-32-P9-NEXT:    lwz r3, L..C5(r2) # %const.0
 ; CHECK-AIX-32-P9-NEXT:    lxv vs1, -32(r1)
-; CHECK-AIX-32-P9-NEXT:    lxv v3, 0(r3)
-; CHECK-AIX-32-P9-NEXT:    xxmrghw v2, vs1, vs0
-; CHECK-AIX-32-P9-NEXT:    vperm v2, v4, v2, v3
-; CHECK-AIX-32-P9-NEXT:    stxv v2, 0(r3)
+; CHECK-AIX-32-P9-NEXT:    xxmrghw vs0, vs1, vs0
+; CHECK-AIX-32-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-AIX-32-P9-NEXT:    xxperm vs0, vs2, vs1
+; CHECK-AIX-32-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-AIX-32-P9-NEXT:    blr
 entry:
   %0 = load <4 x i16>, ptr %ptr1, align 1
   %shuffle1 = shufflevector <4 x i16> %0, <4 x i16> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
   %1 = zext <4 x i16> %shuffle1 to <4 x i32>
   store <4 x i32> %1, ptr undef, align 16
   ret void
 }

 ; CHECK-LE-P8-NEXT:    xxswapd v3, vs0
 ; CHECK-LE-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-LE-P8-NEXT:    blr
 ;
 ; CHECK-LE-P9-LABEL: test_v8i16_v8i16:
 ; CHECK-LE-P9:       # %bb.0: # %entry
 ; CHECK-LE-P9-NEXT:    lxsihzx v2, 0, r3
 ; CHECK-LE-P9-NEXT:    addis r3, r2, .LCPI6_0@toc@ha
-; CHECK-LE-P9-NEXT:    lxsihzx v3, 0, r4
+; CHECK-LE-P9-NEXT:    lxsihzx f0, 0, r4
 ; CHECK-LE-P9-NEXT:    addi r3, r3, .LCPI6_0@toc@l
-; CHECK-LE-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-LE-P9-NEXT:    vperm v2, v3, v2, v4
+; CHECK-LE-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-LE-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-LE-P9-NEXT:    blr
 ;
 ; CHECK-BE-P8-LABEL: test_v8i16_v8i16:
 ; CHECK-BE-P8:       # %bb.0: # %entry
 ; CHECK-BE-P8-NEXT:    addis r5, r2, .LCPI6_0@toc@ha
 ; CHECK-BE-P8-NEXT:    lhz r3, 0(r3)
 ; CHECK-BE-P8-NEXT:    lhz r4, 0(r4)
 ; CHECK-BE-P8-NEXT:    addi r5, r5, .LCPI6_0@toc@l
 ; CHECK-BE-P8-NEXT:    lxvw4x v2, 0, r5
 ; CHECK-BE-P8-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-P8-NEXT:    mtvsrwz v4, r4
 ; CHECK-BE-P8-NEXT:    vperm v2, v3, v4, v2
 ; CHECK-BE-P8-NEXT:    blr
 ;
 ; CHECK-BE-P9-LABEL: test_v8i16_v8i16:
 ; CHECK-BE-P9:       # %bb.0: # %entry
-; CHECK-BE-P9-NEXT:    lxsihzx v2, 0, r3
+; CHECK-BE-P9-NEXT:    lxsihzx f0, 0, r3
 ; CHECK-BE-P9-NEXT:    addis r3, r2, .LCPI6_0@toc@ha
-; CHECK-BE-P9-NEXT:    lxsihzx v3, 0, r4
+; CHECK-BE-P9-NEXT:    lxsihzx v2, 0, r4
 ; CHECK-BE-P9-NEXT:    addi r3, r3, .LCPI6_0@toc@l
-; CHECK-BE-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-BE-P9-NEXT:    vperm v2, v2, v3, v4
+; CHECK-BE-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-BE-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-BE-P9-NEXT:    blr
 ;
 ; CHECK-AIX-64-P8-LABEL: test_v8i16_v8i16:
 ; CHECK-AIX-64-P8:       # %bb.0: # %entry
 ; CHECK-AIX-64-P8-NEXT:    ld r5, L..C8(r2) # %const.0
 ; CHECK-AIX-64-P8-NEXT:    lhz r3, 0(r3)
 ; CHECK-AIX-64-P8-NEXT:    lhz r4, 0(r4)
 ; CHECK-AIX-64-P8-NEXT:    mtvsrwz v2, r3
 ; CHECK-AIX-64-P8-NEXT:    lxvw4x v3, 0, r5
 ; CHECK-AIX-64-P8-NEXT:    mtvsrwz v4, r4
 ; CHECK-AIX-64-P8-NEXT:    vperm v2, v2, v4, v3
 ; CHECK-AIX-64-P8-NEXT:    blr
 ;
 ; CHECK-AIX-64-P9-LABEL: test_v8i16_v8i16:
 ; CHECK-AIX-64-P9:       # %bb.0: # %entry
-; CHECK-AIX-64-P9-NEXT:    lxsihzx v2, 0, r3
+; CHECK-AIX-64-P9-NEXT:    lxsihzx f0, 0, r3
 ; CHECK-AIX-64-P9-NEXT:    ld r3, L..C7(r2) # %const.0
-; CHECK-AIX-64-P9-NEXT:    lxsihzx v3, 0, r4
-; CHECK-AIX-64-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-AIX-64-P9-NEXT:    vperm v2, v2, v3, v4
+; CHECK-AIX-64-P9-NEXT:    lxsihzx v2, 0, r4
+; CHECK-AIX-64-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-AIX-64-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-AIX-64-P9-NEXT:    blr
 ;
 ; CHECK-AIX-32-P8-LABEL: test_v8i16_v8i16:
 ; CHECK-AIX-32-P8:       # %bb.0: # %entry
 ; CHECK-AIX-32-P8-NEXT:    lwz r5, L..C7(r2) # %const.0
 ; CHECK-AIX-32-P8-NEXT:    lhz r3, 0(r3)
 ; CHECK-AIX-32-P8-NEXT:    lhz r4, 0(r4)
 ; CHECK-AIX-32-P8-NEXT:    mtvsrwz v2, r3
 ; CHECK-AIX-32-P8-NEXT:    lxvw4x v3, 0, r5
 ; CHECK-AIX-32-P8-NEXT:    mtvsrwz v4, r4
 ; CHECK-AIX-32-P8-NEXT:    vperm v2, v2, v4, v3
 ; CHECK-AIX-32-P8-NEXT:    blr
 ;
 ; CHECK-AIX-32-P9-LABEL: test_v8i16_v8i16:
 ; CHECK-AIX-32-P9:       # %bb.0: # %entry
-; CHECK-AIX-32-P9-NEXT:    lxsihzx v2, 0, r3
+; CHECK-AIX-32-P9-NEXT:    lxsihzx f0, 0, r3
 ; CHECK-AIX-32-P9-NEXT:    lwz r3, L..C6(r2) # %const.0
-; CHECK-AIX-32-P9-NEXT:    lxsihzx v3, 0, r4
-; CHECK-AIX-32-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-AIX-32-P9-NEXT:    vperm v2, v2, v3, v4
+; CHECK-AIX-32-P9-NEXT:    lxsihzx v2, 0, r4
+; CHECK-AIX-32-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-AIX-32-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-AIX-32-P9-NEXT:    blr
 entry:
   %load1 = load <2 x i8>, ptr %a
   %load2 = load <2 x i8>, ptr %b
   %shuffle1 = shufflevector <2 x i8> %load1, <2 x i8> %load2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
   %shuffle2 = shufflevector <8 x i8> %shuffle1, <8 x i8> %shuffle1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %shuffle2
 }

 ; CHECK-LE-P8-NEXT:    xxlxor v4, v4, v4
 ; CHECK-LE-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-LE-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-LE-P8-NEXT:    stxvd2x vs0, 0, r3
 ; CHECK-LE-P8-NEXT:    blr
 ;
 ; CHECK-LE-P9-LABEL: test_v4i32_v4i32:
 ; CHECK-LE-P9:       # %bb.0: # %entry
-; CHECK-LE-P9-NEXT:    lxsiwzx v2, 0, r3
+; CHECK-LE-P9-NEXT:    lfiwzx f0, 0, r3
 ; CHECK-LE-P9-NEXT:    addis r3, r2, .LCPI9_0@toc@ha
-; CHECK-LE-P9-NEXT:    lxsiwzx v3, 0, r4
+; CHECK-LE-P9-NEXT:    lxsiwzx v2, 0, r4
+; CHECK-LE-P9-NEXT:    xxlxor v4, v4, v4
 ; CHECK-LE-P9-NEXT:    addi r3, r3, .LCPI9_0@toc@l
-; CHECK-LE-P9-NEXT:    lxv v4, 0(r3)
+; CHECK-LE-P9-NEXT:    lxv vs1, 0(r3)
 ; CHECK-LE-P9-NEXT:    addis r3, r2, .LCPI9_1@toc@ha
 ; CHECK-LE-P9-NEXT:    addi r3, r3, .LCPI9_1@toc@l
-; CHECK-LE-P9-NEXT:    vperm v2, v2, v3, v4
 ; CHECK-LE-P9-NEXT:    lxv v3, 0(r3)
-; CHECK-LE-P9-NEXT:    xxlxor v4, v4, v4
+; CHECK-LE-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-LE-P9-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-LE-P9-NEXT:    stxv v2, 0(r3)
 ; CHECK-LE-P9-NEXT:    blr
 ;
 ; CHECK-BE-P8-LABEL: test_v4i32_v4i32:
 ; CHECK-BE-P8:       # %bb.0: # %entry
 ; CHECK-BE-P8-NEXT:    addis r5, r2, .LCPI9_0@toc@ha
 ; CHECK-BE-P8-NEXT:    lxsiwzx v2, 0, r3
 ; CHECK-BE-P8-NEXT:    lxsiwzx v3, 0, r4
 ; CHECK-BE-P8-NEXT:    addi r5, r5, .LCPI9_0@toc@l
 ; CHECK-BE-P8-NEXT:    lxvw4x v4, 0, r5
 ; CHECK-BE-P8-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-BE-P8-NEXT:    xxlxor v3, v3, v3
 ; CHECK-BE-P8-NEXT:    vmrghh v2, v3, v2
 ; CHECK-BE-P8-NEXT:    stxvw4x v2, 0, r3
 ; CHECK-BE-P8-NEXT:    blr
 ;
 ; CHECK-BE-P9-LABEL: test_v4i32_v4i32:
 ; CHECK-BE-P9:       # %bb.0: # %entry
 ; CHECK-BE-P9-NEXT:    lxsiwzx v2, 0, r3
 ; CHECK-BE-P9-NEXT:    addis r3, r2, .LCPI9_0@toc@ha
-; CHECK-BE-P9-NEXT:    lxsiwzx v3, 0, r4
-; CHECK-BE-P9-NEXT:    addi r3, r3, .LCPI9_0@toc@l
-; CHECK-BE-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-BE-P9-NEXT:    vperm v2, v3, v2, v4
+; CHECK-BE-P9-NEXT:    lfiwzx f0, 0, r4
 ; CHECK-BE-P9-NEXT:    xxlxor v3, v3, v3
+; CHECK-BE-P9-NEXT:    addi r3, r3, .LCPI9_0@toc@l
+; CHECK-BE-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-BE-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-BE-P9-NEXT:    vmrghh v2, v3, v2
 ; CHECK-BE-P9-NEXT:    stxv v2, 0(r3)
 ; CHECK-BE-P9-NEXT:    blr
 ;
 ; CHECK-AIX-64-P8-LABEL: test_v4i32_v4i32:
 ; CHECK-AIX-64-P8:       # %bb.0: # %entry
 ; CHECK-AIX-64-P8-NEXT:    ld r5, L..C9(r2) # %const.0
 ; CHECK-AIX-64-P8-NEXT:    lxsiwzx v2, 0, r3
 ; CHECK-AIX-64-P8-NEXT:    lxsiwzx v3, 0, r4
 ; CHECK-AIX-64-P8-NEXT:    lxvw4x v4, 0, r5
 ; CHECK-AIX-64-P8-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-AIX-64-P8-NEXT:    xxlxor v3, v3, v3
 ; CHECK-AIX-64-P8-NEXT:    vmrghh v2, v3, v2
 ; CHECK-AIX-64-P8-NEXT:    stxvw4x v2, 0, r3
 ; CHECK-AIX-64-P8-NEXT:    blr
 ;
 ; CHECK-AIX-64-P9-LABEL: test_v4i32_v4i32:
 ; CHECK-AIX-64-P9:       # %bb.0: # %entry
 ; CHECK-AIX-64-P9-NEXT:    lxsiwzx v2, 0, r3
 ; CHECK-AIX-64-P9-NEXT:    ld r3, L..C8(r2) # %const.0
-; CHECK-AIX-64-P9-NEXT:    lxsiwzx v3, 0, r4
-; CHECK-AIX-64-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-AIX-64-P9-NEXT:    vperm v2, v3, v2, v4
+; CHECK-AIX-64-P9-NEXT:    lfiwzx f0, 0, r4
 ; CHECK-AIX-64-P9-NEXT:    xxlxor v3, v3, v3
+; CHECK-AIX-64-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-AIX-64-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-AIX-64-P9-NEXT:    vmrghh v2, v3, v2
 ; CHECK-AIX-64-P9-NEXT:    stxv v2, 0(r3)
 ; CHECK-AIX-64-P9-NEXT:    blr
 ;
 ; CHECK-AIX-32-P8-LABEL: test_v4i32_v4i32:
 ; CHECK-AIX-32-P8:       # %bb.0: # %entry
 ; CHECK-AIX-32-P8-NEXT:    lwz r5, L..C8(r2) # %const.0
 ; CHECK-AIX-32-P8-NEXT:    lxsiwzx v2, 0, r3
 ; CHECK-AIX-32-P8-NEXT:    lxsiwzx v3, 0, r4
 ; CHECK-AIX-32-P8-NEXT:    lxvw4x v4, 0, r5
 ; CHECK-AIX-32-P8-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-AIX-32-P8-NEXT:    xxlxor v3, v3, v3
 ; CHECK-AIX-32-P8-NEXT:    vmrghh v2, v3, v2
 ; CHECK-AIX-32-P8-NEXT:    stxvw4x v2, 0, r3
 ; CHECK-AIX-32-P8-NEXT:    blr
 ;
 ; CHECK-AIX-32-P9-LABEL: test_v4i32_v4i32:
 ; CHECK-AIX-32-P9:       # %bb.0: # %entry
 ; CHECK-AIX-32-P9-NEXT:    lxsiwzx v2, 0, r3
 ; CHECK-AIX-32-P9-NEXT:    lwz r3, L..C7(r2) # %const.0
-; CHECK-AIX-32-P9-NEXT:    lxsiwzx v3, 0, r4
-; CHECK-AIX-32-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-AIX-32-P9-NEXT:    vperm v2, v3, v2, v4
+; CHECK-AIX-32-P9-NEXT:    lfiwzx f0, 0, r4
 ; CHECK-AIX-32-P9-NEXT:    xxlxor v3, v3, v3
+; CHECK-AIX-32-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-AIX-32-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-AIX-32-P9-NEXT:    vmrghh v2, v3, v2
 ; CHECK-AIX-32-P9-NEXT:    stxv v2, 0(r3)
 ; CHECK-AIX-32-P9-NEXT:    blr
 entry:
   %0 = load <2 x i16>, ptr %ptr1, align 1
   %1 = load <2 x i16>, ptr %ptr2, align 1
   %shuffle1 = shufflevector <2 x i16> %0, <2 x i16> %1, <4 x i32> <i32 2, i32 3, i32 1, i32 0>
   %2 = zext <4 x i16> %shuffle1 to <4 x i32>

 ; CHECK-AIX-32-P8-NEXT:    lxsiwzx v2, 0, r3
 ; CHECK-AIX-32-P8-NEXT:    lxsiwzx v3, 0, r4
 ; CHECK-AIX-32-P8-NEXT:    lxvw4x v4, 0, r5
 ; CHECK-AIX-32-P8-NEXT:    vperm v2, v2, v3, v4
 ; CHECK-AIX-32-P8-NEXT:    blr
 ;
 ; CHECK-AIX-32-P9-LABEL: test_v4i32_v2i64:
 ; CHECK-AIX-32-P9:       # %bb.0: # %entry
-; CHECK-AIX-32-P9-NEXT:    lxsiwzx v2, 0, r3
+; CHECK-AIX-32-P9-NEXT:    lfiwzx f0, 0, r3
 ; CHECK-AIX-32-P9-NEXT:    lwz r3, L..C8(r2) # %const.0
-; CHECK-AIX-32-P9-NEXT:    lxsiwzx v3, 0, r4
-; CHECK-AIX-32-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-AIX-32-P9-NEXT:    vperm v2, v2, v3, v4
+; CHECK-AIX-32-P9-NEXT:    lxsiwzx v2, 0, r4
+; CHECK-AIX-32-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-AIX-32-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-AIX-32-P9-NEXT:    blr
 entry:
   %0 = load <2 x i8>, ptr %a, align 4
   %bc1 = bitcast <2 x i8> %0 to i16
   %vecinit3 = insertelement <8 x i16> poison, i16 %bc1, i64 0
   %1 = load <2 x i8>, ptr %b, align 8
   %bc2 = bitcast <2 x i8> %1 to i16
   %vecinit6 = insertelement <8 x i16> undef, i16 %bc2, i64 0

 ; CHECK-LE-P8-NEXT:    xxlxor v4, v4, v4
 ; CHECK-LE-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-LE-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-LE-P8-NEXT:    stxvd2x vs0, 0, r3
 ; CHECK-LE-P8-NEXT:    blr
 ;
 ; CHECK-LE-P9-LABEL: test_v2i64_v2i64:
 ; CHECK-LE-P9:       # %bb.0: # %entry
-; CHECK-LE-P9-NEXT:    lxsd v2, 0(r3)
+; CHECK-LE-P9-NEXT:    lfd f0, 0(r3)
 ; CHECK-LE-P9-NEXT:    addis r3, r2, .LCPI12_0@toc@ha
-; CHECK-LE-P9-NEXT:    lxsd v3, 0(r4)
+; CHECK-LE-P9-NEXT:    lxsd v2, 0(r4)
+; CHECK-LE-P9-NEXT:    xxlxor v4, v4, v4
 ; CHECK-LE-P9-NEXT:    addi r3, r3, .LCPI12_0@toc@l
-; CHECK-LE-P9-NEXT:    lxv v4, 0(r3)
+; CHECK-LE-P9-NEXT:    lxv vs1, 0(r3)
 ; CHECK-LE-P9-NEXT:    addis r3, r2, .LCPI12_1@toc@ha
 ; CHECK-LE-P9-NEXT:    addi r3, r3, .LCPI12_1@toc@l
-; CHECK-LE-P9-NEXT:    vperm v2, v2, v3, v4
 ; CHECK-LE-P9-NEXT:    lxv v3, 0(r3)
-; CHECK-LE-P9-NEXT:    xxlxor v4, v4, v4
+; CHECK-LE-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-LE-P9-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-LE-P9-NEXT:    stxv v2, 0(r3)
 ; CHECK-LE-P9-NEXT:    blr
 ;
 ; CHECK-BE-P8-LABEL: test_v2i64_v2i64:
 ; CHECK-BE-P8:       # %bb.0: # %entry
 ; CHECK-BE-P8-NEXT:    addis r5, r2, .LCPI12_0@toc@ha
 ; CHECK-BE-P8-NEXT:    lxsdx v2, 0, r3
 ; CHECK-BE-P8-NEXT:    lxsdx v3, 0, r4
 ; CHECK-BE-P8-NEXT:    addi r5, r5, .LCPI12_0@toc@l
 ; CHECK-BE-P8-NEXT:    lxvw4x v4, 0, r5
 ; CHECK-BE-P8-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-BE-P8-NEXT:    xxlxor v3, v3, v3
 ; CHECK-BE-P8-NEXT:    vmrghh v2, v3, v2
 ; CHECK-BE-P8-NEXT:    stxvw4x v2, 0, r3
 ; CHECK-BE-P8-NEXT:    blr
 ;
 ; CHECK-BE-P9-LABEL: test_v2i64_v2i64:
 ; CHECK-BE-P9:       # %bb.0: # %entry
 ; CHECK-BE-P9-NEXT:    lxsd v2, 0(r3)
 ; CHECK-BE-P9-NEXT:    addis r3, r2, .LCPI12_0@toc@ha
-; CHECK-BE-P9-NEXT:    lxsd v3, 0(r4)
-; CHECK-BE-P9-NEXT:    addi r3, r3, .LCPI12_0@toc@l
-; CHECK-BE-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-BE-P9-NEXT:    vperm v2, v3, v2, v4
+; CHECK-BE-P9-NEXT:    lfd f0, 0(r4)
 ; CHECK-BE-P9-NEXT:    xxlxor v3, v3, v3
+; CHECK-BE-P9-NEXT:    addi r3, r3, .LCPI12_0@toc@l
+; CHECK-BE-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-BE-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-BE-P9-NEXT:    vmrghh v2, v3, v2
 ; CHECK-BE-P9-NEXT:    stxv v2, 0(r3)
 ; CHECK-BE-P9-NEXT:    blr
 ;
 ; CHECK-AIX-64-P8-LABEL: test_v2i64_v2i64:
 ; CHECK-AIX-64-P8:       # %bb.0: # %entry
 ; CHECK-AIX-64-P8-NEXT:    ld r5, L..C10(r2) # %const.0
 ; CHECK-AIX-64-P8-NEXT:    lxsdx v2, 0, r3
 ; CHECK-AIX-64-P8-NEXT:    lxsdx v3, 0, r4
 ; CHECK-AIX-64-P8-NEXT:    lxvw4x v4, 0, r5
 ; CHECK-AIX-64-P8-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-AIX-64-P8-NEXT:    xxlxor v3, v3, v3
 ; CHECK-AIX-64-P8-NEXT:    vmrghh v2, v3, v2
 ; CHECK-AIX-64-P8-NEXT:    stxvw4x v2, 0, r3
 ; CHECK-AIX-64-P8-NEXT:    blr
 ;
 ; CHECK-AIX-64-P9-LABEL: test_v2i64_v2i64:
 ; CHECK-AIX-64-P9:       # %bb.0: # %entry
 ; CHECK-AIX-64-P9-NEXT:    lxsd v2, 0(r3)
 ; CHECK-AIX-64-P9-NEXT:    ld r3, L..C9(r2) # %const.0
-; CHECK-AIX-64-P9-NEXT:    lxsd v3, 0(r4)
-; CHECK-AIX-64-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-AIX-64-P9-NEXT:    vperm v2, v3, v2, v4
+; CHECK-AIX-64-P9-NEXT:    lfd f0, 0(r4)
 ; CHECK-AIX-64-P9-NEXT:    xxlxor v3, v3, v3
+; CHECK-AIX-64-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-AIX-64-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-AIX-64-P9-NEXT:    vmrghh v2, v3, v2
 ; CHECK-AIX-64-P9-NEXT:    stxv v2, 0(r3)
 ; CHECK-AIX-64-P9-NEXT:    blr
 ;
 ; CHECK-AIX-32-P8-LABEL: test_v2i64_v2i64:
 ; CHECK-AIX-32-P8:       # %bb.0: # %entry
 ; CHECK-AIX-32-P8-NEXT:    lwz r5, L..C10(r2) # %const.0
 ; CHECK-AIX-32-P8-NEXT:    lxsiwzx v2, 0, r3
 ; CHECK-AIX-32-P8-NEXT:    lxsiwzx v3, 0, r4
 ; CHECK-AIX-32-P8-NEXT:    lxvw4x v4, 0, r5
 ; CHECK-AIX-32-P8-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-AIX-32-P8-NEXT:    xxlxor v3, v3, v3
 ; CHECK-AIX-32-P8-NEXT:    vmrghh v2, v3, v2
 ; CHECK-AIX-32-P8-NEXT:    stxvw4x v2, 0, r3
 ; CHECK-AIX-32-P8-NEXT:    blr
 ;
 ; CHECK-AIX-32-P9-LABEL: test_v2i64_v2i64:
 ; CHECK-AIX-32-P9:       # %bb.0: # %entry
 ; CHECK-AIX-32-P9-NEXT:    lxsiwzx v2, 0, r3
 ; CHECK-AIX-32-P9-NEXT:    lwz r3, L..C9(r2) # %const.0
-; CHECK-AIX-32-P9-NEXT:    lxsiwzx v3, 0, r4
-; CHECK-AIX-32-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-AIX-32-P9-NEXT:    vperm v2, v3, v2, v4
+; CHECK-AIX-32-P9-NEXT:    lfiwzx f0, 0, r4
 ; CHECK-AIX-32-P9-NEXT:    xxlxor v3, v3, v3
+; CHECK-AIX-32-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-AIX-32-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-AIX-32-P9-NEXT:    vmrghh v2, v3, v2
 ; CHECK-AIX-32-P9-NEXT:    stxv v2, 0(r3)
 ; CHECK-AIX-32-P9-NEXT:    blr
 entry:
   %0 = load <4 x i16>, ptr %ptr1, align 1
   %1 = load <4 x i16>, ptr %ptr2, align 1
   %shuffle1 = shufflevector <4 x i16> %0, <4 x i16> %1, <4 x i32> <i32 4, i32 5, i32 1, i32 0>
   %2 = zext <4 x i16> %shuffle1 to <4 x i32>

 ; CHECK-AIX-32-P8-NEXT:    lxvw4x v4, 0, r5
 ; CHECK-AIX-32-P8-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-AIX-32-P8-NEXT:    blr
 ;
 ; CHECK-AIX-32-P9-LABEL: test_v2i64_v4i32:
 ; CHECK-AIX-32-P9:       # %bb.0: # %entry
 ; CHECK-AIX-32-P9-NEXT:    lxsiwzx v2, 0, r3
 ; CHECK-AIX-32-P9-NEXT:    lwz r3, L..C10(r2) # %const.0
-; CHECK-AIX-32-P9-NEXT:    lxsiwzx v3, 0, r4
-; CHECK-AIX-32-P9-NEXT:    lxv v4, 0(r3)
-; CHECK-AIX-32-P9-NEXT:    vperm v2, v3, v2, v4
+; CHECK-AIX-32-P9-NEXT:    lfiwzx f0, 0, r4
+; CHECK-AIX-32-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-AIX-32-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-AIX-32-P9-NEXT:    blr
 entry:
   %0 = load <2 x i8>, ptr %a, align 4
   %bc1 = bitcast <2 x i8> %0 to i16
   %vecinit3 = insertelement <8 x i16> poison, i16 %bc1, i64 0
   %1 = load <2 x i8>, ptr %b, align 8
   %bc2 = bitcast <2 x i8> %1 to i16
   %vecinit6 = insertelement <8 x i16> undef, i16 %bc2, i64 0

llvm/test/CodeGen/PowerPC/vec-itofp.ll

 ; CHECK-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-P8-NEXT:    xvcvuxddp vs0, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, vs0
 ; CHECK-P8-NEXT:    stxvd2x vs0, 0, r3
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    lxv v2, 0(r4)
+; CHECK-P9-NEXT:    lxv vs1, 0(r4)
 ; CHECK-P9-NEXT:    addis r4, r2, .LCPI2_0@toc@ha
-; CHECK-P9-NEXT:    xxlxor v4, v4, v4
+; CHECK-P9-NEXT:    xxlxor vs0, vs0, vs0
 ; CHECK-P9-NEXT:    addi r4, r4, .LCPI2_0@toc@l
-; CHECK-P9-NEXT:    lxv v3, 0(r4)
-; CHECK-P9-NEXT:    vperm v2, v4, v2, v3
-; CHECK-P9-NEXT:    xvcvuxddp vs0, v2
+; CHECK-P9-NEXT:    lxv vs2, 0(r4)
+; CHECK-P9-NEXT:    xxperm vs1, vs0, vs2
+; CHECK-P9-NEXT:    xvcvuxddp vs0, vs1
 ; CHECK-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv v2, 0(r4)
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI2_0@toc@ha
 ; CHECK-BE-NEXT:    xxlxor v4, v4, v4

 ; CHECK-P8-NEXT:    stxvd2x vs0, 0, r3
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: stest2:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lxv v2, 0(r4)
 ; CHECK-P9-NEXT:    addis r4, r2, .LCPI5_0@toc@ha
 ; CHECK-P9-NEXT:    addi r4, r4, .LCPI5_0@toc@l
-; CHECK-P9-NEXT:    lxv v3, 0(r4)
-; CHECK-P9-NEXT:    vperm v2, v2, v2, v3
+; CHECK-P9-NEXT:    lxv vs0, 0(r4)
+; CHECK-P9-NEXT:    xxperm v2, v2, vs0
 ; CHECK-P9-NEXT:    vextsh2d v2, v2
 ; CHECK-P9-NEXT:    xvcvsxddp vs0, v2
 ; CHECK-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: stest2:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv v2, 0(r4)
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI5_0@toc@ha
 ; CHECK-BE-NEXT:    addi r4, r4, .LCPI5_0@toc@l
-; CHECK-BE-NEXT:    lxv v3, 0(r4)
-; CHECK-BE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-BE-NEXT:    lxv vs0, 0(r4)
+; CHECK-BE-NEXT:    xxperm v2, v2, vs0
 ; CHECK-BE-NEXT:    vextsh2d v2, v2
 ; CHECK-BE-NEXT:    xvcvsxddp vs0, v2
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = load <2 x i16>, <2 x i16>* %SrcPtr, align 16
   %1 = sitofp <2 x i16> %0 to <2 x double>
   store <2 x double> %1, <2 x double>* %Sink, align 16
   ret void
 }

llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i16_elts.ll

 ; CHECK-P9-NEXT:    vmrghh v2, v3, v2
 ; CHECK-P9-NEXT:    vextuwrx r3, r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtfprd f0, r3
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
-; CHECK-BE-NEXT:    xscvspdpn f1, vs0
+; CHECK-BE-NEXT:    xscvspdpn f2, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI0_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r3)
+; CHECK-BE-NEXT:    lxv vs1, 0(r3)
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-NEXT:    mffprwz r3, f2
+; CHECK-BE-NEXT:    mtfprwz f2, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    li r3, 0
-; CHECK-BE-NEXT:    vperm v2, v3, v4, v2
+; CHECK-BE-NEXT:    xxperm v2, vs2, vs1
 ; CHECK-BE-NEXT:    vextuwlx r3, r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i64 %a.coerce to <2 x float>
   %1 = fptoui <2 x float> %0 to <2 x i16>
   %2 = bitcast <2 x i16> %1 to i32
   ret i32 %2
 }

 ; CHECK-P9-NEXT:    mtvsrd v2, r3
 ; CHECK-P9-NEXT:    vmrghh v2, v4, v2
 ; CHECK-P9-NEXT:    xxmrglw vs0, v2, v3
 ; CHECK-P9-NEXT:    mfvsrld r3, vs0
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 3
+; CHECK-BE-NEXT:    xxsldwi vs1, v2, v2, 3
+; CHECK-BE-NEXT:    xxswapd vs2, v2
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI1_0@toc@l
-; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    xxswapd vs0, v2
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
-; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    xscvspdpn f0, v2
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vperm v4, v5, v4, v3
-; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
-; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    mtvsrwz v2, r3
-; CHECK-BE-NEXT:    vperm v2, v5, v2, v3
-; CHECK-BE-NEXT:    xxmrghw vs0, v2, v4
+; CHECK-BE-NEXT:    xxsldwi vs3, v2, v2, 1
+; CHECK-BE-NEXT:    xscvspdpn f1, vs1
+; CHECK-BE-NEXT:    xscvspdpn f2, vs2
+; CHECK-BE-NEXT:    xscvspdpn f3, vs3
+; CHECK-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    xscvdpsxws f3, f3
+; CHECK-BE-NEXT:    mffprwz r3, f1
+; CHECK-BE-NEXT:    mtfprwz f1, r3
+; CHECK-BE-NEXT:    mffprwz r3, f2
+; CHECK-BE-NEXT:    mtfprwz f2, r3
+; CHECK-BE-NEXT:    xxperm vs1, vs2, vs0
+; CHECK-BE-NEXT:    xscvspdpn f2, v2
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    mffprwz r3, f2
+; CHECK-BE-NEXT:    mtfprwz f2, r3
+; CHECK-BE-NEXT:    mffprwz r3, f3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
+; CHECK-BE-NEXT:    xxperm vs3, vs2, vs0
+; CHECK-BE-NEXT:    xxmrghw vs0, vs3, vs1
 ; CHECK-BE-NEXT:    mffprd r3, f0
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = fptoui <4 x float> %a to <4 x i16>
   %1 = bitcast <4 x i16> %0 to i64
   ret i64 %1
 }
 

 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test8elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI2_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r3)
-; CHECK-BE-NEXT:    xxsldwi vs2, vs1, vs1, 3
-; CHECK-BE-NEXT:    xscvspdpn f2, vs2
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    xxswapd vs2, vs1
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
-; CHECK-BE-NEXT:    xscvspdpn f2, vs2
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    xscvspdpn f2, vs1
+; CHECK-BE-NEXT:    lxv vs2, 0(r3)
+; CHECK-BE-NEXT:    xxsldwi vs3, vs1, vs1, 3
+; CHECK-BE-NEXT:    xxswapd vs4, vs1
+; CHECK-BE-NEXT:    xscvspdpn f3, vs3
+; CHECK-BE-NEXT:    xscvspdpn f4, vs4
+; CHECK-BE-NEXT:    xscvdpsxws f3, f3
+; CHECK-BE-NEXT:    xscvdpsxws f4, f4
+; CHECK-BE-NEXT:    mffprwz r3, f3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
+; CHECK-BE-NEXT:    mffprwz r3, f4
+; CHECK-BE-NEXT:    mtfprwz f4, r3
+; CHECK-BE-NEXT:    xxperm vs3, vs4, vs2
+; CHECK-BE-NEXT:    xscvspdpn f4, vs1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    vperm v3, v4, v3, v2
+; CHECK-BE-NEXT:    xscvdpsxws f4, f4
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    xxsldwi vs2, vs0, vs0, 3
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
-; CHECK-BE-NEXT:    xscvspdpn f2, vs2
+; CHECK-BE-NEXT:    mffprwz r3, f4
+; CHECK-BE-NEXT:    mtfprwz f4, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
-; CHECK-BE-NEXT:    xxmrghw vs1, v4, v3
-; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    xxswapd vs2, vs0
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
-; CHECK-BE-NEXT:    xscvspdpn f2, vs2
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    xscvspdpn f2, vs0
+; CHECK-BE-NEXT:    mtfprwz f1, r3
+; CHECK-BE-NEXT:    xxperm vs1, vs4, vs2
+; CHECK-BE-NEXT:    xxswapd vs4, vs0
+; CHECK-BE-NEXT:    xxmrghw vs1, vs1, vs3
+; CHECK-BE-NEXT:    xxsldwi vs3, vs0, vs0, 3
+; CHECK-BE-NEXT:    xscvspdpn f4, vs4
+; CHECK-BE-NEXT:    xscvspdpn f3, vs3
+; CHECK-BE-NEXT:    xscvdpsxws f4, f4
+; CHECK-BE-NEXT:    xscvdpsxws f3, f3
+; CHECK-BE-NEXT:    mffprwz r3, f3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
+; CHECK-BE-NEXT:    mffprwz r3, f4
+; CHECK-BE-NEXT:    mtfprwz f4, r3
+; CHECK-BE-NEXT:    xxperm vs3, vs4, vs2
+; CHECK-BE-NEXT:    xscvspdpn f4, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    vperm v3, v4, v3, v2
+; CHECK-BE-NEXT:    xscvdpsxws f4, f4
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mffprwz r3, f4
+; CHECK-BE-NEXT:    mtfprwz f4, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
-; CHECK-BE-NEXT:    vperm v2, v4, v5, v2
-; CHECK-BE-NEXT:    xxmrghw vs0, v2, v3
+; CHECK-BE-NEXT:    mtfprwz f0, r3
+; CHECK-BE-NEXT:    xxperm vs0, vs4, vs2
+; CHECK-BE-NEXT:    xxmrghw vs0, vs0, vs3
 ; CHECK-BE-NEXT:    xxmrghd v2, vs0, vs1
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <8 x float>, <8 x float>* %0, align 32
   %1 = fptoui <8 x float> %a to <8 x i16>
   ret <8 x i16> %1
 }
 

 ; CHECK-P9-NEXT:    vmrghh v3, v3, v4
 ; CHECK-P9-NEXT:    xxmrglw vs1, v3, v2
 ; CHECK-P9-NEXT:    xxmrgld vs0, vs1, vs0
 ; CHECK-P9-NEXT:    stxv vs0, 16(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test16elt:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    lxv vs1, 16(r4)
-; CHECK-BE-NEXT:    addis r5, r2, .LCPI3_0@toc@ha
-; CHECK-BE-NEXT:    lxv vs0, 0(r4)
-; CHECK-BE-NEXT:    addi r5, r5, .LCPI3_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r5)
-; CHECK-BE-NEXT:    xxsldwi vs2, vs1, vs1, 3
-; CHECK-BE-NEXT:    xxswapd vs3, vs1
-; CHECK-BE-NEXT:    xscvspdpn f4, vs1
-; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
-; CHECK-BE-NEXT:    xxsldwi vs5, vs0, vs0, 3
-; CHECK-BE-NEXT:    xscvspdpn f2, vs2
+; CHECK-BE-NEXT:    lxv vs3, 16(r4)
+; CHECK-BE-NEXT:    lxv vs0, 32(r4)
+; CHECK-BE-NEXT:    lxv vs2, 48(r4)
+; CHECK-BE-NEXT:    lxv vs5, 0(r4)
+; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_0@toc@ha
+; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_0@toc@l
+; CHECK-BE-NEXT:    lxv vs1, 0(r4)
+; CHECK-BE-NEXT:    xxsldwi vs4, vs3, vs3, 3
+; CHECK-BE-NEXT:    xxswapd vs6, vs3
+; CHECK-BE-NEXT:    xscvspdpn f7, vs3
+; CHECK-BE-NEXT:    xxsldwi vs3, vs3, vs3, 1
+; CHECK-BE-NEXT:    xxsldwi vs8, vs5, vs5, 3
+; CHECK-BE-NEXT:    xscvspdpn f4, vs4
+; CHECK-BE-NEXT:    xscvspdpn f6, vs6
 ; CHECK-BE-NEXT:    xscvspdpn f3, vs3
-; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    xscvdpsxws f7, f7
+; CHECK-BE-NEXT:    xscvspdpn f8, vs8
+; CHECK-BE-NEXT:    xscvdpsxws f4, f4
+; CHECK-BE-NEXT:    xscvdpsxws f6, f6
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mffprwz r5, f2
-; CHECK-BE-NEXT:    xxswapd vs2, vs0
-; CHECK-BE-NEXT:    mtvsrwz v3, r5
-; CHECK-BE-NEXT:    mffprwz r5, f3
-; CHECK-BE-NEXT:    xscvdpsxws f3, f4
+; CHECK-BE-NEXT:    xscvdpsxws f8, f8
+; CHECK-BE-NEXT:    mffprwz r4, f4
+; CHECK-BE-NEXT:    mtfprwz f4, r4
+; CHECK-BE-NEXT:    mffprwz r4, f6
+; CHECK-BE-NEXT:    mtfprwz f6, r4
+; CHECK-BE-NEXT:    mffprwz r4, f7
+; CHECK-BE-NEXT:    xxperm vs4, vs6, vs1
+; CHECK-BE-NEXT:    xxswapd vs6, vs5
+; CHECK-BE-NEXT:    mtfprwz f7, r4
+; CHECK-BE-NEXT:    mffprwz r4, f3
+; CHECK-BE-NEXT:    mtfprwz f3, r4
+; CHECK-BE-NEXT:    mffprwz r4, f8
+; CHECK-BE-NEXT:    xscvspdpn f6, vs6
+; CHECK-BE-NEXT:    xxperm vs3, vs7, vs1
+; CHECK-BE-NEXT:    xscvspdpn f7, vs5
+; CHECK-BE-NEXT:    xxsldwi vs5, vs5, vs5, 1
+; CHECK-BE-NEXT:    mtfprwz f8, r4
+; CHECK-BE-NEXT:    xscvdpsxws f6, f6
+; CHECK-BE-NEXT:    xscvspdpn f5, vs5
+; CHECK-BE-NEXT:    xscvdpsxws f7, f7
+; CHECK-BE-NEXT:    xxmrghw vs3, vs3, vs4
+; CHECK-BE-NEXT:    xscvdpsxws f5, f5
+; CHECK-BE-NEXT:    mffprwz r4, f6
+; CHECK-BE-NEXT:    mtfprwz f6, r4
+; CHECK-BE-NEXT:    mffprwz r4, f7
+; CHECK-BE-NEXT:    mtfprwz f7, r4
+; CHECK-BE-NEXT:    mffprwz r4, f5
+; CHECK-BE-NEXT:    xxperm vs8, vs6, vs1
+; CHECK-BE-NEXT:    xxsldwi vs6, vs2, vs2, 3
+; CHECK-BE-NEXT:    mtfprwz f5, r4
+; CHECK-BE-NEXT:    xscvspdpn f6, vs6
+; CHECK-BE-NEXT:    xxperm vs5, vs7, vs1
+; CHECK-BE-NEXT:    xxswapd vs7, vs2
+; CHECK-BE-NEXT:    xscvdpsxws f6, f6
+; CHECK-BE-NEXT:    xscvspdpn f7, vs7
+; CHECK-BE-NEXT:    xxmrghw vs4, vs5, vs8
+; CHECK-BE-NEXT:    xscvspdpn f5, vs2
+; CHECK-BE-NEXT:    xxsldwi vs2, vs2, vs2, 1
+; CHECK-BE-NEXT:    xscvdpsxws f7, f7
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs2
-; CHECK-BE-NEXT:    mtvsrwz v4, r5
-; CHECK-BE-NEXT:    vperm v3, v4, v3, v2
+; CHECK-BE-NEXT:    xscvdpsxws f5, f5
+; CHECK-BE-NEXT:    xxmrghd vs3, vs4, vs3
+; CHECK-BE-NEXT:    xxsldwi vs4, vs0, vs0, 3
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mffprwz r5, f3
-; CHECK-BE-NEXT:    xscvspdpn f3, vs5
-; CHECK-BE-NEXT:    mtvsrwz v4, r5
-; CHECK-BE-NEXT:    mffprwz r5, f1
-; CHECK-BE-NEXT:    xscvspdpn f1, vs0
-; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
-; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    mtvsrwz v5, r5
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r5, f1
-; CHECK-BE-NEXT:    mtvsrwz v5, r5
-; CHECK-BE-NEXT:    mffprwz r5, f3
-; CHECK-BE-NEXT:    mtvsrwz v0, r5
-; CHECK-BE-NEXT:    mffprwz r5, f2
-; CHECK-BE-NEXT:    xxmrghw vs2, v4, v3
-; CHECK-BE-NEXT:    mtvsrwz v1, r5
-; CHECK-BE-NEXT:    mffprwz r5, f0
-; CHECK-BE-NEXT:    lxv vs0, 48(r4)
-; CHECK-BE-NEXT:    vperm v0, v1, v0, v2
-; CHECK-BE-NEXT:    mtvsrwz v1, r5
-; CHECK-BE-NEXT:    vperm v5, v5, v1, v2
-; CHECK-BE-NEXT:    xxsldwi vs1, vs0, vs0, 3
-; CHECK-BE-NEXT:    xxswapd vs3, vs0
-; CHECK-BE-NEXT:    xscvspdpn f4, vs0
+; CHECK-BE-NEXT:    mffprwz r4, f6
+; CHECK-BE-NEXT:    xscvspdpn f4, vs4
+; CHECK-BE-NEXT:    mtfprwz f6, r4
+; CHECK-BE-NEXT:    xscvdpsxws f4, f4
+; CHECK-BE-NEXT:    mffprwz r4, f7
+; CHECK-BE-NEXT:    mtfprwz f7, r4
+; CHECK-BE-NEXT:    mffprwz r4, f5
+; CHECK-BE-NEXT:    mtfprwz f5, r4
+; CHECK-BE-NEXT:    mffprwz r4, f2
+; CHECK-BE-NEXT:    xxperm vs6, vs7, vs1
+; CHECK-BE-NEXT:    mtfprwz f2, r4
+; CHECK-BE-NEXT:    mffprwz r4, f4
+; CHECK-BE-NEXT:    xxperm vs2, vs5, vs1
+; CHECK-BE-NEXT:    xxswapd vs5, vs0
+; CHECK-BE-NEXT:    mtfprwz f4, r4
+; CHECK-BE-NEXT:    xscvspdpn f5, vs5
+; CHECK-BE-NEXT:    xxmrghw vs2, vs2, vs6
+; CHECK-BE-NEXT:    xscvdpsxws f5, f5
+; CHECK-BE-NEXT:    mffprwz r4, f5
+; CHECK-BE-NEXT:    mtfprwz f5, r4
+; CHECK-BE-NEXT:    xxperm vs4, vs5, vs1
+; CHECK-BE-NEXT:    xscvspdpn f5, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
-; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    xscvspdpn f3, vs3
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    xscvdpsxws f4, f4
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    xscvdpsxws f3, f3
+; CHECK-BE-NEXT:    xscvdpsxws f5, f5
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r5, f1
-; CHECK-BE-NEXT:    lxv vs1, 32(r4)
-; CHECK-BE-NEXT:    mffprwz r4, f4
-; CHECK-BE-NEXT:    mtvsrwz v3, r5
-; CHECK-BE-NEXT:    mffprwz r5, f3
-; CHECK-BE-NEXT:    xxmrghw vs3, v5, v0
-; CHECK-BE-NEXT:    mtvsrwz v4, r5
-; CHECK-BE-NEXT:    xxmrghd vs2, vs3, vs2
-; CHECK-BE-NEXT:    xxsldwi vs3, vs1, vs1, 3
-; CHECK-BE-NEXT:    vperm v3, v4, v3, v2
-; CHECK-BE-NEXT:    mtvsrwz v4, r4
+; CHECK-BE-NEXT:    mffprwz r4, f5
+; CHECK-BE-NEXT:    mtfprwz f5, r4
 ; CHECK-BE-NEXT:    mffprwz r4, f0
-; CHECK-BE-NEXT:    xscvspdpn f3, vs3
-; CHECK-BE-NEXT:    mtvsrwz v5, r4
-; CHECK-BE-NEXT:    stxv vs2, 0(r3)
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
-; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    xxmrghw vs0, v4, v3
-; CHECK-BE-NEXT:    mffprwz r4, f3
-; CHECK-BE-NEXT:    xxswapd vs3, vs1
-; CHECK-BE-NEXT:    mtvsrwz v3, r4
-; CHECK-BE-NEXT:    xscvspdpn f3, vs3
-; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    mffprwz r4, f3
-; CHECK-BE-NEXT:    xscvspdpn f3, vs1
-; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
-; CHECK-BE-NEXT:    mtvsrwz v4, r4
-; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    vperm v3, v4, v3, v2
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mffprwz r4, f3
-; CHECK-BE-NEXT:    mtvsrwz v4, r4
-; CHECK-BE-NEXT:    mffprwz r4, f1
-; CHECK-BE-NEXT:    mtvsrwz v5, r4
-; CHECK-BE-NEXT:    vperm v2, v4, v5, v2
-; CHECK-BE-NEXT:    xxmrghw vs1, v2, v3
-; CHECK-BE-NEXT:    xxmrghd vs0, vs1, vs0
+; CHECK-BE-NEXT:    mtfprwz f0, r4
+; CHECK-BE-NEXT:    xxperm vs0, vs5, vs1
+; CHECK-BE-NEXT:    stxv vs3, 0(r3)
+; CHECK-BE-NEXT:    xxmrghw vs0, vs0, vs4
+; CHECK-BE-NEXT:    xxmrghd vs0, vs0, vs2
 ; CHECK-BE-NEXT:    stxv vs0, 16(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <16 x float>, <16 x float>* %0, align 64
   %1 = fptoui <16 x float> %a to <16 x i16>
   store <16 x i16> %1, <16 x i16>* %agg.result, align 32
   ret void
 }

 ; CHECK-P9-NEXT:    vmrghh v2, v3, v2
 ; CHECK-P9-NEXT:    vextuwrx r3, r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtfprd f0, r3
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
-; CHECK-BE-NEXT:    xscvspdpn f1, vs0
+; CHECK-BE-NEXT:    xscvspdpn f2, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI4_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r3)
+; CHECK-BE-NEXT:    lxv vs1, 0(r3)
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-NEXT:    mffprwz r3, f2
+; CHECK-BE-NEXT:    mtfprwz f2, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    li r3, 0
-; CHECK-BE-NEXT:    vperm v2, v3, v4, v2
+; CHECK-BE-NEXT:    xxperm v2, vs2, vs1
 ; CHECK-BE-NEXT:    vextuwlx r3, r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i64 %a.coerce to <2 x float>
   %1 = fptosi <2 x float> %0 to <2 x i16>
   %2 = bitcast <2 x i16> %1 to i32
   ret i32 %2
 }

 ; CHECK-P9-NEXT:    mtvsrd v2, r3
 ; CHECK-P9-NEXT:    vmrghh v2, v4, v2
 ; CHECK-P9-NEXT:    xxmrglw vs0, v2, v3
 ; CHECK-P9-NEXT:    mfvsrld r3, vs0
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 3
+; CHECK-BE-NEXT:    xxsldwi vs1, v2, v2, 3
+; CHECK-BE-NEXT:    xxswapd vs2, v2
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI5_0@toc@l
-; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    xxswapd vs0, v2
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
-; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    xscvspdpn f0, v2
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vperm v4, v5, v4, v3
-; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
-; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    mtvsrwz v2, r3
-; CHECK-BE-NEXT:    vperm v2, v5, v2, v3
-; CHECK-BE-NEXT:    xxmrghw vs0, v2, v4
+; CHECK-BE-NEXT:    xxsldwi vs3, v2, v2, 1
+; CHECK-BE-NEXT:    xscvspdpn f1, vs1
+; CHECK-BE-NEXT:    xscvspdpn f2, vs2
+; CHECK-BE-NEXT:    xscvspdpn f3, vs3
+; CHECK-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    xscvdpsxws f3, f3
+; CHECK-BE-NEXT:    mffprwz r3, f1
+; CHECK-BE-NEXT:    mtfprwz f1, r3
+; CHECK-BE-NEXT:    mffprwz r3, f2
+; CHECK-BE-NEXT:    mtfprwz f2, r3
+; CHECK-BE-NEXT:    xxperm vs1, vs2, vs0
+; CHECK-BE-NEXT:    xscvspdpn f2, v2
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    mffprwz r3, f2
+; CHECK-BE-NEXT:    mtfprwz f2, r3
+; CHECK-BE-NEXT:    mffprwz r3, f3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
+; CHECK-BE-NEXT:    xxperm vs3, vs2, vs0
+; CHECK-BE-NEXT:    xxmrghw vs0, vs3, vs1
 ; CHECK-BE-NEXT:    mffprd r3, f0
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = fptosi <4 x float> %a to <4 x i16>
   %1 = bitcast <4 x i16> %0 to i64
   ret i64 %1
 }
 

 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test8elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI6_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI6_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r3)
-; CHECK-BE-NEXT:    xxsldwi vs2, vs1, vs1, 3
-; CHECK-BE-NEXT:    xscvspdpn f2, vs2
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    xxswapd vs2, vs1
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
-; CHECK-BE-NEXT:    xscvspdpn f2, vs2
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    xscvspdpn f2, vs1
+; CHECK-BE-NEXT:    lxv vs2, 0(r3)
+; CHECK-BE-NEXT:    xxsldwi vs3, vs1, vs1, 3
+; CHECK-BE-NEXT:    xxswapd vs4, vs1
+; CHECK-BE-NEXT:    xscvspdpn f3, vs3
+; CHECK-BE-NEXT:    xscvspdpn f4, vs4
+; CHECK-BE-NEXT:    xscvdpsxws f3, f3
+; CHECK-BE-NEXT:    xscvdpsxws f4, f4
+; CHECK-BE-NEXT:    mffprwz r3, f3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
+; CHECK-BE-NEXT:    mffprwz r3, f4
+; CHECK-BE-NEXT:    mtfprwz f4, r3
+; CHECK-BE-NEXT:    xxperm vs3, vs4, vs2
+; CHECK-BE-NEXT:    xscvspdpn f4, vs1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    vperm v3, v4, v3, v2
+; CHECK-BE-NEXT:    xscvdpsxws f4, f4
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    xxsldwi vs2, vs0, vs0, 3
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
-; CHECK-BE-NEXT:    xscvspdpn f2, vs2
+; CHECK-BE-NEXT:    mffprwz r3, f4
+; CHECK-BE-NEXT:    mtfprwz f4, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
-; CHECK-BE-NEXT:    xxmrghw vs1, v4, v3
-; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    xxswapd vs2, vs0
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
-; CHECK-BE-NEXT:    xscvspdpn f2, vs2
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    xscvspdpn f2, vs0
+; CHECK-BE-NEXT:    mtfprwz f1, r3
+; CHECK-BE-NEXT:    xxperm vs1, vs4, vs2
+; CHECK-BE-NEXT:    xxswapd vs4, vs0
+; CHECK-BE-NEXT:    xxmrghw vs1, vs1, vs3
+; CHECK-BE-NEXT:    xxsldwi vs3, vs0, vs0, 3
+; CHECK-BE-NEXT:    xscvspdpn f4, vs4
+; CHECK-BE-NEXT:    xscvspdpn f3, vs3
+; CHECK-BE-NEXT:    xscvdpsxws f4, f4
+; CHECK-BE-NEXT:    xscvdpsxws f3, f3
+; CHECK-BE-NEXT:    mffprwz r3, f3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
+; CHECK-BE-NEXT:    mffprwz r3, f4
+; CHECK-BE-NEXT:    mtfprwz f4, r3
+; CHECK-BE-NEXT:    xxperm vs3, vs4, vs2
+; CHECK-BE-NEXT:    xscvspdpn f4, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    vperm v3, v4, v3, v2
+; CHECK-BE-NEXT:    xscvdpsxws f4, f4
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mffprwz r3, f4
+; CHECK-BE-NEXT:    mtfprwz f4, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
-; CHECK-BE-NEXT:    vperm v2, v4, v5, v2
-; CHECK-BE-NEXT:    xxmrghw vs0, v2, v3
+; CHECK-BE-NEXT:    mtfprwz f0, r3
+; CHECK-BE-NEXT:    xxperm vs0, vs4, vs2
+; CHECK-BE-NEXT:    xxmrghw vs0, vs0, vs3
 ; CHECK-BE-NEXT:    xxmrghd v2, vs0, vs1
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <8 x float>, <8 x float>* %0, align 32
   %1 = fptosi <8 x float> %a to <8 x i16>
   ret <8 x i16> %1
 }
 

 ; CHECK-P9-NEXT:    vmrghh v3, v3, v4
 ; CHECK-P9-NEXT:    xxmrglw vs1, v3, v2
 ; CHECK-P9-NEXT:    xxmrgld vs0, vs1, vs0
 ; CHECK-P9-NEXT:    stxv vs0, 16(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test16elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    lxv vs1, 16(r4)
-; CHECK-BE-NEXT:    addis r5, r2, .LCPI7_0@toc@ha
-; CHECK-BE-NEXT:    lxv vs0, 0(r4)
-; CHECK-BE-NEXT:    addi r5, r5, .LCPI7_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r5)
-; CHECK-BE-NEXT:    xxsldwi vs2, vs1, vs1, 3
-; CHECK-BE-NEXT:    xxswapd vs3, vs1
-; CHECK-BE-NEXT:    xscvspdpn f4, vs1
-; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
-; CHECK-BE-NEXT:    xxsldwi vs5, vs0, vs0, 3
-; CHECK-BE-NEXT:    xscvspdpn f2, vs2
+; CHECK-BE-NEXT:    lxv vs3, 16(r4)
+; CHECK-BE-NEXT:    lxv vs0, 32(r4)
+; CHECK-BE-NEXT:    lxv vs2, 48(r4)
+; CHECK-BE-NEXT:    lxv vs5, 0(r4)
+; CHECK-BE-NEXT:    addis r4, r2, .LCPI7_0@toc@ha
+; CHECK-BE-NEXT:    addi r4, r4, .LCPI7_0@toc@l
+; CHECK-BE-NEXT:    lxv vs1, 0(r4)
+; CHECK-BE-NEXT:    xxsldwi vs4, vs3, vs3, 3
+; CHECK-BE-NEXT:    xxswapd vs6, vs3
+; CHECK-BE-NEXT:    xscvspdpn f7, vs3
+; CHECK-BE-NEXT:    xxsldwi vs3, vs3, vs3, 1
+; CHECK-BE-NEXT:    xxsldwi vs8, vs5, vs5, 3
+; CHECK-BE-NEXT:    xscvspdpn f4, vs4
+; CHECK-BE-NEXT:    xscvspdpn f6, vs6
 ; CHECK-BE-NEXT:    xscvspdpn f3, vs3
-; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    xscvdpsxws f7, f7
+; CHECK-BE-NEXT:    xscvspdpn f8, vs8
+; CHECK-BE-NEXT:    xscvdpsxws f4, f4
+; CHECK-BE-NEXT:    xscvdpsxws f6, f6
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mffprwz r5, f2
-; CHECK-BE-NEXT:    xxswapd vs2, vs0
-; CHECK-BE-NEXT:    mtvsrwz v3, r5
-; CHECK-BE-NEXT:    mffprwz r5, f3
-; CHECK-BE-NEXT:    xscvdpsxws f3, f4
+; CHECK-BE-NEXT:    xscvdpsxws f8, f8
+; CHECK-BE-NEXT:    mffprwz r4, f4
+; CHECK-BE-NEXT:    mtfprwz f4, r4
+; CHECK-BE-NEXT:    mffprwz r4, f6
+; CHECK-BE-NEXT:    mtfprwz f6, r4
+; CHECK-BE-NEXT:    mffprwz r4, f7
+; CHECK-BE-NEXT:    xxperm vs4, vs6, vs1
+; CHECK-BE-NEXT:    xxswapd vs6, vs5
+; CHECK-BE-NEXT:    mtfprwz f7, r4
+; CHECK-BE-NEXT:    mffprwz r4, f3
+; CHECK-BE-NEXT:    mtfprwz f3, r4
+; CHECK-BE-NEXT:    mffprwz r4, f8
+; CHECK-BE-NEXT:    xscvspdpn f6, vs6
+; CHECK-BE-NEXT:    xxperm vs3, vs7, vs1
+; CHECK-BE-NEXT:    xscvspdpn f7, vs5
+; CHECK-BE-NEXT:    xxsldwi vs5, vs5, vs5, 1
+; CHECK-BE-NEXT:    mtfprwz f8, r4
+; CHECK-BE-NEXT:    xscvdpsxws f6, f6
+; CHECK-BE-NEXT:    xscvspdpn f5, vs5
+; CHECK-BE-NEXT:    xscvdpsxws f7, f7
+; CHECK-BE-NEXT:    xxmrghw vs3, vs3, vs4
+; CHECK-BE-NEXT:    xscvdpsxws f5, f5
+; CHECK-BE-NEXT:    mffprwz r4, f6
+; CHECK-BE-NEXT:    mtfprwz f6, r4
+; CHECK-BE-NEXT:    mffprwz r4, f7
+; CHECK-BE-NEXT:    mtfprwz f7, r4
+; CHECK-BE-NEXT:    mffprwz r4, f5
+; CHECK-BE-NEXT:    xxperm vs8, vs6, vs1
+; CHECK-BE-NEXT:    xxsldwi vs6, vs2, vs2, 3
+; CHECK-BE-NEXT:    mtfprwz f5, r4
+; CHECK-BE-NEXT:    xscvspdpn f6, vs6
+; CHECK-BE-NEXT:    xxperm vs5, vs7, vs1
+; CHECK-BE-NEXT:    xxswapd vs7, vs2
+; CHECK-BE-NEXT:    xscvdpsxws f6, f6
+; CHECK-BE-NEXT:    xscvspdpn f7, vs7
+; CHECK-BE-NEXT:    xxmrghw vs4, vs5, vs8
+; CHECK-BE-NEXT:    xscvspdpn f5, vs2
+; CHECK-BE-NEXT:    xxsldwi vs2, vs2, vs2, 1
+; CHECK-BE-NEXT:    xscvdpsxws f7, f7
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs2
-; CHECK-BE-NEXT:    mtvsrwz v4, r5
-; CHECK-BE-NEXT:    vperm v3, v4, v3, v2
+; CHECK-BE-NEXT:    xscvdpsxws f5, f5
+; CHECK-BE-NEXT:    xxmrghd vs3, vs4, vs3
+; CHECK-BE-NEXT:    xxsldwi vs4, vs0, vs0, 3
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mffprwz r5, f3
-; CHECK-BE-NEXT:    xscvspdpn f3, vs5
-; CHECK-BE-NEXT:    mtvsrwz v4, r5
-; CHECK-BE-NEXT:    mffprwz r5, f1
-; CHECK-BE-NEXT:    xscvspdpn f1, vs0
-; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
-; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    mtvsrwz v5, r5
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r5, f1
-; CHECK-BE-NEXT:    mtvsrwz v5, r5
-; CHECK-BE-NEXT:    mffprwz r5, f3
-; CHECK-BE-NEXT:    mtvsrwz v0, r5
-; CHECK-BE-NEXT:    mffprwz r5, f2
-; CHECK-BE-NEXT:    xxmrghw vs2, v4, v3
-; CHECK-BE-NEXT:    mtvsrwz v1, r5
-; CHECK-BE-NEXT:    mffprwz r5, f0
-; CHECK-BE-NEXT:    lxv vs0, 48(r4)
-; CHECK-BE-NEXT:    vperm v0, v1, v0, v2
-; CHECK-BE-NEXT:    mtvsrwz v1, r5
-; CHECK-BE-NEXT:    vperm v5, v5, v1, v2
-; CHECK-BE-NEXT:    xxsldwi vs1, vs0, vs0, 3
-; CHECK-BE-NEXT:    xxswapd vs3, vs0
-; CHECK-BE-NEXT:    xscvspdpn f4, vs0
+; CHECK-BE-NEXT:    mffprwz r4, f6
+; CHECK-BE-NEXT:    xscvspdpn f4, vs4
+; CHECK-BE-NEXT:    mtfprwz f6, r4
+; CHECK-BE-NEXT:    xscvdpsxws f4, f4
+; CHECK-BE-NEXT:    mffprwz r4, f7
+; CHECK-BE-NEXT:    mtfprwz f7, r4
+; CHECK-BE-NEXT:    mffprwz r4, f5
+; CHECK-BE-NEXT:    mtfprwz f5, r4
+; CHECK-BE-NEXT:    mffprwz r4, f2
+; CHECK-BE-NEXT:    xxperm vs6, vs7, vs1
+; CHECK-BE-NEXT:    mtfprwz f2, r4
+; CHECK-BE-NEXT:    mffprwz r4, f4
+; CHECK-BE-NEXT:    xxperm vs2, vs5, vs1
+; CHECK-BE-NEXT:    xxswapd vs5, vs0
+; CHECK-BE-NEXT:    mtfprwz f4, r4
+; CHECK-BE-NEXT:    xscvspdpn f5, vs5
+; CHECK-BE-NEXT:    xxmrghw vs2, vs2, vs6
+; CHECK-BE-NEXT:    xscvdpsxws f5, f5
+; CHECK-BE-NEXT:    mffprwz r4, f5
+; CHECK-BE-NEXT:    mtfprwz f5, r4
+; CHECK-BE-NEXT:    xxperm vs4, vs5, vs1
+; CHECK-BE-NEXT:    xscvspdpn f5, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
-; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    xscvspdpn f3, vs3
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    xscvdpsxws f4, f4
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    xscvdpsxws f3, f3
+; CHECK-BE-NEXT:    xscvdpsxws f5, f5
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r5, f1
-; CHECK-BE-NEXT:    lxv vs1, 32(r4)
-; CHECK-BE-NEXT:    mffprwz r4, f4
-; CHECK-BE-NEXT:    mtvsrwz v3, r5
-; CHECK-BE-NEXT:    mffprwz r5, f3
-; CHECK-BE-NEXT:    xxmrghw vs3, v5, v0
-; CHECK-BE-NEXT:    mtvsrwz v4, r5
-; CHECK-BE-NEXT:    xxmrghd vs2, vs3, vs2
-; CHECK-BE-NEXT:    xxsldwi vs3, vs1, vs1, 3
-; CHECK-BE-NEXT:    vperm v3, v4, v3, v2
-; CHECK-BE-NEXT:    mtvsrwz v4, r4
+; CHECK-BE-NEXT:    mffprwz r4, f5
+; CHECK-BE-NEXT:    mtfprwz f5, r4
 ; CHECK-BE-NEXT:    mffprwz r4, f0
-; CHECK-BE-NEXT:    xscvspdpn f3, vs3
-; CHECK-BE-NEXT:    mtvsrwz v5, r4
-; CHECK-BE-NEXT:    stxv vs2, 0(r3)
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
-; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    xxmrghw vs0, v4, v3
-; CHECK-BE-NEXT:    mffprwz r4, f3
-; CHECK-BE-NEXT:    xxswapd vs3, vs1
-; CHECK-BE-NEXT:    mtvsrwz v3, r4
-; CHECK-BE-NEXT:    xscvspdpn f3, vs3
-; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    mffprwz r4, f3
-; CHECK-BE-NEXT:    xscvspdpn f3, vs1
-; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
-; CHECK-BE-NEXT:    mtvsrwz v4, r4
-; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    vperm v3, v4, v3, v2
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mffprwz r4, f3
-; CHECK-BE-NEXT:    mtvsrwz v4, r4
-; CHECK-BE-NEXT:    mffprwz r4, f1
-; CHECK-BE-NEXT:    mtvsrwz v5, r4
-; CHECK-BE-NEXT:    vperm v2, v4, v5, v2
-; CHECK-BE-NEXT:    xxmrghw vs1, v2, v3
-; CHECK-BE-NEXT:    xxmrghd vs0, vs1, vs0
+; CHECK-BE-NEXT:    mtfprwz f0, r4
+; CHECK-BE-NEXT:    xxperm vs0, vs5, vs1
+; CHECK-BE-NEXT:    stxv vs3, 0(r3)
+; CHECK-BE-NEXT:    xxmrghw vs0, vs0, vs4
+; CHECK-BE-NEXT:    xxmrghd vs0, vs0, vs2
 ; CHECK-BE-NEXT:    stxv vs0, 16(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <16 x float>, <16 x float>* %0, align 64
   %1 = fptosi <16 x float> %a to <16 x i16>
   store <16 x i16> %1, <16 x i16>* %agg.result, align 32
   ret void
 }

llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i8_elts.ll

 ; CHECK-P9-NEXT:    stxsihx v2, 0, r3
 ; CHECK-P9-NEXT:    lhz r3, -2(r1)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtfprd f0, r3
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
-; CHECK-BE-NEXT:    xscvspdpn f1, vs0
+; CHECK-BE-NEXT:    xscvspdpn f2, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI0_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r3)
+; CHECK-BE-NEXT:    lxv vs1, 0(r3)
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-NEXT:    mffprwz r3, f2
+; CHECK-BE-NEXT:    mtfprwz f2, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    addi r3, r1, -2
-; CHECK-BE-NEXT:    vperm v2, v3, v4, v2
+; CHECK-BE-NEXT:    xxperm v2, vs2, vs1
 ; CHECK-BE-NEXT:    vsldoi v2, v2, v2, 10
 ; CHECK-BE-NEXT:    stxsihx v2, 0, r3
 ; CHECK-BE-NEXT:    lhz r3, -2(r1)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i64 %a.coerce to <2 x float>
   %1 = fptoui <2 x float> %0 to <2 x i8>
   %2 = bitcast <2 x i8> %1 to i16

 ; CHECK-P9-NEXT:    li r3, 0
 ; CHECK-P9-NEXT:    vmrghb v2, v4, v2
 ; CHECK-P9-NEXT:    vmrglh v2, v2, v3
 ; CHECK-P9-NEXT:    vextuwrx r3, r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 3
+; CHECK-BE-NEXT:    xxsldwi vs1, v2, v2, 3
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
+; CHECK-BE-NEXT:    xxsldwi vs2, v2, v2, 1
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI1_0@toc@l
-; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    xxswapd vs0, v2
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
-; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    xscvspdpn f0, v2
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vperm v4, v5, v4, v3
-; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
-; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f0
+; CHECK-BE-NEXT:    xscvspdpn f1, vs1
+; CHECK-BE-NEXT:    xscvspdpn f2, vs2
+; CHECK-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    mffprwz r3, f1
+; CHECK-BE-NEXT:    xxswapd vs1, v2
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-NEXT:    xscvspdpn f1, vs1
+; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
+; CHECK-BE-NEXT:    mtfprwz f1, r3
+; CHECK-BE-NEXT:    xxperm v3, vs1, vs0
+; CHECK-BE-NEXT:    xscvspdpn f1, v2
+; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
+; CHECK-BE-NEXT:    mtfprwz f1, r3
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    li r3, 0
-; CHECK-BE-NEXT:    vperm v2, v5, v2, v3
-; CHECK-BE-NEXT:    vmrghh v2, v2, v4
+; CHECK-BE-NEXT:    xxperm v2, vs1, vs0
+; CHECK-BE-NEXT:    vmrghh v2, v2, v3
 ; CHECK-BE-NEXT:    vextuwlx r3, r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = fptoui <4 x float> %a to <4 x i8>
   %1 = bitcast <4 x i8> %0 to i32
   ret i32 %1
 }
 

 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test8elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI2_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r3)
-; CHECK-BE-NEXT:    xxsldwi vs2, vs1, vs1, 3
-; CHECK-BE-NEXT:    xscvspdpn f2, vs2
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    xxswapd vs2, vs1
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
-; CHECK-BE-NEXT:    xscvspdpn f2, vs2
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    xscvspdpn f2, vs1
+; CHECK-BE-NEXT:    lxv vs2, 0(r3)
+; CHECK-BE-NEXT:    xxsldwi vs3, vs1, vs1, 3
+; CHECK-BE-NEXT:    xscvspdpn f3, vs3
+; CHECK-BE-NEXT:    xscvdpsxws f3, f3
+; CHECK-BE-NEXT:    mffprwz r3, f3
+; CHECK-BE-NEXT:    xxswapd vs3, vs1
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
+; CHECK-BE-NEXT:    xscvspdpn f3, vs3
+; CHECK-BE-NEXT:    xscvdpsxws f3, f3
+; CHECK-BE-NEXT:    mffprwz r3, f3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
+; CHECK-BE-NEXT:    xxperm v2, vs3, vs2
+; CHECK-BE-NEXT:    xscvspdpn f3, vs1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    vperm v3, v4, v3, v2
+; CHECK-BE-NEXT:    xscvdpsxws f3, f3
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mffprwz r3, f3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs0, vs0, 3
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xxperm v3, vs3, vs2
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vmrghh v3, v4, v3
+; CHECK-BE-NEXT:    vmrghh v2, v3, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs0
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    mffprwz r3, f1
+; CHECK-BE-NEXT:    mtfprwz f1, r3
+; CHECK-BE-NEXT:    xxperm v3, vs1, vs2
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vperm v4, v5, v4, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtfprwz f1, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    mtvsrwz v0, r3
-; CHECK-BE-NEXT:    vperm v2, v5, v0, v2
-; CHECK-BE-NEXT:    vmrghh v2, v2, v4
-; CHECK-BE-NEXT:    xxmrghw vs0, v2, v3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    xxperm v4, vs1, vs2
+; CHECK-BE-NEXT:    vmrghh v3, v4, v3
+; CHECK-BE-NEXT:    xxmrghw vs0, v3, v2
 ; CHECK-BE-NEXT:    mffprd r3, f0
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <8 x float>, <8 x float>* %0, align 32
   %1 = fptoui <8 x float> %a to <8 x i8>
   %2 = bitcast <8 x i8> %1 to i64
   ret i64 %2
 }

 ; CHECK-P9-NEXT:    vmrghb v4, v4, v5
 ; CHECK-P9-NEXT:    vmrglh v3, v4, v3
 ; CHECK-P9-NEXT:    xxmrglw vs0, v3, v2
 ; CHECK-P9-NEXT:    xxmrgld v2, vs0, vs2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test16elt:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    lxv vs3, 48(r3)
-; CHECK-BE-NEXT:    lxv vs0, 0(r3)
-; CHECK-BE-NEXT:    lxv vs1, 16(r3)
-; CHECK-BE-NEXT:    lxv vs2, 32(r3)
+; CHECK-BE-NEXT:    lxv vs4, 48(r3)
+; CHECK-BE-NEXT:    lxv vs1, 0(r3)
+; CHECK-BE-NEXT:    lxv vs2, 16(r3)
+; CHECK-BE-NEXT:    lxv vs3, 32(r3)
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI3_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r3)
+; CHECK-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-BE-NEXT:    xxsldwi vs5, vs4, vs4, 3
+; CHECK-BE-NEXT:    xscvspdpn f5, vs5
+; CHECK-BE-NEXT:    xscvdpsxws f5, f5
+; CHECK-BE-NEXT:    mffprwz r3, f5
+; CHECK-BE-NEXT:    xxswapd vs5, vs4
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
+; CHECK-BE-NEXT:    xscvspdpn f5, vs5
+; CHECK-BE-NEXT:    xscvdpsxws f5, f5
+; CHECK-BE-NEXT:    mffprwz r3, f5
+; CHECK-BE-NEXT:    mtfprwz f5, r3
+; CHECK-BE-NEXT:    xxperm v2, vs5, vs0
+; CHECK-BE-NEXT:    xscvspdpn f5, vs4
+; CHECK-BE-NEXT:    xxsldwi vs4, vs4, vs4, 1
+; CHECK-BE-NEXT:    xscvspdpn f4, vs4
+; CHECK-BE-NEXT:    xscvdpsxws f5, f5
+; CHECK-BE-NEXT:    xscvdpsxws f4, f4
+; CHECK-BE-NEXT:    mffprwz r3, f5
+; CHECK-BE-NEXT:    mtfprwz f5, r3
+; CHECK-BE-NEXT:    mffprwz r3, f4
 ; CHECK-BE-NEXT:    xxsldwi vs4, vs3, vs3, 3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvspdpn f4, vs4
+; CHECK-BE-NEXT:    xxperm v3, vs5, vs0
 ; CHECK-BE-NEXT:    xscvdpsxws f4, f4
+; CHECK-BE-NEXT:    vmrghh v2, v3, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f4
 ; CHECK-BE-NEXT:    xxswapd vs4, vs3
 ; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvspdpn f4, vs4
 ; CHECK-BE-NEXT:    xscvdpsxws f4, f4
 ; CHECK-BE-NEXT:    mffprwz r3, f4
+; CHECK-BE-NEXT:    mtfprwz f4, r3
+; CHECK-BE-NEXT:    xxperm v3, vs4, vs0
 ; CHECK-BE-NEXT:    xscvspdpn f4, vs3
 ; CHECK-BE-NEXT:    xxsldwi vs3, vs3, vs3, 1
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvspdpn f3, vs3
 ; CHECK-BE-NEXT:    xscvdpsxws f4, f4
-; CHECK-BE-NEXT:    vperm v3, v4, v3, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
 ; CHECK-BE-NEXT:    mffprwz r3, f4
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtfprwz f4, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f3
-; CHECK-BE-NEXT:    xxsldwi vs3, vs2, vs2, 3
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
-; CHECK-BE-NEXT:    xscvspdpn f3, vs3
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
-; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    vmrghh v3, v4, v3
-; CHECK-BE-NEXT:    mffprwz r3, f3
-; CHECK-BE-NEXT:    xxswapd vs3, vs2
 ; CHECK-BE-NEXT:    mtvsrwz v4, r3
-; CHECK-BE-NEXT:    xscvspdpn f3, vs3
-; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    mffprwz r3, f3
-; CHECK-BE-NEXT:    xscvspdpn f3, vs2
+; CHECK-BE-NEXT:    xxperm v4, vs4, vs0
+; CHECK-BE-NEXT:    xxsldwi vs4, vs2, vs2, 3
+; CHECK-BE-NEXT:    xscvspdpn f4, vs4
+; CHECK-BE-NEXT:    vmrghh v3, v4, v3
+; CHECK-BE-NEXT:    xscvdpsxws f4, f4
+; CHECK-BE-NEXT:    xxmrghw vs3, v3, v2
+; CHECK-BE-NEXT:    mffprwz r3, f4
+; CHECK-BE-NEXT:    xxswapd vs4, vs2
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
+; CHECK-BE-NEXT:    xscvspdpn f4, vs4
+; CHECK-BE-NEXT:    xscvdpsxws f4, f4
+; CHECK-BE-NEXT:    mffprwz r3, f4
+; CHECK-BE-NEXT:    mtfprwz f4, r3
+; CHECK-BE-NEXT:    xxperm v2, vs4, vs0
+; CHECK-BE-NEXT:    xscvspdpn f4, vs2
 ; CHECK-BE-NEXT:    xxsldwi vs2, vs2, vs2, 1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
-; CHECK-BE-NEXT:    xscvdpsxws f3, f3
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs2
-; CHECK-BE-NEXT:    vperm v4, v5, v4, v2
+; CHECK-BE-NEXT:    xscvdpsxws f4, f4
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mffprwz r3, f3
-; CHECK-BE-NEXT:    xxsldwi vs3, vs1, vs1, 3
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
-; CHECK-BE-NEXT:    xscvspdpn f3, vs3
+; CHECK-BE-NEXT:    mffprwz r3, f4
+; CHECK-BE-NEXT:    mtfprwz f4, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    mtvsrwz v0, r3
-; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    vperm v5, v5, v0, v2
-; CHECK-BE-NEXT:    vmrghh v4, v5, v4
-; CHECK-BE-NEXT:    mffprwz r3, f3
-; CHECK-BE-NEXT:    xxswapd vs3, vs1
-; CHECK-BE-NEXT:    xxmrghw vs2, v4, v3
+; CHECK-BE-NEXT:    xxsldwi vs2, vs1, vs1, 3
 ; CHECK-BE-NEXT:    mtvsrwz v3, r3
-; CHECK-BE-NEXT:    xscvspdpn f3, vs3
-; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    mffprwz r3, f3
-; CHECK-BE-NEXT:    xscvspdpn f3, vs1
+; CHECK-BE-NEXT:    xscvspdpn f2, vs2
+; CHECK-BE-NEXT:    xxperm v3, vs4, vs0
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    vmrghh v2, v3, v2
+; CHECK-BE-NEXT:    mffprwz r3, f2
+; CHECK-BE-NEXT:    xxswapd vs2, vs1
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-NEXT:    xscvspdpn f2, vs2
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    mffprwz r3, f2
+; CHECK-BE-NEXT:    mtfprwz f2, r3
+; CHECK-BE-NEXT:    xxperm v3, vs2, vs0
+; CHECK-BE-NEXT:    xscvspdpn f2, vs1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
-; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    vperm v3, v4, v3, v2
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mffprwz r3, f3
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
-; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    xxsldwi vs1, vs0, vs0, 3
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vmrghh v3, v4, v3
+; CHECK-BE-NEXT:    mffprwz r3, f2
+; CHECK-BE-NEXT:    mtfprwz f2, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    xxswapd vs1, vs0
 ; CHECK-BE-NEXT:    mtvsrwz v4, r3
-; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    xscvspdpn f1, vs0
-; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
-; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vperm v4, v5, v4, v2
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
-; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    mtvsrwz v0, r3
-; CHECK-BE-NEXT:    vperm v2, v5, v0, v2
-; CHECK-BE-NEXT:    vmrghh v2, v2, v4
-; CHECK-BE-NEXT:    xxmrghw vs0, v2, v3
-; CHECK-BE-NEXT:    xxmrghd v2, vs0, vs2
+; CHECK-BE-NEXT:    xxperm v4, vs2, vs0
+; CHECK-BE-NEXT:    vmrghh v3, v4, v3
+; CHECK-BE-NEXT:    xxmrghw vs0, v3, v2
+; CHECK-BE-NEXT:    xxmrghd v2, vs0, vs3
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <16 x float>, <16 x float>* %0, align 64
   %1 = fptoui <16 x float> %a to <16 x i8>
   ret <16 x i8> %1
 }
 
 define i16 @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 {

 ; CHECK-P9-NEXT:    stxsihx v2, 0, r3
 ; CHECK-P9-NEXT:    lhz r3, -2(r1)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtfprd f0, r3
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
-; CHECK-BE-NEXT:    xscvspdpn f1, vs0
+; CHECK-BE-NEXT:    xscvspdpn f2, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI4_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r3)
+; CHECK-BE-NEXT:    lxv vs1, 0(r3)
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-NEXT:    mffprwz r3, f2
+; CHECK-BE-NEXT:    mtfprwz f2, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    addi r3, r1, -2
-; CHECK-BE-NEXT:    vperm v2, v3, v4, v2
+; CHECK-BE-NEXT:    xxperm v2, vs2, vs1
 ; CHECK-BE-NEXT:    vsldoi v2, v2, v2, 10
 ; CHECK-BE-NEXT:    stxsihx v2, 0, r3
 ; CHECK-BE-NEXT:    lhz r3, -2(r1)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i64 %a.coerce to <2 x float>
   %1 = fptosi <2 x float> %0 to <2 x i8>
   %2 = bitcast <2 x i8> %1 to i16

 ; CHECK-P9-NEXT:    li r3, 0
 ; CHECK-P9-NEXT:    vmrghb v2, v4, v2
 ; CHECK-P9-NEXT:    vmrglh v2, v2, v3
 ; CHECK-P9-NEXT:    vextuwrx r3, r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 3
+; CHECK-BE-NEXT:    xxsldwi vs1, v2, v2, 3
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
+; CHECK-BE-NEXT:    xxsldwi vs2, v2, v2, 1
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI5_0@toc@l
-; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    xxswapd vs0, v2
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
-; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    xscvspdpn f0, v2
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vperm v4, v5, v4, v3
-; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
-; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f0
+; CHECK-BE-NEXT:    xscvspdpn f1, vs1
+; CHECK-BE-NEXT:    xscvspdpn f2, vs2
+; CHECK-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    mffprwz r3, f1
+; CHECK-BE-NEXT:    xxswapd vs1, v2
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-NEXT:    xscvspdpn f1, vs1
+; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
+; CHECK-BE-NEXT:    mtfprwz f1, r3
+; CHECK-BE-NEXT:    xxperm v3, vs1, vs0
+; CHECK-BE-NEXT:    xscvspdpn f1, v2
+; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
+; CHECK-BE-NEXT:    mtfprwz f1, r3
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    li r3, 0
-; CHECK-BE-NEXT:    vperm v2, v5, v2, v3
-; CHECK-BE-NEXT:    vmrghh v2, v2, v4
+; CHECK-BE-NEXT:    xxperm v2, vs1, vs0
+; CHECK-BE-NEXT:    vmrghh v2, v2, v3
 ; CHECK-BE-NEXT:    vextuwlx r3, r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = fptosi <4 x float> %a to <4 x i8>
   %1 = bitcast <4 x i8> %0 to i32
   ret i32 %1
 }
 

 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test8elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI6_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI6_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r3)
-; CHECK-BE-NEXT:    xxsldwi vs2, vs1, vs1, 3
-; CHECK-BE-NEXT:    xscvspdpn f2, vs2
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    xxswapd vs2, vs1
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
-; CHECK-BE-NEXT:    xscvspdpn f2, vs2
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    xscvspdpn f2, vs1
+; CHECK-BE-NEXT:    lxv vs2, 0(r3)
+; CHECK-BE-NEXT:    xxsldwi vs3, vs1, vs1, 3
+; CHECK-BE-NEXT:    xscvspdpn f3, vs3
+; CHECK-BE-NEXT:    xscvdpsxws f3, f3
+; CHECK-BE-NEXT:    mffprwz r3, f3
+; CHECK-BE-NEXT:    xxswapd vs3, vs1
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
+; CHECK-BE-NEXT:    xscvspdpn f3, vs3
+; CHECK-BE-NEXT:    xscvdpsxws f3, f3
+; CHECK-BE-NEXT:    mffprwz r3, f3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
+; CHECK-BE-NEXT:    xxperm v2, vs3, vs2
+; CHECK-BE-NEXT:    xscvspdpn f3, vs1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    vperm v3, v4, v3, v2
+; CHECK-BE-NEXT:    xscvdpsxws f3, f3
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mffprwz r3, f3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs0, vs0, 3
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xxperm v3, vs3, vs2
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vmrghh v3, v4, v3
+; CHECK-BE-NEXT:    vmrghh v2, v3, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs0
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    mffprwz r3, f1
+; CHECK-BE-NEXT:    mtfprwz f1, r3
+; CHECK-BE-NEXT:    xxperm v3, vs1, vs2
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vperm v4, v5, v4, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtfprwz f1, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    mtvsrwz v0, r3
-; CHECK-BE-NEXT:    vperm v2, v5, v0, v2
-; CHECK-BE-NEXT:    vmrghh v2, v2, v4
-; CHECK-BE-NEXT:    xxmrghw vs0, v2, v3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    xxperm v4, vs1, vs2
+; CHECK-BE-NEXT:    vmrghh v3, v4, v3
+; CHECK-BE-NEXT:    xxmrghw vs0, v3, v2
 ; CHECK-BE-NEXT:    mffprd r3, f0
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <8 x float>, <8 x float>* %0, align 32
   %1 = fptosi <8 x float> %a to <8 x i8>
   %2 = bitcast <8 x i8> %1 to i64
   ret i64 %2
 }

 ; CHECK-P9-NEXT:    vmrghb v4, v4, v5
 ; CHECK-P9-NEXT:    vmrglh v3, v4, v3
 ; CHECK-P9-NEXT:    xxmrglw vs0, v3, v2
 ; CHECK-P9-NEXT:    xxmrgld v2, vs0, vs2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test16elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    lxv vs3, 48(r3)
-; CHECK-BE-NEXT:    lxv vs0, 0(r3)
-; CHECK-BE-NEXT:    lxv vs1, 16(r3)
-; CHECK-BE-NEXT:    lxv vs2, 32(r3)
+; CHECK-BE-NEXT:    lxv vs4, 48(r3)
+; CHECK-BE-NEXT:    lxv vs1, 0(r3)
+; CHECK-BE-NEXT:    lxv vs2, 16(r3)
+; CHECK-BE-NEXT:    lxv vs3, 32(r3)
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI7_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI7_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r3)
+; CHECK-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-BE-NEXT:    xxsldwi vs5, vs4, vs4, 3
+; CHECK-BE-NEXT:    xscvspdpn f5, vs5
+; CHECK-BE-NEXT:    xscvdpsxws f5, f5
+; CHECK-BE-NEXT:    mffprwz r3, f5
+; CHECK-BE-NEXT:    xxswapd vs5, vs4
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
+; CHECK-BE-NEXT:    xscvspdpn f5, vs5
+; CHECK-BE-NEXT:    xscvdpsxws f5, f5
+; CHECK-BE-NEXT:    mffprwz r3, f5
+; CHECK-BE-NEXT:    mtfprwz f5, r3
+; CHECK-BE-NEXT:    xxperm v2, vs5, vs0
+; CHECK-BE-NEXT:    xscvspdpn f5, vs4
+; CHECK-BE-NEXT:    xxsldwi vs4, vs4, vs4, 1
+; CHECK-BE-NEXT:    xscvspdpn f4, vs4
+; CHECK-BE-NEXT:    xscvdpsxws f5, f5
+; CHECK-BE-NEXT:    xscvdpsxws f4, f4
+; CHECK-BE-NEXT:    mffprwz r3, f5
+; CHECK-BE-NEXT:    mtfprwz f5, r3
+; CHECK-BE-NEXT:    mffprwz r3, f4
 ; CHECK-BE-NEXT:    xxsldwi vs4, vs3, vs3, 3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvspdpn f4, vs4
+; CHECK-BE-NEXT:    xxperm v3, vs5, vs0
 ; CHECK-BE-NEXT:    xscvdpsxws f4, f4
+; CHECK-BE-NEXT:    vmrghh v2, v3, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f4
 ; CHECK-BE-NEXT:    xxswapd vs4, vs3
 ; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvspdpn f4, vs4
 ; CHECK-BE-NEXT:    xscvdpsxws f4, f4
 ; CHECK-BE-NEXT:    mffprwz r3, f4
+; CHECK-BE-NEXT:    mtfprwz f4, r3
+; CHECK-BE-NEXT:    xxperm v3, vs4, vs0
 ; CHECK-BE-NEXT:    xscvspdpn f4, vs3
 ; CHECK-BE-NEXT:    xxsldwi vs3, vs3, vs3, 1
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvspdpn f3, vs3
 ; CHECK-BE-NEXT:    xscvdpsxws f4, f4
-; CHECK-BE-NEXT:    vperm v3, v4, v3, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
 ; CHECK-BE-NEXT:    mffprwz r3, f4
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtfprwz f4, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f3
-; CHECK-BE-NEXT:    xxsldwi vs3, vs2, vs2, 3
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
-; CHECK-BE-NEXT:    xscvspdpn f3, vs3
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
-; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    vmrghh v3, v4, v3
-; CHECK-BE-NEXT:    mffprwz r3, f3
-; CHECK-BE-NEXT:    xxswapd vs3, vs2
 ; CHECK-BE-NEXT:    mtvsrwz v4, r3
-; CHECK-BE-NEXT:    xscvspdpn f3, vs3
-; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    mffprwz r3, f3
-; CHECK-BE-NEXT:    xscvspdpn f3, vs2
+; CHECK-BE-NEXT:    xxperm v4, vs4, vs0
+; CHECK-BE-NEXT:    xxsldwi vs4, vs2, vs2, 3
+; CHECK-BE-NEXT:    xscvspdpn f4, vs4
+; CHECK-BE-NEXT:    vmrghh v3, v4, v3
+; CHECK-BE-NEXT:    xscvdpsxws f4, f4
+; CHECK-BE-NEXT:    xxmrghw vs3, v3, v2
+; CHECK-BE-NEXT:    mffprwz r3, f4
+; CHECK-BE-NEXT:    xxswapd vs4, vs2
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
+; CHECK-BE-NEXT:    xscvspdpn f4, vs4
+; CHECK-BE-NEXT:    xscvdpsxws f4, f4
+; CHECK-BE-NEXT:    mffprwz r3, f4
+; CHECK-BE-NEXT:    mtfprwz f4, r3
+; CHECK-BE-NEXT:    xxperm v2, vs4, vs0
+; CHECK-BE-NEXT:    xscvspdpn f4, vs2
 ; CHECK-BE-NEXT:    xxsldwi vs2, vs2, vs2, 1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
-; CHECK-BE-NEXT:    xscvdpsxws f3, f3
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs2
-; CHECK-BE-NEXT:    vperm v4, v5, v4, v2
+; CHECK-BE-NEXT:    xscvdpsxws f4, f4
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mffprwz r3, f3
-; CHECK-BE-NEXT:    xxsldwi vs3, vs1, vs1, 3
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
-; CHECK-BE-NEXT:    xscvspdpn f3, vs3
+; CHECK-BE-NEXT:    mffprwz r3, f4
+; CHECK-BE-NEXT:    mtfprwz f4, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    mtvsrwz v0, r3
-; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    vperm v5, v5, v0, v2
-; CHECK-BE-NEXT:    vmrghh v4, v5, v4
-; CHECK-BE-NEXT:    mffprwz r3, f3
-; CHECK-BE-NEXT:    xxswapd vs3, vs1
-; CHECK-BE-NEXT:    xxmrghw vs2, v4, v3
+; CHECK-BE-NEXT:    xxsldwi vs2, vs1, vs1, 3
 ; CHECK-BE-NEXT:    mtvsrwz v3, r3
-; CHECK-BE-NEXT:    xscvspdpn f3, vs3
-; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    mffprwz r3, f3
-; CHECK-BE-NEXT:    xscvspdpn f3, vs1
+; CHECK-BE-NEXT:    xscvspdpn f2, vs2
+; CHECK-BE-NEXT:    xxperm v3, vs4, vs0
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    vmrghh v2, v3, v2
+; CHECK-BE-NEXT:    mffprwz r3, f2
+; CHECK-BE-NEXT:    xxswapd vs2, vs1
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-NEXT:    xscvspdpn f2, vs2
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    mffprwz r3, f2
+; CHECK-BE-NEXT:    mtfprwz f2, r3
+; CHECK-BE-NEXT:    xxperm v3, vs2, vs0
+; CHECK-BE-NEXT:    xscvspdpn f2, vs1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
-; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    vperm v3, v4, v3, v2
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mffprwz r3, f3
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
-; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    xxsldwi vs1, vs0, vs0, 3
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vmrghh v3, v4, v3
+; CHECK-BE-NEXT:    mffprwz r3, f2
+; CHECK-BE-NEXT:    mtfprwz f2, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    xxswapd vs1, vs0
 ; CHECK-BE-NEXT:    mtvsrwz v4, r3
-; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    xscvspdpn f1, vs0
-; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
-; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vperm v4, v5, v4, v2
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
-; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    mtvsrwz v0, r3
-; CHECK-BE-NEXT:    vperm v2, v5, v0, v2
-; CHECK-BE-NEXT:    vmrghh v2, v2, v4
-; CHECK-BE-NEXT:    xxmrghw vs0, v2, v3
-; CHECK-BE-NEXT:    xxmrghd v2, vs0, vs2
+; CHECK-BE-NEXT:    xxperm v4, vs2, vs0
+; CHECK-BE-NEXT:    vmrghh v3, v4, v3
+; CHECK-BE-NEXT:    xxmrghw vs0, v3, v2
+; CHECK-BE-NEXT:    xxmrghd v2, vs0, vs3
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <16 x float>, <16 x float>* %0, align 64
   %1 = fptosi <16 x float> %a to <16 x i8>
   ret <16 x i8> %1
 }

llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i16_elts.ll

 ; CHECK-P9-NEXT:    mtvsrd v2, r3
 ; CHECK-P9-NEXT:    li r3, 0
 ; CHECK-P9-NEXT:    vmrghh v2, v3, v2
 ; CHECK-P9-NEXT:    vextuwrx r3, r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    xscvdpsxws f0, v2
+; CHECK-BE-NEXT:    xxswapd vs2, v2
+; CHECK-BE-NEXT:    xscvdpsxws f1, v2
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI0_0@toc@l
-; CHECK-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    xxswapd vs0, v2
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f0
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-BE-NEXT:    mffprwz r3, f1
+; CHECK-BE-NEXT:    mtfprwz f1, r3
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    li r3, 0
-; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
+; CHECK-BE-NEXT:    xxperm v2, vs1, vs0
 ; CHECK-BE-NEXT:    vextuwlx r3, r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = fptoui <2 x double> %a to <2 x i16>
   %1 = bitcast <2 x i16> %0 to i32
   ret i32 %1
 }
 

 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI1_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r3)
-; CHECK-BE-NEXT:    xscvdpsxws f2, f1
+; CHECK-BE-NEXT:    lxv vs2, 0(r3)
+; CHECK-BE-NEXT:    xscvdpsxws f3, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-NEXT:    mffprwz r3, f3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    xscvdpsxws f1, f0
+; CHECK-BE-NEXT:    mtfprwz f1, r3
+; CHECK-BE-NEXT:    xxperm vs1, vs3, vs2
+; CHECK-BE-NEXT:    xscvdpsxws f3, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vperm v3, v3, v4, v2
-; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mffprwz r3, f3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
-; CHECK-BE-NEXT:    vperm v2, v4, v5, v2
-; CHECK-BE-NEXT:    xxmrghw vs0, v2, v3
+; CHECK-BE-NEXT:    mtfprwz f0, r3
+; CHECK-BE-NEXT:    xxperm vs0, vs3, vs2
+; CHECK-BE-NEXT:    xxmrghw vs0, vs0, vs1
 ; CHECK-BE-NEXT:    mffprd r3, f0
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <4 x double>, <4 x double>* %0, align 32
   %1 = fptoui <4 x double> %a to <4 x i16>
   %2 = bitcast <4 x i16> %1 to i64
   ret i64 %2
 }

 ; CHECK-BE-LABEL: test8elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI2_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r3)
-; CHECK-BE-NEXT:    xscvdpsxws f4, f3
+; CHECK-BE-NEXT:    lxv vs4, 0(r3)
+; CHECK-BE-NEXT:    xscvdpsxws f5, f3
 ; CHECK-BE-NEXT:    xxswapd vs3, vs3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    mffprwz r3, f4
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-NEXT:    mffprwz r3, f5
+; CHECK-BE-NEXT:    mtfprwz f5, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f3
-; CHECK-BE-NEXT:    xscvdpsxws f3, f2
+; CHECK-BE-NEXT:    mtfprwz f3, r3
+; CHECK-BE-NEXT:    xxperm vs3, vs5, vs4
+; CHECK-BE-NEXT:    xscvdpsxws f5, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs2
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    vperm v3, v3, v4, v2
-; CHECK-BE-NEXT:    mffprwz r3, f3
+; CHECK-BE-NEXT:    mffprwz r3, f5
+; CHECK-BE-NEXT:    mtfprwz f5, r3
+; CHECK-BE-NEXT:    mffprwz r3, f2
+; CHECK-BE-NEXT:    mtfprwz f2, r3
+; CHECK-BE-NEXT:    xxperm vs2, vs5, vs4
+; CHECK-BE-NEXT:    xxmrghw vs2, vs2, vs3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
-; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f3
-; CHECK-BE-NEXT:    xxmrghw vs2, v4, v3
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    xscvdpsxws f1, f0
+; CHECK-BE-NEXT:    mtfprwz f1, r3
+; CHECK-BE-NEXT:    xxperm vs1, vs3, vs4
+; CHECK-BE-NEXT:    xscvdpsxws f3, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vperm v3, v3, v4, v2
-; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mffprwz r3, f3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
-; CHECK-BE-NEXT:    vperm v2, v4, v5, v2
-; CHECK-BE-NEXT:    xxmrghw vs0, v2, v3
+; CHECK-BE-NEXT:    mtfprwz f0, r3
+; CHECK-BE-NEXT:    xxperm vs0, vs3, vs4
+; CHECK-BE-NEXT:    xxmrghw vs0, vs0, vs1
 ; CHECK-BE-NEXT:    xxmrghd v2, vs0, vs2
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <8 x double>, <8 x double>* %0, align 64
   %1 = fptoui <8 x double> %a to <8 x i16>
   ret <8 x i16> %1
 }
 

 ; CHECK-P9-NEXT:    vmrghh v3, v3, v4
 ; CHECK-P9-NEXT:    xxmrglw vs0, v3, v2
 ; CHECK-P9-NEXT:    xxmrgld vs0, vs0, vs2
 ; CHECK-P9-NEXT:    stxv vs0, 16(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test16elt:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    lxv vs2, 48(r4)
-; CHECK-BE-NEXT:    lxv vs1, 32(r4)
-; CHECK-BE-NEXT:    lxv vs0, 16(r4)
-; CHECK-BE-NEXT:    addis r5, r2, .LCPI3_0@toc@ha
-; CHECK-BE-NEXT:    addi r5, r5, .LCPI3_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r5)
-; CHECK-BE-NEXT:    xscvdpsxws f3, f2
-; CHECK-BE-NEXT:    xscvdpsxws f4, f1
-; CHECK-BE-NEXT:    xxswapd vs2, vs2
-; CHECK-BE-NEXT:    xscvdpsxws f5, f0
-; CHECK-BE-NEXT:    xxswapd vs1, vs1
-; CHECK-BE-NEXT:    xxswapd vs0, vs0
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r5, f3
-; CHECK-BE-NEXT:    lxv vs3, 112(r4)
-; CHECK-BE-NEXT:    mtvsrwz v3, r5
-; CHECK-BE-NEXT:    mffprwz r5, f4
-; CHECK-BE-NEXT:    lxv vs4, 0(r4)
-; CHECK-BE-NEXT:    mtvsrwz v4, r5
-; CHECK-BE-NEXT:    mffprwz r5, f5
-; CHECK-BE-NEXT:    xscvdpsxws f7, f3
-; CHECK-BE-NEXT:    xxswapd vs3, vs3
-; CHECK-BE-NEXT:    mtvsrwz v5, r5
-; CHECK-BE-NEXT:    mffprwz r5, f2
-; CHECK-BE-NEXT:    lxv vs2, 96(r4)
-; CHECK-BE-NEXT:    xscvdpsxws f5, f4
-; CHECK-BE-NEXT:    xxswapd vs4, vs4
-; CHECK-BE-NEXT:    mtvsrwz v0, r5
-; CHECK-BE-NEXT:    mffprwz r5, f1
-; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    lxv vs1, 80(r4)
-; CHECK-BE-NEXT:    xscvdpsxws f4, f4
-; CHECK-BE-NEXT:    vperm v3, v3, v0, v2
-; CHECK-BE-NEXT:    mtvsrwz v0, r5
-; CHECK-BE-NEXT:    mffprwz r5, f0
+; CHECK-BE-NEXT:    lxv vs8, 48(r4)
 ; CHECK-BE-NEXT:    lxv vs0, 64(r4)
-; CHECK-BE-NEXT:    vperm v4, v4, v0, v2
-; CHECK-BE-NEXT:    mtvsrwz v0, r5
+; CHECK-BE-NEXT:    lxv vs2, 80(r4)
+; CHECK-BE-NEXT:    lxv vs3, 96(r4)
+; CHECK-BE-NEXT:    xscvdpsxws f9, f8
+; CHECK-BE-NEXT:    xxswapd vs8, vs8
+; CHECK-BE-NEXT:    lxv vs4, 112(r4)
+; CHECK-BE-NEXT:    lxv vs5, 0(r4)
+; CHECK-BE-NEXT:    lxv vs6, 16(r4)
+; CHECK-BE-NEXT:    lxv vs7, 32(r4)
+; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_0@toc@ha
+; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_0@toc@l
+; CHECK-BE-NEXT:    lxv vs1, 0(r4)
+; CHECK-BE-NEXT:    xscvdpsxws f8, f8
+; CHECK-BE-NEXT:    mffprwz r4, f9
+; CHECK-BE-NEXT:    mtfprwz f9, r4
+; CHECK-BE-NEXT:    mffprwz r4, f8
+; CHECK-BE-NEXT:    mtfprwz f8, r4
+; CHECK-BE-NEXT:    xxperm vs8, vs9, vs1
+; CHECK-BE-NEXT:    xscvdpsxws f9, f7
+; CHECK-BE-NEXT:    xxswapd vs7, vs7
+; CHECK-BE-NEXT:    xscvdpsxws f7, f7
+; CHECK-BE-NEXT:    mffprwz r4, f9
+; CHECK-BE-NEXT:    mtfprwz f9, r4
+; CHECK-BE-NEXT:    mffprwz r4, f7
+; CHECK-BE-NEXT:    mtfprwz f7, r4
+; CHECK-BE-NEXT:    xxperm vs7, vs9, vs1
+; CHECK-BE-NEXT:    xscvdpsxws f9, f6
+; CHECK-BE-NEXT:    xxswapd vs6, vs6
+; CHECK-BE-NEXT:    xscvdpsxws f6, f6
+; CHECK-BE-NEXT:    xxmrghw vs7, vs7, vs8
+; CHECK-BE-NEXT:    mffprwz r4, f9
+; CHECK-BE-NEXT:    mtfprwz f9, r4
+; CHECK-BE-NEXT:    mffprwz r4, f6
+; CHECK-BE-NEXT:    mtfprwz f6, r4
+; CHECK-BE-NEXT:    xxperm vs6, vs9, vs1
+; CHECK-BE-NEXT:    xscvdpsxws f9, f5
+; CHECK-BE-NEXT:    xxswapd vs5, vs5
+; CHECK-BE-NEXT:    xscvdpsxws f5, f5
+; CHECK-BE-NEXT:    mffprwz r4, f9
+; CHECK-BE-NEXT:    mtfprwz f9, r4
 ; CHECK-BE-NEXT:    mffprwz r4, f5
-; CHECK-BE-NEXT:    vperm v5, v5, v0, v2
-; CHECK-BE-NEXT:    xxmrghw vs6, v4, v3
-; CHECK-BE-NEXT:    mtvsrwz v3, r4
+; CHECK-BE-NEXT:    mtfprwz f5, r4
+; CHECK-BE-NEXT:    xxperm vs5, vs9, vs1
+; CHECK-BE-NEXT:    xscvdpsxws f9, f4
+; CHECK-BE-NEXT:    xxswapd vs4, vs4
+; CHECK-BE-NEXT:    xscvdpsxws f4, f4
+; CHECK-BE-NEXT:    xxmrghw vs5, vs5, vs6
+; CHECK-BE-NEXT:    xscvdpsxws f6, f3
+; CHECK-BE-NEXT:    xxswapd vs3, vs3
+; CHECK-BE-NEXT:    xscvdpsxws f3, f3
+; CHECK-BE-NEXT:    xxmrghd vs5, vs5, vs7
+; CHECK-BE-NEXT:    mffprwz r4, f9
+; CHECK-BE-NEXT:    mtfprwz f9, r4
 ; CHECK-BE-NEXT:    mffprwz r4, f4
-; CHECK-BE-NEXT:    mtvsrwz v4, r4
-; CHECK-BE-NEXT:    mffprwz r4, f7
-; CHECK-BE-NEXT:    vperm v3, v3, v4, v2
-; CHECK-BE-NEXT:    mtvsrwz v4, r4
+; CHECK-BE-NEXT:    mtfprwz f4, r4
+; CHECK-BE-NEXT:    mffprwz r4, f6
+; CHECK-BE-NEXT:    mtfprwz f6, r4
 ; CHECK-BE-NEXT:    mffprwz r4, f3
-; CHECK-BE-NEXT:    xscvdpsxws f3, f2
+; CHECK-BE-NEXT:    xxperm vs4, vs9, vs1
+; CHECK-BE-NEXT:    mtfprwz f3, r4
+; CHECK-BE-NEXT:    xxperm vs3, vs6, vs1
+; CHECK-BE-NEXT:    xxmrghw vs3, vs3, vs4
+; CHECK-BE-NEXT:    xscvdpsxws f4, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    xxmrghw vs4, v3, v5
-; CHECK-BE-NEXT:    mtvsrwz v3, r4
-; CHECK-BE-NEXT:    vperm v3, v4, v3, v2
-; CHECK-BE-NEXT:    xxmrghd vs4, vs4, vs6
-; CHECK-BE-NEXT:    mffprwz r4, f3
-; CHECK-BE-NEXT:    xscvdpsxws f3, f1
-; CHECK-BE-NEXT:    xxswapd vs1, vs1
-; CHECK-BE-NEXT:    mtvsrwz v4, r4
-; CHECK-BE-NEXT:    stxv vs4, 0(r3)
+; CHECK-BE-NEXT:    mffprwz r4, f4
+; CHECK-BE-NEXT:    mtfprwz f4, r4
 ; CHECK-BE-NEXT:    mffprwz r4, f2
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mtvsrwz v5, r4
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
-; CHECK-BE-NEXT:    mffprwz r4, f3
-; CHECK-BE-NEXT:    xxmrghw vs2, v4, v3
-; CHECK-BE-NEXT:    mtvsrwz v3, r4
-; CHECK-BE-NEXT:    mffprwz r4, f1
-; CHECK-BE-NEXT:    xscvdpsxws f1, f0
+; CHECK-BE-NEXT:    mtfprwz f2, r4
+; CHECK-BE-NEXT:    xxperm vs2, vs4, vs1
+; CHECK-BE-NEXT:    xscvdpsxws f4, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
-; CHECK-BE-NEXT:    mtvsrwz v4, r4
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vperm v3, v3, v4, v2
-; CHECK-BE-NEXT:    mffprwz r4, f1
-; CHECK-BE-NEXT:    mtvsrwz v4, r4
+; CHECK-BE-NEXT:    mffprwz r4, f4
+; CHECK-BE-NEXT:    mtfprwz f4, r4
 ; CHECK-BE-NEXT:    mffprwz r4, f0
-; CHECK-BE-NEXT:    mtvsrwz v5, r4
-; CHECK-BE-NEXT:    vperm v2, v4, v5, v2
-; CHECK-BE-NEXT:    xxmrghw vs0, v2, v3
-; CHECK-BE-NEXT:    xxmrghd vs0, vs0, vs2
+; CHECK-BE-NEXT:    mtfprwz f0, r4
+; CHECK-BE-NEXT:    xxperm vs0, vs4, vs1
+; CHECK-BE-NEXT:    stxv vs5, 0(r3)
+; CHECK-BE-NEXT:    xxmrghw vs0, vs0, vs2
+; CHECK-BE-NEXT:    xxmrghd vs0, vs0, vs3
 ; CHECK-BE-NEXT:    stxv vs0, 16(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <16 x double>, <16 x double>* %0, align 128
   %1 = fptoui <16 x double> %a to <16 x i16>
   store <16 x i16> %1, <16 x i16>* %agg.result, align 32
   ret void
 }

 ; CHECK-P9-NEXT:    mtvsrd v2, r3
 ; CHECK-P9-NEXT:    li r3, 0
 ; CHECK-P9-NEXT:    vmrghh v2, v3, v2
 ; CHECK-P9-NEXT:    vextuwrx r3, r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    xscvdpsxws f0, v2
+; CHECK-BE-NEXT:    xxswapd vs2, v2
+; CHECK-BE-NEXT:    xscvdpsxws f1, v2
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI4_0@toc@l
-; CHECK-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    xxswapd vs0, v2
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f0
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-BE-NEXT:    mffprwz r3, f1
+; CHECK-BE-NEXT:    mtfprwz f1, r3
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    li r3, 0
-; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
+; CHECK-BE-NEXT:    xxperm v2, vs1, vs0
 ; CHECK-BE-NEXT:    vextuwlx r3, r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = fptosi <2 x double> %a to <2 x i16>
   %1 = bitcast <2 x i16> %0 to i32
   ret i32 %1
 }
 

 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI5_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r3)
-; CHECK-BE-NEXT:    xscvdpsxws f2, f1
+; CHECK-BE-NEXT:    lxv vs2, 0(r3)
+; CHECK-BE-NEXT:    xscvdpsxws f3, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-NEXT:    mffprwz r3, f3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    xscvdpsxws f1, f0
+; CHECK-BE-NEXT:    mtfprwz f1, r3
+; CHECK-BE-NEXT:    xxperm vs1, vs3, vs2
+; CHECK-BE-NEXT:    xscvdpsxws f3, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vperm v3, v3, v4, v2
-; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mffprwz r3, f3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
-; CHECK-BE-NEXT:    vperm v2, v4, v5, v2
-; CHECK-BE-NEXT:    xxmrghw vs0, v2, v3
+; CHECK-BE-NEXT:    mtfprwz f0, r3
+; CHECK-BE-NEXT:    xxperm vs0, vs3, vs2
+; CHECK-BE-NEXT:    xxmrghw vs0, vs0, vs1
 ; CHECK-BE-NEXT:    mffprd r3, f0
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <4 x double>, <4 x double>* %0, align 32
   %1 = fptosi <4 x double> %a to <4 x i16>
   %2 = bitcast <4 x i16> %1 to i64
   ret i64 %2
 }

 ; CHECK-BE-LABEL: test8elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI6_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI6_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r3)
-; CHECK-BE-NEXT:    xscvdpsxws f4, f3
+; CHECK-BE-NEXT:    lxv vs4, 0(r3)
+; CHECK-BE-NEXT:    xscvdpsxws f5, f3
 ; CHECK-BE-NEXT:    xxswapd vs3, vs3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    mffprwz r3, f4
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-NEXT:    mffprwz r3, f5
+; CHECK-BE-NEXT:    mtfprwz f5, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f3
-; CHECK-BE-NEXT:    xscvdpsxws f3, f2
+; CHECK-BE-NEXT:    mtfprwz f3, r3
+; CHECK-BE-NEXT:    xxperm vs3, vs5, vs4
+; CHECK-BE-NEXT:    xscvdpsxws f5, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs2
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    vperm v3, v3, v4, v2
-; CHECK-BE-NEXT:    mffprwz r3, f3
+; CHECK-BE-NEXT:    mffprwz r3, f5
+; CHECK-BE-NEXT:    mtfprwz f5, r3
+; CHECK-BE-NEXT:    mffprwz r3, f2
+; CHECK-BE-NEXT:    mtfprwz f2, r3
+; CHECK-BE-NEXT:    xxperm vs2, vs5, vs4
+; CHECK-BE-NEXT:    xxmrghw vs2, vs2, vs3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
-; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f3
-; CHECK-BE-NEXT:    xxmrghw vs2, v4, v3
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    xscvdpsxws f1, f0
+; CHECK-BE-NEXT:    mtfprwz f1, r3
+; CHECK-BE-NEXT:    xxperm vs1, vs3, vs4
+; CHECK-BE-NEXT:    xscvdpsxws f3, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vperm v3, v3, v4, v2
-; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mffprwz r3, f3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
-; CHECK-BE-NEXT:    vperm v2, v4, v5, v2
-; CHECK-BE-NEXT:    xxmrghw vs0, v2, v3
+; CHECK-BE-NEXT:    mtfprwz f0, r3
+; CHECK-BE-NEXT:    xxperm vs0, vs3, vs4
+; CHECK-BE-NEXT:    xxmrghw vs0, vs0, vs1
 ; CHECK-BE-NEXT:    xxmrghd v2, vs0, vs2
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <8 x double>, <8 x double>* %0, align 64
   %1 = fptosi <8 x double> %a to <8 x i16>
   ret <8 x i16> %1
 }
 

 ; CHECK-P9-NEXT:    vmrghh v3, v3, v4
 ; CHECK-P9-NEXT:    xxmrglw vs0, v3, v2
 ; CHECK-P9-NEXT:    xxmrgld vs0, vs0, vs2
 ; CHECK-P9-NEXT:    stxv vs0, 16(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test16elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    lxv vs2, 48(r4)
-; CHECK-BE-NEXT:    lxv vs1, 32(r4)
-; CHECK-BE-NEXT:    lxv vs0, 16(r4)
-; CHECK-BE-NEXT:    addis r5, r2, .LCPI7_0@toc@ha
-; CHECK-BE-NEXT:    addi r5, r5, .LCPI7_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r5)
-; CHECK-BE-NEXT:    xscvdpsxws f3, f2
-; CHECK-BE-NEXT:    xscvdpsxws f4, f1
-; CHECK-BE-NEXT:    xxswapd vs2, vs2
-; CHECK-BE-NEXT:    xscvdpsxws f5, f0
-; CHECK-BE-NEXT:    xxswapd vs1, vs1
-; CHECK-BE-NEXT:    xxswapd vs0, vs0
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r5, f3
-; CHECK-BE-NEXT:    lxv vs3, 112(r4)
-; CHECK-BE-NEXT:    mtvsrwz v3, r5
-; CHECK-BE-NEXT:    mffprwz r5, f4
-; CHECK-BE-NEXT:    lxv vs4, 0(r4)
-; CHECK-BE-NEXT:    mtvsrwz v4, r5
-; CHECK-BE-NEXT:    mffprwz r5, f5
-; CHECK-BE-NEXT:    xscvdpsxws f7, f3
-; CHECK-BE-NEXT:    xxswapd vs3, vs3
-; CHECK-BE-NEXT:    mtvsrwz v5, r5
-; CHECK-BE-NEXT:    mffprwz r5, f2
-; CHECK-BE-NEXT:    lxv vs2, 96(r4)
-; CHECK-BE-NEXT:    xscvdpsxws f5, f4
-; CHECK-BE-NEXT:    xxswapd vs4, vs4
-; CHECK-BE-NEXT:    mtvsrwz v0, r5
-; CHECK-BE-NEXT:    mffprwz r5, f1
-; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    lxv vs1, 80(r4)
-; CHECK-BE-NEXT:    xscvdpsxws f4, f4
-; CHECK-BE-NEXT:    vperm v3, v3, v0, v2
-; CHECK-BE-NEXT:    mtvsrwz v0, r5
-; CHECK-BE-NEXT:    mffprwz r5, f0
+; CHECK-BE-NEXT:    lxv vs8, 48(r4)
 ; CHECK-BE-NEXT:    lxv vs0, 64(r4)
-; CHECK-BE-NEXT:    vperm v4, v4, v0, v2
-; CHECK-BE-NEXT:    mtvsrwz v0, r5
+; CHECK-BE-NEXT:    lxv vs2, 80(r4)
+; CHECK-BE-NEXT:    lxv vs3, 96(r4)
+; CHECK-BE-NEXT:    xscvdpsxws f9, f8
+; CHECK-BE-NEXT:    xxswapd vs8, vs8
+; CHECK-BE-NEXT:    lxv vs4, 112(r4)
+; CHECK-BE-NEXT:    lxv vs5, 0(r4)
+; CHECK-BE-NEXT:    lxv vs6, 16(r4)
+; CHECK-BE-NEXT:    lxv vs7, 32(r4)
+; CHECK-BE-NEXT:    addis r4, r2, .LCPI7_0@toc@ha
+; CHECK-BE-NEXT:    addi r4, r4, .LCPI7_0@toc@l
+; CHECK-BE-NEXT:    lxv vs1, 0(r4)
+; CHECK-BE-NEXT:    xscvdpsxws f8, f8
+; CHECK-BE-NEXT:    mffprwz r4, f9
+; CHECK-BE-NEXT:    mtfprwz f9, r4
+; CHECK-BE-NEXT:    mffprwz r4, f8
+; CHECK-BE-NEXT:    mtfprwz f8, r4
+; CHECK-BE-NEXT:    xxperm vs8, vs9, vs1
+; CHECK-BE-NEXT:    xscvdpsxws f9, f7
+; CHECK-BE-NEXT:    xxswapd vs7, vs7
+; CHECK-BE-NEXT:    xscvdpsxws f7, f7
+; CHECK-BE-NEXT:    mffprwz r4, f9
+; CHECK-BE-NEXT:    mtfprwz f9, r4
+; CHECK-BE-NEXT:    mffprwz r4, f7
+; CHECK-BE-NEXT:    mtfprwz f7, r4
+; CHECK-BE-NEXT:    xxperm vs7, vs9, vs1
+; CHECK-BE-NEXT:    xscvdpsxws f9, f6
+; CHECK-BE-NEXT:    xxswapd vs6, vs6
+; CHECK-BE-NEXT:    xscvdpsxws f6, f6
+; CHECK-BE-NEXT:    xxmrghw vs7, vs7, vs8
+; CHECK-BE-NEXT:    mffprwz r4, f9
+; CHECK-BE-NEXT:    mtfprwz f9, r4
+; CHECK-BE-NEXT:    mffprwz r4, f6
+; CHECK-BE-NEXT:    mtfprwz f6, r4
+; CHECK-BE-NEXT:    xxperm vs6, vs9, vs1
+; CHECK-BE-NEXT:    xscvdpsxws f9, f5
+; CHECK-BE-NEXT:    xxswapd vs5, vs5
+; CHECK-BE-NEXT:    xscvdpsxws f5, f5
+; CHECK-BE-NEXT:    mffprwz r4, f9
+; CHECK-BE-NEXT:    mtfprwz f9, r4
 ; CHECK-BE-NEXT:    mffprwz r4, f5
-; CHECK-BE-NEXT:    vperm v5, v5, v0, v2
-; CHECK-BE-NEXT:    xxmrghw vs6, v4, v3
-; CHECK-BE-NEXT:    mtvsrwz v3, r4
+; CHECK-BE-NEXT:    mtfprwz f5, r4
+; CHECK-BE-NEXT:    xxperm vs5, vs9, vs1
+; CHECK-BE-NEXT:    xscvdpsxws f9, f4
+; CHECK-BE-NEXT:    xxswapd vs4, vs4
+; CHECK-BE-NEXT:    xscvdpsxws f4, f4
+; CHECK-BE-NEXT:    xxmrghw vs5, vs5, vs6
+; CHECK-BE-NEXT:    xscvdpsxws f6, f3
+; CHECK-BE-NEXT:    xxswapd vs3, vs3
+; CHECK-BE-NEXT:    xscvdpsxws f3, f3
+; CHECK-BE-NEXT:    xxmrghd vs5, vs5, vs7
+; CHECK-BE-NEXT:    mffprwz r4, f9
+; CHECK-BE-NEXT:    mtfprwz f9, r4
 ; CHECK-BE-NEXT:    mffprwz r4, f4
-; CHECK-BE-NEXT:    mtvsrwz v4, r4
-; CHECK-BE-NEXT:    mffprwz r4, f7
-; CHECK-BE-NEXT:    vperm v3, v3, v4, v2
-; CHECK-BE-NEXT:    mtvsrwz v4, r4
+; CHECK-BE-NEXT:    mtfprwz f4, r4
+; CHECK-BE-NEXT:    mffprwz r4, f6
+; CHECK-BE-NEXT:    mtfprwz f6, r4
 ; CHECK-BE-NEXT:    mffprwz r4, f3
-; CHECK-BE-NEXT:    xscvdpsxws f3, f2
+; CHECK-BE-NEXT:    xxperm vs4, vs9, vs1
+; CHECK-BE-NEXT:    mtfprwz f3, r4
+; CHECK-BE-NEXT:    xxperm vs3, vs6, vs1
+; CHECK-BE-NEXT:    xxmrghw vs3, vs3, vs4
+; CHECK-BE-NEXT:    xscvdpsxws f4, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    xxmrghw vs4, v3, v5
-; CHECK-BE-NEXT:    mtvsrwz v3, r4
-; CHECK-BE-NEXT:    vperm v3, v4, v3, v2
-; CHECK-BE-NEXT:    xxmrghd vs4, vs4, vs6
-; CHECK-BE-NEXT:    mffprwz r4, f3
-; CHECK-BE-NEXT:    xscvdpsxws f3, f1
-; CHECK-BE-NEXT:    xxswapd vs1, vs1
-; CHECK-BE-NEXT:    mtvsrwz v4, r4
-; CHECK-BE-NEXT:    stxv vs4, 0(r3)
+; CHECK-BE-NEXT:    mffprwz r4, f4
+; CHECK-BE-NEXT:    mtfprwz f4, r4
 ; CHECK-BE-NEXT:    mffprwz r4, f2
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mtvsrwz v5, r4
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
-; CHECK-BE-NEXT:    mffprwz r4, f3
-; CHECK-BE-NEXT:    xxmrghw vs2, v4, v3
-; CHECK-BE-NEXT:    mtvsrwz v3, r4
-; CHECK-BE-NEXT:    mffprwz r4, f1
-; CHECK-BE-NEXT:    xscvdpsxws f1, f0
+; CHECK-BE-NEXT:    mtfprwz f2, r4
+; CHECK-BE-NEXT:    xxperm vs2, vs4, vs1
+; CHECK-BE-NEXT:    xscvdpsxws f4, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
-; CHECK-BE-NEXT:    mtvsrwz v4, r4
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vperm v3, v3, v4, v2
-; CHECK-BE-NEXT:    mffprwz r4, f1
-; CHECK-BE-NEXT:    mtvsrwz v4, r4
+; CHECK-BE-NEXT:    mffprwz r4, f4
+; CHECK-BE-NEXT:    mtfprwz f4, r4
 ; CHECK-BE-NEXT:    mffprwz r4, f0
-; CHECK-BE-NEXT:    mtvsrwz v5, r4
-; CHECK-BE-NEXT:    vperm v2, v4, v5, v2
-; CHECK-BE-NEXT:    xxmrghw vs0, v2, v3
-; CHECK-BE-NEXT:    xxmrghd vs0, vs0, vs2
+; CHECK-BE-NEXT:    mtfprwz f0, r4
+; CHECK-BE-NEXT:    xxperm vs0, vs4, vs1
+; CHECK-BE-NEXT:    stxv vs5, 0(r3)
+; CHECK-BE-NEXT:    xxmrghw vs0, vs0, vs2
+; CHECK-BE-NEXT:    xxmrghd vs0, vs0, vs3
 ; CHECK-BE-NEXT:    stxv vs0, 16(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <16 x double>, <16 x double>* %0, align 128
   %1 = fptosi <16 x double> %a to <16 x i16>
   store <16 x i16> %1, <16 x i16>* %agg.result, align 32
   ret void
 }

llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i8_elts.ll

 ; CHECK-P9-NEXT:    vmrghb v2, v3, v2
 ; CHECK-P9-NEXT:    vsldoi v2, v2, v2, 8
 ; CHECK-P9-NEXT:    stxsihx v2, 0, r3
 ; CHECK-P9-NEXT:    lhz r3, -2(r1)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    xscvdpsxws f0, v2
+; CHECK-BE-NEXT:    xxswapd vs2, v2
+; CHECK-BE-NEXT:    xscvdpsxws f1, v2
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI0_0@toc@l
-; CHECK-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    xxswapd vs0, v2
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f0
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-BE-NEXT:    mffprwz r3, f1
+; CHECK-BE-NEXT:    mtfprwz f1, r3
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    addi r3, r1, -2
-; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
+; CHECK-BE-NEXT:    xxperm v2, vs1, vs0
 ; CHECK-BE-NEXT:    vsldoi v2, v2, v2, 10
 ; CHECK-BE-NEXT:    stxsihx v2, 0, r3
 ; CHECK-BE-NEXT:    lhz r3, -2(r1)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = fptoui <2 x double> %a to <2 x i8>
   %1 = bitcast <2 x i8> %0 to i16
   ret i16 %1

 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI1_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r3)
-; CHECK-BE-NEXT:    xscvdpsxws f2, f1
+; CHECK-BE-NEXT:    lxv vs2, 0(r3)
+; CHECK-BE-NEXT:    xscvdpsxws f3, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-NEXT:    mffprwz r3, f3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vperm v3, v3, v4, v2
+; CHECK-BE-NEXT:    xxperm v2, vs3, vs2
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtfprwz f1, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    li r3, 0
-; CHECK-BE-NEXT:    vperm v2, v4, v5, v2
-; CHECK-BE-NEXT:    vmrghh v2, v2, v3
+; CHECK-BE-NEXT:    xxperm v3, vs1, vs2
+; CHECK-BE-NEXT:    vmrghh v2, v3, v2
 ; CHECK-BE-NEXT:    vextuwlx r3, r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <4 x double>, <4 x double>* %0, align 32
   %1 = fptoui <4 x double> %a to <4 x i8>
   %2 = bitcast <4 x i8> %1 to i32
   ret i32 %2
 }

 ; CHECK-BE-LABEL: test8elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI2_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r3)
-; CHECK-BE-NEXT:    xscvdpsxws f4, f3
+; CHECK-BE-NEXT:    lxv vs4, 0(r3)
+; CHECK-BE-NEXT:    xscvdpsxws f5, f3
 ; CHECK-BE-NEXT:    xxswapd vs3, vs3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    mffprwz r3, f4
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-NEXT:    mffprwz r3, f5
+; CHECK-BE-NEXT:    mtfprwz f5, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs2
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    vperm v3, v3, v4, v2
+; CHECK-BE-NEXT:    xxperm v2, vs5, vs4
 ; CHECK-BE-NEXT:    mffprwz r3, f3
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xxperm v3, vs3, vs4
 ; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    vmrghh v3, v4, v3
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    vmrghh v2, v3, v2
+; CHECK-BE-NEXT:    mtfprwz f2, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xxperm v3, vs2, vs4
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtfprwz f1, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    mtvsrwz v0, r3
-; CHECK-BE-NEXT:    vperm v2, v5, v0, v2
-; CHECK-BE-NEXT:    vmrghh v2, v2, v4
-; CHECK-BE-NEXT:    xxmrghw vs0, v2, v3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    xxperm v4, vs1, vs4
+; CHECK-BE-NEXT:    vmrghh v3, v4, v3
+; CHECK-BE-NEXT:    xxmrghw vs0, v3, v2
 ; CHECK-BE-NEXT:    mffprd r3, f0
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <8 x double>, <8 x double>* %0, align 64
   %1 = fptoui <8 x double> %a to <8 x i8>
   %2 = bitcast <8 x i8> %1 to i64
   ret i64 %2
 }

 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test16elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs7, 112(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs2, 32(r3)
-; CHECK-BE-NEXT:    xscvdpsxws f8, f7
+; CHECK-BE-NEXT:    xscvdpsxws f9, f7
 ; CHECK-BE-NEXT:    xxswapd vs7, vs7
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    lxv vs4, 64(r3)
 ; CHECK-BE-NEXT:    lxv vs5, 80(r3)
 ; CHECK-BE-NEXT:    lxv vs6, 96(r3)
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI3_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r3)
+; CHECK-BE-NEXT:    lxv vs8, 0(r3)
 ; CHECK-BE-NEXT:    xscvdpsxws f7, f7
-; CHECK-BE-NEXT:    mffprwz r3, f8
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-NEXT:    mffprwz r3, f9
+; CHECK-BE-NEXT:    mtfprwz f9, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f7
 ; CHECK-BE-NEXT:    xscvdpsxws f7, f6
 ; CHECK-BE-NEXT:    xxswapd vs6, vs6
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f6, f6
-; CHECK-BE-NEXT:    vperm v3, v3, v4, v2
+; CHECK-BE-NEXT:    xxperm v2, vs9, vs8
 ; CHECK-BE-NEXT:    mffprwz r3, f7
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtfprwz f7, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f6
 ; CHECK-BE-NEXT:    xscvdpsxws f6, f5
 ; CHECK-BE-NEXT:    xxswapd vs5, vs5
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f5, f5
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xxperm v3, vs7, vs8
 ; CHECK-BE-NEXT:    mffprwz r3, f6
-; CHECK-BE-NEXT:    vmrghh v3, v4, v3
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    vmrghh v2, v3, v2
+; CHECK-BE-NEXT:    mtfprwz f6, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f5
 ; CHECK-BE-NEXT:    xscvdpsxws f5, f4
 ; CHECK-BE-NEXT:    xxswapd vs4, vs4
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f4, f4
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xxperm v3, vs6, vs8
 ; CHECK-BE-NEXT:    mffprwz r3, f5
+; CHECK-BE-NEXT:    mtfprwz f5, r3
+; CHECK-BE-NEXT:    mffprwz r3, f4
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    xxperm v4, vs5, vs8
 ; CHECK-BE-NEXT:    xscvdpsxws f5, f3
 ; CHECK-BE-NEXT:    xxswapd vs3, vs3
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
-; CHECK-BE-NEXT:    mffprwz r3, f4
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    mtvsrwz v0, r3
-; CHECK-BE-NEXT:    vperm v5, v5, v0, v2
+; CHECK-BE-NEXT:    vmrghh v3, v4, v3
+; CHECK-BE-NEXT:    xxmrghw vs4, v3, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f5
-; CHECK-BE-NEXT:    vmrghh v4, v5, v4
-; CHECK-BE-NEXT:    xxmrghw vs4, v4, v3
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-NEXT:    mtfprwz f5, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs2
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    vperm v3, v3, v4, v2
+; CHECK-BE-NEXT:    xxperm v2, vs5, vs8
 ; CHECK-BE-NEXT:    mffprwz r3, f3
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xxperm v3, vs3, vs8
 ; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    vmrghh v3, v4, v3
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    vmrghh v2, v3, v2
+; CHECK-BE-NEXT:    mtfprwz f2, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xxperm v3, vs2, vs8
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtfprwz f1, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    mtvsrwz v0, r3
-; CHECK-BE-NEXT:    vperm v2, v5, v0, v2
-; CHECK-BE-NEXT:    vmrghh v2, v2, v4
-; CHECK-BE-NEXT:    xxmrghw vs0, v2, v3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    xxperm v4, vs1, vs8
+; CHECK-BE-NEXT:    vmrghh v3, v4, v3
+; CHECK-BE-NEXT:    xxmrghw vs0, v3, v2
 ; CHECK-BE-NEXT:    xxmrghd v2, vs0, vs4
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <16 x double>, <16 x double>* %0, align 128
   %1 = fptoui <16 x double> %a to <16 x i8>
   ret <16 x i8> %1
 }
 

 ; CHECK-P9-NEXT:    vmrghb v2, v3, v2
 ; CHECK-P9-NEXT:    vsldoi v2, v2, v2, 8
 ; CHECK-P9-NEXT:    stxsihx v2, 0, r3
 ; CHECK-P9-NEXT:    lhz r3, -2(r1)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    xscvdpsxws f0, v2
+; CHECK-BE-NEXT:    xxswapd vs2, v2
+; CHECK-BE-NEXT:    xscvdpsxws f1, v2
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI4_0@toc@l
-; CHECK-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    xxswapd vs0, v2
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f0
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-BE-NEXT:    mffprwz r3, f1
+; CHECK-BE-NEXT:    mtfprwz f1, r3
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    addi r3, r1, -2
-; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
+; CHECK-BE-NEXT:    xxperm v2, vs1, vs0
 ; CHECK-BE-NEXT:    vsldoi v2, v2, v2, 10
 ; CHECK-BE-NEXT:    stxsihx v2, 0, r3
 ; CHECK-BE-NEXT:    lhz r3, -2(r1)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = fptosi <2 x double> %a to <2 x i8>
   %1 = bitcast <2 x i8> %0 to i16
   ret i16 %1

 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI5_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r3)
-; CHECK-BE-NEXT:    xscvdpsxws f2, f1
+; CHECK-BE-NEXT:    lxv vs2, 0(r3)
+; CHECK-BE-NEXT:    xscvdpsxws f3, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-NEXT:    mffprwz r3, f3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vperm v3, v3, v4, v2
+; CHECK-BE-NEXT:    xxperm v2, vs3, vs2
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtfprwz f1, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    li r3, 0
-; CHECK-BE-NEXT:    vperm v2, v4, v5, v2
-; CHECK-BE-NEXT:    vmrghh v2, v2, v3
+; CHECK-BE-NEXT:    xxperm v3, vs1, vs2
+; CHECK-BE-NEXT:    vmrghh v2, v3, v2
 ; CHECK-BE-NEXT:    vextuwlx r3, r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <4 x double>, <4 x double>* %0, align 32
   %1 = fptosi <4 x double> %a to <4 x i8>
   %2 = bitcast <4 x i8> %1 to i32
   ret i32 %2
 }

 ; CHECK-BE-LABEL: test8elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI6_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI6_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r3)
-; CHECK-BE-NEXT:    xscvdpsxws f4, f3
+; CHECK-BE-NEXT:    lxv vs4, 0(r3)
+; CHECK-BE-NEXT:    xscvdpsxws f5, f3
 ; CHECK-BE-NEXT:    xxswapd vs3, vs3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    mffprwz r3, f4
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-NEXT:    mffprwz r3, f5
+; CHECK-BE-NEXT:    mtfprwz f5, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs2
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    vperm v3, v3, v4, v2
+; CHECK-BE-NEXT:    xxperm v2, vs5, vs4
 ; CHECK-BE-NEXT:    mffprwz r3, f3
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xxperm v3, vs3, vs4
 ; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    vmrghh v3, v4, v3
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    vmrghh v2, v3, v2
+; CHECK-BE-NEXT:    mtfprwz f2, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xxperm v3, vs2, vs4
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtfprwz f1, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    mtvsrwz v0, r3
-; CHECK-BE-NEXT:    vperm v2, v5, v0, v2
-; CHECK-BE-NEXT:    vmrghh v2, v2, v4
-; CHECK-BE-NEXT:    xxmrghw vs0, v2, v3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    xxperm v4, vs1, vs4
+; CHECK-BE-NEXT:    vmrghh v3, v4, v3
+; CHECK-BE-NEXT:    xxmrghw vs0, v3, v2
 ; CHECK-BE-NEXT:    mffprd r3, f0
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <8 x double>, <8 x double>* %0, align 64
   %1 = fptosi <8 x double> %a to <8 x i8>
   %2 = bitcast <8 x i8> %1 to i64
   ret i64 %2
 }

 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test16elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs7, 112(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs2, 32(r3)
-; CHECK-BE-NEXT:    xscvdpsxws f8, f7
+; CHECK-BE-NEXT:    xscvdpsxws f9, f7
 ; CHECK-BE-NEXT:    xxswapd vs7, vs7
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    lxv vs4, 64(r3)
 ; CHECK-BE-NEXT:    lxv vs5, 80(r3)
 ; CHECK-BE-NEXT:    lxv vs6, 96(r3)
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI7_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI7_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r3)
+; CHECK-BE-NEXT:    lxv vs8, 0(r3)
 ; CHECK-BE-NEXT:    xscvdpsxws f7, f7
-; CHECK-BE-NEXT:    mffprwz r3, f8
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-NEXT:    mffprwz r3, f9
+; CHECK-BE-NEXT:    mtfprwz f9, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f7
 ; CHECK-BE-NEXT:    xscvdpsxws f7, f6
 ; CHECK-BE-NEXT:    xxswapd vs6, vs6
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f6, f6
-; CHECK-BE-NEXT:    vperm v3, v3, v4, v2
+; CHECK-BE-NEXT:    xxperm v2, vs9, vs8
 ; CHECK-BE-NEXT:    mffprwz r3, f7
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtfprwz f7, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f6
 ; CHECK-BE-NEXT:    xscvdpsxws f6, f5
 ; CHECK-BE-NEXT:    xxswapd vs5, vs5
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f5, f5
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xxperm v3, vs7, vs8
 ; CHECK-BE-NEXT:    mffprwz r3, f6
-; CHECK-BE-NEXT:    vmrghh v3, v4, v3
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    vmrghh v2, v3, v2
+; CHECK-BE-NEXT:    mtfprwz f6, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f5
 ; CHECK-BE-NEXT:    xscvdpsxws f5, f4
 ; CHECK-BE-NEXT:    xxswapd vs4, vs4
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f4, f4
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xxperm v3, vs6, vs8
 ; CHECK-BE-NEXT:    mffprwz r3, f5
+; CHECK-BE-NEXT:    mtfprwz f5, r3
+; CHECK-BE-NEXT:    mffprwz r3, f4
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    xxperm v4, vs5, vs8
 ; CHECK-BE-NEXT:    xscvdpsxws f5, f3
 ; CHECK-BE-NEXT:    xxswapd vs3, vs3
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
-; CHECK-BE-NEXT:    mffprwz r3, f4
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    mtvsrwz v0, r3
-; CHECK-BE-NEXT:    vperm v5, v5, v0, v2
+; CHECK-BE-NEXT:    vmrghh v3, v4, v3
+; CHECK-BE-NEXT:    xxmrghw vs4, v3, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f5
-; CHECK-BE-NEXT:    vmrghh v4, v5, v4
-; CHECK-BE-NEXT:    xxmrghw vs4, v4, v3
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-NEXT:    mtfprwz f5, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs2
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    vperm v3, v3, v4, v2
+; CHECK-BE-NEXT:    xxperm v2, vs5, vs8
 ; CHECK-BE-NEXT:    mffprwz r3, f3
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xxperm v3, vs3, vs8
 ; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    vmrghh v3, v4, v3
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    vmrghh v2, v3, v2
+; CHECK-BE-NEXT:    mtfprwz f2, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xxperm v3, vs2, vs8
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtfprwz f1, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    mtvsrwz v0, r3
-; CHECK-BE-NEXT:    vperm v2, v5, v0, v2
-; CHECK-BE-NEXT:    vmrghh v2, v2, v4
-; CHECK-BE-NEXT:    xxmrghw vs0, v2, v3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    xxperm v4, vs1, vs8
+; CHECK-BE-NEXT:    vmrghh v3, v4, v3
+; CHECK-BE-NEXT:    xxmrghw vs0, v3, v2
 ; CHECK-BE-NEXT:    xxmrghd v2, vs0, vs4
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <16 x double>, <16 x double>* %0, align 128
   %1 = fptosi <16 x double> %a to <16 x i8>
   ret <16 x i8> %1
 }

llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll

 ; CHECK-P9-NEXT:    mtvsrd v2, r3
 ; CHECK-P9-NEXT:    xxlxor v3, v3, v3
 ; CHECK-P9-NEXT:    vmrghh v2, v3, v2
 ; CHECK-P9-NEXT:    xvcvuxwsp v2, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    mtvsrd v2, r3
+; CHECK-BE-NEXT:    mtfprd f1, r3
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
-; CHECK-BE-NEXT:    xxlxor v4, v4, v4
+; CHECK-BE-NEXT:    xxlxor vs0, vs0, vs0
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI1_0@toc@l
-; CHECK-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
-; CHECK-BE-NEXT:    xvcvuxwsp v2, v2
+; CHECK-BE-NEXT:    lxv vs2, 0(r3)
+; CHECK-BE-NEXT:    xxperm vs1, vs0, vs2
+; CHECK-BE-NEXT:    xvcvuxwsp v2, vs1
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i64 %a.coerce to <4 x i16>
   %1 = uitofp <4 x i16> %0 to <4 x float>
   ret <4 x float> %1
 }
 
 define void @test8elt(<8 x float>* noalias nocapture sret(<8 x float>) %agg.result, <8 x i16> %a) local_unnamed_addr #2 {

llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll

 ; CHECK-P8-NEXT:    lxvd2x vs0, 0, r4
 ; CHECK-P8-NEXT:    xxswapd v3, vs0
 ; CHECK-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-P8-NEXT:    xvcvuxddp v2, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    mtvsrwz v2, r3
+; CHECK-P9-NEXT:    mtfprwz f1, r3
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
-; CHECK-P9-NEXT:    xxlxor v4, v4, v4
+; CHECK-P9-NEXT:    xxlxor vs0, vs0, vs0
 ; CHECK-P9-NEXT:    addi r3, r3, .LCPI0_0@toc@l
-; CHECK-P9-NEXT:    lxv v3, 0(r3)
-; CHECK-P9-NEXT:    vperm v2, v4, v2, v3
-; CHECK-P9-NEXT:    xvcvuxddp v2, v2
+; CHECK-P9-NEXT:    lxv vs2, 0(r3)
+; CHECK-P9-NEXT:    xxperm vs1, vs0, vs2
+; CHECK-P9-NEXT:    xvcvuxddp v2, vs1
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    mtvsrwz v2, r3
+; CHECK-BE-NEXT:    mtfprwz f1, r3
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
-; CHECK-BE-NEXT:    xxlxor v4, v4, v4
+; CHECK-BE-NEXT:    xxlxor vs0, vs0, vs0
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI0_0@toc@l
-; CHECK-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
-; CHECK-BE-NEXT:    xvcvuxddp v2, v2
+; CHECK-BE-NEXT:    lxv vs2, 0(r3)
+; CHECK-BE-NEXT:    xxperm vs1, vs0, vs2
+; CHECK-BE-NEXT:    xvcvuxddp v2, vs1
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i32 %a.coerce to <2 x i16>
   %1 = uitofp <2 x i16> %0 to <2 x double>
   ret <2 x double> %1
 }
 
 define void @test4elt(<4 x double>* noalias nocapture sret(<4 x double>) %agg.result, i64 %a.coerce) local_unnamed_addr #1 {

 ; CHECK-P8-NEXT:    xvcvsxddp v2, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    mtvsrwz v2, r3
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
 ; CHECK-P9-NEXT:    addi r3, r3, .LCPI4_0@toc@l
-; CHECK-P9-NEXT:    lxv v3, 0(r3)
-; CHECK-P9-NEXT:    vperm v2, v2, v2, v3
+; CHECK-P9-NEXT:    lxv vs0, 0(r3)
+; CHECK-P9-NEXT:    xxperm v2, v2, vs0
 ; CHECK-P9-NEXT:    vextsh2d v2, v2
 ; CHECK-P9-NEXT:    xvcvsxddp v2, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI4_0@toc@l
-; CHECK-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-BE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-BE-NEXT:    xxperm v2, v2, vs0
 ; CHECK-BE-NEXT:    vextsh2d v2, v2
 ; CHECK-BE-NEXT:    xvcvsxddp v2, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i32 %a.coerce to <2 x i16>
   %1 = sitofp <2 x i16> %0 to <2 x double>
   ret <2 x double> %1
 }

llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll

 ; CHECK-P8-NEXT:    lxvd2x vs0, 0, r4
 ; CHECK-P8-NEXT:    xxswapd v3, vs0
 ; CHECK-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-P8-NEXT:    xvcvuxwsp v2, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test4elt:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    mtvsrwz v2, r3
+; CHECK-P9-NEXT:    mtfprwz f1, r3
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
-; CHECK-P9-NEXT:    xxlxor v4, v4, v4
+; CHECK-P9-NEXT:    xxlxor vs0, vs0, vs0
 ; CHECK-P9-NEXT:    addi r3, r3, .LCPI1_0@toc@l
-; CHECK-P9-NEXT:    lxv v3, 0(r3)
-; CHECK-P9-NEXT:    vperm v2, v4, v2, v3
-; CHECK-P9-NEXT:    xvcvuxwsp v2, v2
+; CHECK-P9-NEXT:    lxv vs2, 0(r3)
+; CHECK-P9-NEXT:    xxperm vs1, vs0, vs2
+; CHECK-P9-NEXT:    xvcvuxwsp v2, vs1
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    mtvsrwz v2, r3
+; CHECK-BE-NEXT:    mtfprwz f1, r3
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
-; CHECK-BE-NEXT:    xxlxor v4, v4, v4
+; CHECK-BE-NEXT:    xxlxor vs0, vs0, vs0
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI1_0@toc@l
-; CHECK-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
-; CHECK-BE-NEXT:    xvcvuxwsp v2, v2
+; CHECK-BE-NEXT:    lxv vs2, 0(r3)
+; CHECK-BE-NEXT:    xxperm vs1, vs0, vs2
+; CHECK-BE-NEXT:    xvcvuxwsp v2, vs1
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i32 %a.coerce to <4 x i8>
   %1 = uitofp <4 x i8> %0 to <4 x float>
   ret <4 x float> %1
 }
 
 define void @test8elt(<8 x float>* noalias nocapture sret(<8 x float>) %agg.result, i64 %a.coerce) local_unnamed_addr #2 {

 ; CHECK-P8-NEXT:    xvcvsxwsp v2, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test4elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    mtvsrwz v2, r3
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
 ; CHECK-P9-NEXT:    addi r3, r3, .LCPI5_0@toc@l
-; CHECK-P9-NEXT:    lxv v3, 0(r3)
-; CHECK-P9-NEXT:    vperm v2, v2, v2, v3
+; CHECK-P9-NEXT:    lxv vs0, 0(r3)
+; CHECK-P9-NEXT:    xxperm v2, v2, vs0
 ; CHECK-P9-NEXT:    vextsb2w v2, v2
 ; CHECK-P9-NEXT:    xvcvsxwsp v2, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI5_0@toc@l
-; CHECK-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-BE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-BE-NEXT:    xxperm v2, v2, vs0
 ; CHECK-BE-NEXT:    vextsb2w v2, v2
 ; CHECK-BE-NEXT:    xvcvsxwsp v2, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i32 %a.coerce to <4 x i8>
   %1 = sitofp <4 x i8> %0 to <4 x float>
   ret <4 x float> %1
 }

llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll

 ; CHECK-P8-NEXT:    lxvd2x vs0, 0, r4
 ; CHECK-P8-NEXT:    xxswapd v3, vs0
 ; CHECK-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-P8-NEXT:    xvcvuxddp v2, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    mtvsrwz v2, r3
+; CHECK-P9-NEXT:    mtfprwz f1, r3
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
-; CHECK-P9-NEXT:    xxlxor v4, v4, v4
+; CHECK-P9-NEXT:    xxlxor vs0, vs0, vs0
 ; CHECK-P9-NEXT:    addi r3, r3, .LCPI0_0@toc@l
-; CHECK-P9-NEXT:    lxv v3, 0(r3)
-; CHECK-P9-NEXT:    vperm v2, v4, v2, v3
-; CHECK-P9-NEXT:    xvcvuxddp v2, v2
+; CHECK-P9-NEXT:    lxv vs2, 0(r3)
+; CHECK-P9-NEXT:    xxperm vs1, vs0, vs2
+; CHECK-P9-NEXT:    xvcvuxddp v2, vs1
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    mtvsrwz v2, r3
+; CHECK-BE-NEXT:    mtfprwz f1, r3
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
-; CHECK-BE-NEXT:    xxlxor v4, v4, v4
+; CHECK-BE-NEXT:    xxlxor vs0, vs0, vs0
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI0_0@toc@l
-; CHECK-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
-; CHECK-BE-NEXT:    xvcvuxddp v2, v2
+; CHECK-BE-NEXT:    lxv vs2, 0(r3)
+; CHECK-BE-NEXT:    xxperm vs1, vs0, vs2
+; CHECK-BE-NEXT:    xvcvuxddp v2, vs1
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i16 %a.coerce to <2 x i8>
   %1 = uitofp <2 x i8> %0 to <2 x double>
   ret <2 x double> %1
 }
 
 define void @test4elt(<4 x double>* noalias nocapture sret(<4 x double>) %agg.result, i32 %a.coerce) local_unnamed_addr #1 {

 ; CHECK-P8-NEXT:    xvcvsxddp v2, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    mtvsrwz v2, r3
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
 ; CHECK-P9-NEXT:    addi r3, r3, .LCPI4_0@toc@l
-; CHECK-P9-NEXT:    lxv v3, 0(r3)
-; CHECK-P9-NEXT:    vperm v2, v2, v2, v3
+; CHECK-P9-NEXT:    lxv vs0, 0(r3)
+; CHECK-P9-NEXT:    xxperm v2, v2, vs0
 ; CHECK-P9-NEXT:    vextsb2d v2, v2
 ; CHECK-P9-NEXT:    xvcvsxddp v2, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI4_0@toc@l
-; CHECK-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-BE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-BE-NEXT:    xxperm v2, v2, vs0
 ; CHECK-BE-NEXT:    vextsb2d v2, v2
 ; CHECK-BE-NEXT:    xvcvsxddp v2, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i16 %a.coerce to <2 x i8>
   %1 = sitofp <2 x i8> %0 to <2 x double>
   ret <2 x double> %1
 }

llvm/test/CodeGen/PowerPC/vec_extract_p9.ll

entry:
   ret i32 %vecext
 }
 
 define double @test10(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LE-LABEL: test10:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    addis 3, 2, .LCPI9_0@toc@ha
 ; CHECK-LE-NEXT:    addi 3, 3, .LCPI9_0@toc@l
-; CHECK-LE-NEXT:    lxv 36, 0(3)
+; CHECK-LE-NEXT:    lxv 0, 0(3)
 ; CHECK-LE-NEXT:    addis 3, 2, .LCPI9_1@toc@ha
 ; CHECK-LE-NEXT:    lfs 1, .LCPI9_1@toc@l(3)
-; CHECK-LE-NEXT:    vperm 2, 2, 3, 4
-; CHECK-LE-NEXT:    xxswapd 0, 34
+; CHECK-LE-NEXT:    xxperm 35, 34, 0
+; CHECK-LE-NEXT:    xxswapd 0, 35
 ; CHECK-LE-NEXT:    xsadddp 1, 0, 1
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test10:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI9_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI9_0@toc@l
-; CHECK-BE-NEXT:    lxv 36, 0(3)
+; CHECK-BE-NEXT:    lxv 0, 0(3)
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI9_1@toc@ha
+; CHECK-BE-NEXT:    xxperm 34, 35, 0
 ; CHECK-BE-NEXT:    lfs 0, .LCPI9_1@toc@l(3)
-; CHECK-BE-NEXT:    vperm 2, 3, 2, 4
 ; CHECK-BE-NEXT:    xsadddp 1, 34, 0
 ; CHECK-BE-NEXT:    blr
 entry:
   %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 5, i32 2, i32 3, i32 7>
   %cast = bitcast <4 x i32> %shuffle to <2 x double>
   %extract = extractelement <2 x double> %cast, i32 0
   %add = fadd double %extract, 1.0000
   ret double %add
 }

llvm/test/CodeGen/PowerPC/vec_int_ext.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-LE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-BE
 
 define <4 x i32> @vextsb2wLE(<16 x i8> %a) {
 ; CHECK-LE-LABEL: vextsb2wLE:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    vextsb2w 2, 2
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: vextsb2wLE:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI0_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 0, 0(3)
+; CHECK-BE-NEXT:    xxperm 34, 34, 0
 ; CHECK-BE-NEXT:    vextsb2w 2, 2
 ; CHECK-BE-NEXT:    blr
 
 entry:
   %vecext = extractelement <16 x i8> %a, i32 0
   %conv = sext i8 %vecext to i32
   %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
   %vecext1 = extractelement <16 x i8> %a, i32 4

 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    vextsb2d 2, 2
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: vextsb2dLE:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI1_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI1_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 0, 0(3)
+; CHECK-BE-NEXT:    xxperm 34, 34, 0
 ; CHECK-BE-NEXT:    vextsb2d 2, 2
 ; CHECK-BE-NEXT:    blr
 
 entry:
   %vecext = extractelement <16 x i8> %a, i32 0
   %conv = sext i8 %vecext to i64
   %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
   %vecext1 = extractelement <16 x i8> %a, i32 8
   %conv2 = sext i8 %vecext1 to i64
   %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
   ret <2 x i64> %vecinit3
 }
 
 define <4 x i32> @vextsh2wLE(<8 x i16> %a) {
 ; CHECK-LE-LABEL: vextsh2wLE:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    vextsh2w 2, 2
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: vextsh2wLE:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI2_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI2_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 0, 0(3)
+; CHECK-BE-NEXT:    xxperm 34, 34, 0
 ; CHECK-BE-NEXT:    vextsh2w 2, 2
 ; CHECK-BE-NEXT:    blr
 
 entry:
   %vecext = extractelement <8 x i16> %a, i32 0
   %conv = sext i16 %vecext to i32
   %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
   %vecext1 = extractelement <8 x i16> %a, i32 2

 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    vextsh2d 2, 2
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: vextsh2dLE:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI3_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 0, 0(3)
+; CHECK-BE-NEXT:    xxperm 34, 34, 0
 ; CHECK-BE-NEXT:    vextsh2d 2, 2
 ; CHECK-BE-NEXT:    blr
 
 entry:
   %vecext = extractelement <8 x i16> %a, i32 0
   %conv = sext i16 %vecext to i64
   %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
   %vecext1 = extractelement <8 x i16> %a, i32 4

 ; CHECK-BE-NEXT:    li 9, 12
 ; CHECK-BE-NEXT:    li 10, 14
 ; CHECK-BE-NEXT:    li 7, 8
 ; CHECK-BE-NEXT:    li 8, 10
 ; CHECK-BE-NEXT:    vextublx 9, 9, 2
 ; CHECK-BE-NEXT:    vextublx 10, 10, 2
 ; CHECK-BE-NEXT:    vextublx 7, 7, 2
 ; CHECK-BE-NEXT:    vextublx 8, 8, 2
-; CHECK-BE-NEXT:    li 3, 0
-; CHECK-BE-NEXT:    li 4, 2
 ; CHECK-BE-NEXT:    li 5, 4
 ; CHECK-BE-NEXT:    li 6, 6
+; CHECK-BE-NEXT:    li 3, 0
+; CHECK-BE-NEXT:    li 4, 2
 ; CHECK-BE-NEXT:    extsb 9, 9
 ; CHECK-BE-NEXT:    extsb 10, 10
-; CHECK-BE-NEXT:    vextublx 3, 3, 2
-; CHECK-BE-NEXT:    vextublx 4, 4, 2
-; CHECK-BE-NEXT:    vextublx 5, 5, 2
 ; CHECK-BE-NEXT:    extsb 7, 7
 ; CHECK-BE-NEXT:    extsb 8, 8
-; CHECK-BE-NEXT:    extsb 5, 5
-; CHECK-BE-NEXT:    extsb 3, 3
-; CHECK-BE-NEXT:    extsb 4, 4
-; CHECK-BE-NEXT:    mtvsrwz 35, 9
-; CHECK-BE-NEXT:    addis 9, 2, .LCPI11_0@toc@ha
+; CHECK-BE-NEXT:    vextublx 5, 5, 2
 ; CHECK-BE-NEXT:    vextublx 6, 6, 2
-; CHECK-BE-NEXT:    mtvsrwz 34, 10
-; CHECK-BE-NEXT:    mtvsrwz 37, 7
+; CHECK-BE-NEXT:    extsb 5, 5
 ; CHECK-BE-NEXT:    extsb 6, 6
+; CHECK-BE-NEXT:    mtfprwz 1, 9
+; CHECK-BE-NEXT:    addis 9, 2, .LCPI11_0@toc@ha
+; CHECK-BE-NEXT:    mtfprwz 0, 10
+; CHECK-BE-NEXT:    mtfprwz 3, 7
+; CHECK-BE-NEXT:    vextublx 3, 3, 2
+; CHECK-BE-NEXT:    extsb 3, 3
+; CHECK-BE-NEXT:    mtfprwz 4, 3
 ; CHECK-BE-NEXT:    addi 9, 9, .LCPI11_0@toc@l
-; CHECK-BE-NEXT:    lxv 36, 0(9)
-; CHECK-BE-NEXT:    vperm 2, 3, 2, 4
-; CHECK-BE-NEXT:    mtvsrwz 35, 8
-; CHECK-BE-NEXT:    vperm 3, 5, 3, 4
-; CHECK-BE-NEXT:    mtvsrwz 37, 3
-; CHECK-BE-NEXT:    xxmrghw 0, 35, 34
-; CHECK-BE-NEXT:    mtvsrwz 34, 6
-; CHECK-BE-NEXT:    mtvsrwz 35, 5
-; CHECK-BE-NEXT:    vperm 2, 3, 2, 4
-; CHECK-BE-NEXT:    mtvsrwz 35, 4
-; CHECK-BE-NEXT:    vperm 3, 5, 3, 4
-; CHECK-BE-NEXT:    xxmrghw 1, 35, 34
+; CHECK-BE-NEXT:    vextublx 4, 4, 2
+; CHECK-BE-NEXT:    extsb 4, 4
+; CHECK-BE-NEXT:    lxv 2, 0(9)
+; CHECK-BE-NEXT:    xxperm 0, 1, 2
+; CHECK-BE-NEXT:    mtfprwz 1, 8
+; CHECK-BE-NEXT:    xxperm 1, 3, 2
+; CHECK-BE-NEXT:    mtfprwz 3, 5
+; CHECK-BE-NEXT:    xxmrghw 0, 1, 0
+; CHECK-BE-NEXT:    mtfprwz 1, 6
+; CHECK-BE-NEXT:    xxperm 1, 3, 2
+; CHECK-BE-NEXT:    mtfprwz 3, 4
+; CHECK-BE-NEXT:    xxperm 3, 4, 2
+; CHECK-BE-NEXT:    xxmrghw 1, 3, 1
 ; CHECK-BE-NEXT:    xxmrghd 34, 1, 0
 ; CHECK-BE-NEXT:    blr
 entry:
 
 
   %vecext = extractelement <16 x i8> %a, i32 0
   %conv = sext i8 %vecext to i16
   %vecinit = insertelement <8 x i16> undef, i16 %conv, i32 0

llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll

 ; PC64LE9-NEXT:    addis 3, 2, .LCPI2_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI2_0@toc@l
 ; PC64LE9-NEXT:    xxswapd 2, 34
 ; PC64LE9-NEXT:    xxsldwi 3, 34, 34, 3
 ; PC64LE9-NEXT:    xscvspdpn 0, 0
 ; PC64LE9-NEXT:    xscvspdpn 1, 1
 ; PC64LE9-NEXT:    xscvspdpn 2, 2
 ; PC64LE9-NEXT:    xscvspdpn 3, 3
-; PC64LE9-NEXT:    lxv 36, 0(3)
 ; PC64LE9-NEXT:    xsdivsp 0, 1, 0
 ; PC64LE9-NEXT:    xxswapd 1, 35
 ; PC64LE9-NEXT:    xscvspdpn 1, 1
 ; PC64LE9-NEXT:    xsdivsp 1, 2, 1
 ; PC64LE9-NEXT:    xxsldwi 2, 35, 35, 3
 ; PC64LE9-NEXT:    xscvspdpn 2, 2
 ; PC64LE9-NEXT:    xsdivsp 2, 3, 2
-; PC64LE9-NEXT:    xscvdpspn 35, 0
+; PC64LE9-NEXT:    xscvdpspn 0, 0
 ; PC64LE9-NEXT:    xscvdpspn 1, 1
 ; PC64LE9-NEXT:    xscvdpspn 2, 2
 ; PC64LE9-NEXT:    xxmrghw 34, 1, 2
-; PC64LE9-NEXT:    vperm 2, 3, 2, 4
+; PC64LE9-NEXT:    lxv 1, 0(3)
+; PC64LE9-NEXT:    xxperm 34, 0, 1
 ; PC64LE9-NEXT:    blr
 entry:
   %div = call <3 x float> @llvm.experimental.constrained.fdiv.v3f32(
            <3 x float> %x,
            <3 x float> %y,
            metadata !"round.dynamic",
            metadata !"fpexcept.strict") #1
   ret <3 x float> %div

 ; PC64LE9-NEXT:    xscvspdpn 1, 0
 ; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3
 ; PC64LE9-NEXT:    xscvspdpn 2, 0
 ; PC64LE9-NEXT:    bl fmodf
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    xscvdpspn 0, 1
 ; PC64LE9-NEXT:    xscvdpspn 1, 30
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI7_0@toc@ha
-; PC64LE9-NEXT:    xscvdpspn 35, 31
+; PC64LE9-NEXT:    addi 3, 3, .LCPI7_0@toc@l
+; PC64LE9-NEXT:    xxmrghw 34, 1, 0
+; PC64LE9-NEXT:    xscvdpspn 0, 31
+; PC64LE9-NEXT:    lxv 1, 0(3)
+; PC64LE9-NEXT:    xxperm 34, 0, 1
 ; PC64LE9-NEXT:    lxv 63, 48(1) # 16-byte Folded Reload
 ; PC64LE9-NEXT:    lxv 62, 32(1) # 16-byte Folded Reload
 ; PC64LE9-NEXT:    lfd 31, 72(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    addi 3, 3, .LCPI7_0@toc@l
 ; PC64LE9-NEXT:    lfd 30, 64(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    lxv 36, 0(3)
-; PC64LE9-NEXT:    xxmrghw 34, 1, 0
-; PC64LE9-NEXT:    vperm 2, 3, 2, 4
 ; PC64LE9-NEXT:    addi 1, 1, 80
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %rem = call <3 x float> @llvm.experimental.constrained.frem.v3f32(
            <3 x float> %x,
            <3 x float> %y,

 ; PC64LE9-NEXT:    addis 3, 2, .LCPI12_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI12_0@toc@l
 ; PC64LE9-NEXT:    xxswapd 2, 34
 ; PC64LE9-NEXT:    xxsldwi 3, 34, 34, 3
 ; PC64LE9-NEXT:    xscvspdpn 0, 0
 ; PC64LE9-NEXT:    xscvspdpn 1, 1
 ; PC64LE9-NEXT:    xscvspdpn 2, 2
 ; PC64LE9-NEXT:    xscvspdpn 3, 3
-; PC64LE9-NEXT:    lxv 36, 0(3)
 ; PC64LE9-NEXT:    xsmulsp 0, 1, 0
 ; PC64LE9-NEXT:    xxswapd 1, 35
 ; PC64LE9-NEXT:    xscvspdpn 1, 1
 ; PC64LE9-NEXT:    xsmulsp 1, 2, 1
 ; PC64LE9-NEXT:    xxsldwi 2, 35, 35, 3
-; PC64LE9-NEXT:    xscvdpspn 35, 0
+; PC64LE9-NEXT:    xscvdpspn 0, 0
 ; PC64LE9-NEXT:    xscvspdpn 2, 2
 ; PC64LE9-NEXT:    xsmulsp 2, 3, 2
 ; PC64LE9-NEXT:    xscvdpspn 1, 1
 ; PC64LE9-NEXT:    xscvdpspn 2, 2
 ; PC64LE9-NEXT:    xxmrghw 34, 1, 2
-; PC64LE9-NEXT:    vperm 2, 3, 2, 4
+; PC64LE9-NEXT:    lxv 1, 0(3)
+; PC64LE9-NEXT:    xxperm 34, 0, 1
 ; PC64LE9-NEXT:    blr
 entry:
   %mul = call <3 x float> @llvm.experimental.constrained.fmul.v3f32(
            <3 x float> %x,
            <3 x float> %y,
            metadata !"round.dynamic",
            metadata !"fpexcept.strict") #1
   ret <3 x float> %mul

 ; PC64LE9-NEXT:    addis 3, 2, .LCPI17_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI17_0@toc@l
 ; PC64LE9-NEXT:    xxswapd 2, 34
 ; PC64LE9-NEXT:    xxsldwi 3, 34, 34, 3
 ; PC64LE9-NEXT:    xscvspdpn 0, 0
 ; PC64LE9-NEXT:    xscvspdpn 1, 1
 ; PC64LE9-NEXT:    xscvspdpn 2, 2
 ; PC64LE9-NEXT:    xscvspdpn 3, 3
-; PC64LE9-NEXT:    lxv 36, 0(3)
 ; PC64LE9-NEXT:    xsaddsp 0, 1, 0
 ; PC64LE9-NEXT:    xxswapd 1, 35
 ; PC64LE9-NEXT:    xscvspdpn 1, 1
 ; PC64LE9-NEXT:    xsaddsp 1, 2, 1
 ; PC64LE9-NEXT:    xxsldwi 2, 35, 35, 3
-; PC64LE9-NEXT:    xscvdpspn 35, 0
+; PC64LE9-NEXT:    xscvdpspn 0, 0
 ; PC64LE9-NEXT:    xscvspdpn 2, 2
 ; PC64LE9-NEXT:    xsaddsp 2, 3, 2
 ; PC64LE9-NEXT:    xscvdpspn 1, 1
 ; PC64LE9-NEXT:    xscvdpspn 2, 2
 ; PC64LE9-NEXT:    xxmrghw 34, 1, 2
-; PC64LE9-NEXT:    vperm 2, 3, 2, 4
+; PC64LE9-NEXT:    lxv 1, 0(3)
+; PC64LE9-NEXT:    xxperm 34, 0, 1
 ; PC64LE9-NEXT:    blr
 entry:
   %add = call <3 x float> @llvm.experimental.constrained.fadd.v3f32(
            <3 x float> %x,
            <3 x float> %y,
            metadata !"round.dynamic",
            metadata !"fpexcept.strict") #1
   ret <3 x float> %add

 ; PC64LE9-NEXT:    addis 3, 2, .LCPI22_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI22_0@toc@l
 ; PC64LE9-NEXT:    xxswapd 2, 34
 ; PC64LE9-NEXT:    xxsldwi 3, 34, 34, 3
 ; PC64LE9-NEXT:    xscvspdpn 0, 0
 ; PC64LE9-NEXT:    xscvspdpn 1, 1
 ; PC64LE9-NEXT:    xscvspdpn 2, 2
 ; PC64LE9-NEXT:    xscvspdpn 3, 3
-; PC64LE9-NEXT:    lxv 36, 0(3)
 ; PC64LE9-NEXT:    xssubsp 0, 1, 0
 ; PC64LE9-NEXT:    xxswapd 1, 35
 ; PC64LE9-NEXT:    xscvspdpn 1, 1
 ; PC64LE9-NEXT:    xssubsp 1, 2, 1
 ; PC64LE9-NEXT:    xxsldwi 2, 35, 35, 3
-; PC64LE9-NEXT:    xscvdpspn 35, 0
+; PC64LE9-NEXT:    xscvdpspn 0, 0
 ; PC64LE9-NEXT:    xscvspdpn 2, 2
 ; PC64LE9-NEXT:    xssubsp 2, 3, 2
 ; PC64LE9-NEXT:    xscvdpspn 1, 1
 ; PC64LE9-NEXT:    xscvdpspn 2, 2
 ; PC64LE9-NEXT:    xxmrghw 34, 1, 2
-; PC64LE9-NEXT:    vperm 2, 3, 2, 4
+; PC64LE9-NEXT:    lxv 1, 0(3)
+; PC64LE9-NEXT:    xxperm 34, 0, 1
 ; PC64LE9-NEXT:    blr
 entry:
   %sub = call <3 x float> @llvm.experimental.constrained.fsub.v3f32(
            <3 x float> %x,
            <3 x float> %y,
            metadata !"round.dynamic",
            metadata !"fpexcept.strict") #1
   ret <3 x float> %sub

 ; PC64LE9-NEXT:    xxswapd 1, 34
 ; PC64LE9-NEXT:    xxsldwi 2, 34, 34, 3
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI27_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI27_0@toc@l
 ; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1
 ; PC64LE9-NEXT:    xscvspdpn 1, 1
 ; PC64LE9-NEXT:    xscvspdpn 2, 2
 ; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    lxv 35, 0(3)
 ; PC64LE9-NEXT:    xssqrtsp 1, 1
 ; PC64LE9-NEXT:    xssqrtsp 2, 2
 ; PC64LE9-NEXT:    xssqrtsp 0, 0
 ; PC64LE9-NEXT:    xscvdpspn 2, 2
 ; PC64LE9-NEXT:    xscvdpspn 1, 1
-; PC64LE9-NEXT:    xscvdpspn 36, 0
+; PC64LE9-NEXT:    xscvdpspn 0, 0
 ; PC64LE9-NEXT:    xxmrghw 34, 1, 2
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    lxv 1, 0(3)
+; PC64LE9-NEXT:    xxperm 34, 0, 1
 ; PC64LE9-NEXT:    blr
 entry:
   %sqrt = call <3 x float> @llvm.experimental.constrained.sqrt.v3f32(
                               <3 x float> %x,
                               metadata !"round.dynamic",
                               metadata !"fpexcept.strict") #1
   ret <3 x float> %sqrt
 }

 ; PC64LE9-NEXT:    xscvspdpn 1, 0
 ; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3
 ; PC64LE9-NEXT:    xscvspdpn 2, 0
 ; PC64LE9-NEXT:    bl powf
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    xscvdpspn 0, 1
 ; PC64LE9-NEXT:    xscvdpspn 1, 30
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI32_0@toc@ha
-; PC64LE9-NEXT:    xscvdpspn 35, 31
+; PC64LE9-NEXT:    addi 3, 3, .LCPI32_0@toc@l
+; PC64LE9-NEXT:    xxmrghw 34, 1, 0
+; PC64LE9-NEXT:    xscvdpspn 0, 31
+; PC64LE9-NEXT:    lxv 1, 0(3)
+; PC64LE9-NEXT:    xxperm 34, 0, 1
 ; PC64LE9-NEXT:    lxv 63, 48(1) # 16-byte Folded Reload
 ; PC64LE9-NEXT:    lxv 62, 32(1) # 16-byte Folded Reload
 ; PC64LE9-NEXT:    lfd 31, 72(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    addi 3, 3, .LCPI32_0@toc@l
 ; PC64LE9-NEXT:    lfd 30, 64(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    lxv 36, 0(3)
-; PC64LE9-NEXT:    xxmrghw 34, 1, 0
-; PC64LE9-NEXT:    vperm 2, 3, 2, 4
 ; PC64LE9-NEXT:    addi 1, 1, 80
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %pow = call <3 x float> @llvm.experimental.constrained.pow.v3f32(
                              <3 x float> %x,
                              <3 x float> %y,

 ; PC64LE9-NEXT:    fmr 30, 1
 ; PC64LE9-NEXT:    mr 4, 30
 ; PC64LE9-NEXT:    xscvspdpn 1, 0
 ; PC64LE9-NEXT:    bl __powisf2
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    xscvdpspn 0, 1
 ; PC64LE9-NEXT:    xscvdpspn 1, 30
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI37_0@toc@ha
-; PC64LE9-NEXT:    xscvdpspn 35, 31
+; PC64LE9-NEXT:    addi 3, 3, .LCPI37_0@toc@l
+; PC64LE9-NEXT:    xxmrghw 34, 1, 0
+; PC64LE9-NEXT:    xscvdpspn 0, 31
+; PC64LE9-NEXT:    lxv 1, 0(3)
+; PC64LE9-NEXT:    xxperm 34, 0, 1
 ; PC64LE9-NEXT:    lxv 63, 32(1) # 16-byte Folded Reload
 ; PC64LE9-NEXT:    lfd 31, 72(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    ld 30, 48(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    addi 3, 3, .LCPI37_0@toc@l
 ; PC64LE9-NEXT:    lfd 30, 64(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    lxv 36, 0(3)
-; PC64LE9-NEXT:    xxmrghw 34, 1, 0
-; PC64LE9-NEXT:    vperm 2, 3, 2, 4
+; PC64LE9-NEXT:    ld 30, 48(1) # 8-byte Folded Reload
 ; PC64LE9-NEXT:    addi 1, 1, 80
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %powi = call <3 x float> @llvm.experimental.constrained.powi.v3f32(
                               <3 x float> %x,
                               i32 %y,

 ; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3
 ; PC64LE9-NEXT:    fmr 30, 1
 ; PC64LE9-NEXT:    xscvspdpn 1, 0
 ; PC64LE9-NEXT:    bl sinf
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    xscvdpspn 0, 1
 ; PC64LE9-NEXT:    xscvdpspn 1, 30
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI42_0@toc@ha
-; PC64LE9-NEXT:    xscvdpspn 36, 31
+; PC64LE9-NEXT:    addi 3, 3, .LCPI42_0@toc@l
+; PC64LE9-NEXT:    xxmrghw 34, 1, 0
+; PC64LE9-NEXT:    xscvdpspn 1, 31
+; PC64LE9-NEXT:    lxv 0, 0(3)
+; PC64LE9-NEXT:    xxperm 34, 1, 0
 ; PC64LE9-NEXT:    lxv 63, 32(1) # 16-byte Folded Reload
 ; PC64LE9-NEXT:    lfd 31, 56(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    addi 3, 3, .LCPI42_0@toc@l
 ; PC64LE9-NEXT:    lfd 30, 48(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    xxmrghw 34, 1, 0
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
 ; PC64LE9-NEXT:    addi 1, 1, 64
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %sin = call <3 x float> @llvm.experimental.constrained.sin.v3f32(
                               <3 x float> %x,
                               metadata !"round.dynamic",

 ; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3
 ; PC64LE9-NEXT:    fmr 30, 1
 ; PC64LE9-NEXT:    xscvspdpn 1, 0
 ; PC64LE9-NEXT:    bl cosf
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    xscvdpspn 0, 1
 ; PC64LE9-NEXT:    xscvdpspn 1, 30
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI47_0@toc@ha
-; PC64LE9-NEXT:    xscvdpspn 36, 31
+; PC64LE9-NEXT:    addi 3, 3, .LCPI47_0@toc@l
+; PC64LE9-NEXT:    xxmrghw 34, 1, 0
+; PC64LE9-NEXT:    xscvdpspn 1, 31
+; PC64LE9-NEXT:    lxv 0, 0(3)
+; PC64LE9-NEXT:    xxperm 34, 1, 0
 ; PC64LE9-NEXT:    lxv 63, 32(1) # 16-byte Folded Reload
 ; PC64LE9-NEXT:    lfd 31, 56(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    addi 3, 3, .LCPI47_0@toc@l
 ; PC64LE9-NEXT:    lfd 30, 48(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    xxmrghw 34, 1, 0
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
 ; PC64LE9-NEXT:    addi 1, 1, 64
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %cos = call <3 x float> @llvm.experimental.constrained.cos.v3f32(
                               <3 x float> %x,
                               metadata !"round.dynamic",

 ; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3
 ; PC64LE9-NEXT:    fmr 30, 1
 ; PC64LE9-NEXT:    xscvspdpn 1, 0
 ; PC64LE9-NEXT:    bl expf
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    xscvdpspn 0, 1
 ; PC64LE9-NEXT:    xscvdpspn 1, 30
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI52_0@toc@ha
-; PC64LE9-NEXT:    xscvdpspn 36, 31
+; PC64LE9-NEXT:    addi 3, 3, .LCPI52_0@toc@l
+; PC64LE9-NEXT:    xxmrghw 34, 1, 0
+; PC64LE9-NEXT:    xscvdpspn 1, 31
+; PC64LE9-NEXT:    lxv 0, 0(3)
+; PC64LE9-NEXT:    xxperm 34, 1, 0
 ; PC64LE9-NEXT:    lxv 63, 32(1) # 16-byte Folded Reload
 ; PC64LE9-NEXT:    lfd 31, 56(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    addi 3, 3, .LCPI52_0@toc@l
 ; PC64LE9-NEXT:    lfd 30, 48(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    xxmrghw 34, 1, 0
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
 ; PC64LE9-NEXT:    addi 1, 1, 64
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %exp = call <3 x float> @llvm.experimental.constrained.exp.v3f32(
                               <3 x float> %x,
                               metadata !"round.dynamic",

 ; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3
 ; PC64LE9-NEXT:    fmr 30, 1
 ; PC64LE9-NEXT:    xscvspdpn 1, 0
 ; PC64LE9-NEXT:    bl exp2f
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    xscvdpspn 0, 1
 ; PC64LE9-NEXT:    xscvdpspn 1, 30
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI57_0@toc@ha
-; PC64LE9-NEXT:    xscvdpspn 36, 31
+; PC64LE9-NEXT:    addi 3, 3, .LCPI57_0@toc@l
+; PC64LE9-NEXT:    xxmrghw 34, 1, 0
+; PC64LE9-NEXT:    xscvdpspn 1, 31
+; PC64LE9-NEXT:    lxv 0, 0(3)
+; PC64LE9-NEXT:    xxperm 34, 1, 0
 ; PC64LE9-NEXT:    lxv 63, 32(1) # 16-byte Folded Reload
 ; PC64LE9-NEXT:    lfd 31, 56(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    addi 3, 3, .LCPI57_0@toc@l
 ; PC64LE9-NEXT:    lfd 30, 48(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    xxmrghw 34, 1, 0
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
 ; PC64LE9-NEXT:    addi 1, 1, 64
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %exp2 = call <3 x float> @llvm.experimental.constrained.exp2.v3f32(
                               <3 x float> %x,
                               metadata !"round.dynamic",

 ; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3
 ; PC64LE9-NEXT:    fmr 30, 1
 ; PC64LE9-NEXT:    xscvspdpn 1, 0
 ; PC64LE9-NEXT:    bl logf
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    xscvdpspn 0, 1
 ; PC64LE9-NEXT:    xscvdpspn 1, 30
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI62_0@toc@ha
-; PC64LE9-NEXT:    xscvdpspn 36, 31
+; PC64LE9-NEXT:    addi 3, 3, .LCPI62_0@toc@l
+; PC64LE9-NEXT:    xxmrghw 34, 1, 0
+; PC64LE9-NEXT:    xscvdpspn 1, 31
+; PC64LE9-NEXT:    lxv 0, 0(3)
+; PC64LE9-NEXT:    xxperm 34, 1, 0
 ; PC64LE9-NEXT:    lxv 63, 32(1) # 16-byte Folded Reload
 ; PC64LE9-NEXT:    lfd 31, 56(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    addi 3, 3, .LCPI62_0@toc@l
 ; PC64LE9-NEXT:    lfd 30, 48(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    xxmrghw 34, 1, 0
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
 ; PC64LE9-NEXT:    addi 1, 1, 64
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %log = call <3 x float> @llvm.experimental.constrained.log.v3f32(
                               <3 x float> %x,
                               metadata !"round.dynamic",

 ; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3
 ; PC64LE9-NEXT:    fmr 30, 1
 ; PC64LE9-NEXT:    xscvspdpn 1, 0
 ; PC64LE9-NEXT:    bl log10f
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    xscvdpspn 0, 1
 ; PC64LE9-NEXT:    xscvdpspn 1, 30
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI67_0@toc@ha
-; PC64LE9-NEXT:    xscvdpspn 36, 31
+; PC64LE9-NEXT:    addi 3, 3, .LCPI67_0@toc@l
+; PC64LE9-NEXT:    xxmrghw 34, 1, 0
+; PC64LE9-NEXT:    xscvdpspn 1, 31
+; PC64LE9-NEXT:    lxv 0, 0(3)
+; PC64LE9-NEXT:    xxperm 34, 1, 0
 ; PC64LE9-NEXT:    lxv 63, 32(1) # 16-byte Folded Reload
 ; PC64LE9-NEXT:    lfd 31, 56(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    addi 3, 3, .LCPI67_0@toc@l
 ; PC64LE9-NEXT:    lfd 30, 48(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    xxmrghw 34, 1, 0
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
 ; PC64LE9-NEXT:    addi 1, 1, 64
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %log10 = call <3 x float> @llvm.experimental.constrained.log10.v3f32(
                               <3 x float> %x,
                               metadata !"round.dynamic",

 ; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3
 ; PC64LE9-NEXT:    fmr 30, 1
 ; PC64LE9-NEXT:    xscvspdpn 1, 0
 ; PC64LE9-NEXT:    bl log2f
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    xscvdpspn 0, 1
 ; PC64LE9-NEXT:    xscvdpspn 1, 30
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI72_0@toc@ha
-; PC64LE9-NEXT:    xscvdpspn 36, 31
+; PC64LE9-NEXT:    addi 3, 3, .LCPI72_0@toc@l
+; PC64LE9-NEXT:    xxmrghw 34, 1, 0
+; PC64LE9-NEXT:    xscvdpspn 1, 31
+; PC64LE9-NEXT:    lxv 0, 0(3)
+; PC64LE9-NEXT:    xxperm 34, 1, 0
 ; PC64LE9-NEXT:    lxv 63, 32(1) # 16-byte Folded Reload
 ; PC64LE9-NEXT:    lfd 31, 56(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    addi 3, 3, .LCPI72_0@toc@l
 ; PC64LE9-NEXT:    lfd 30, 48(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    xxmrghw 34, 1, 0
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
 ; PC64LE9-NEXT:    addi 1, 1, 64
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %log2 = call <3 x float> @llvm.experimental.constrained.log2.v3f32(
                               <3 x float> %x,
                               metadata !"round.dynamic",

 ; PC64LE9-NEXT:    xxswapd 1, 34
 ; PC64LE9-NEXT:    xxsldwi 2, 34, 34, 3
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI77_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI77_0@toc@l
 ; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1
 ; PC64LE9-NEXT:    xscvspdpn 1, 1
 ; PC64LE9-NEXT:    xscvspdpn 2, 2
 ; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    lxv 35, 0(3)
 ; PC64LE9-NEXT:    xsrdpic 1, 1
 ; PC64LE9-NEXT:    xsrdpic 2, 2
 ; PC64LE9-NEXT:    xsrdpic 0, 0
 ; PC64LE9-NEXT:    xscvdpspn 2, 2
 ; PC64LE9-NEXT:    xscvdpspn 1, 1
-; PC64LE9-NEXT:    xscvdpspn 36, 0
+; PC64LE9-NEXT:    xscvdpspn 0, 0
 ; PC64LE9-NEXT:    xxmrghw 34, 1, 2
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    lxv 1, 0(3)
+; PC64LE9-NEXT:    xxperm 34, 0, 1
 ; PC64LE9-NEXT:    blr
  entry:
   %rint = call <3 x float> @llvm.experimental.constrained.rint.v3f32(
                               <3 x float> %x,
                               metadata !"round.dynamic",
                               metadata !"fpexcept.strict") #1
   ret <3 x float> %rint
 }

 ; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3
 ; PC64LE9-NEXT:    fmr 30, 1
 ; PC64LE9-NEXT:    xscvspdpn 1, 0
 ; PC64LE9-NEXT:    bl nearbyintf
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    xscvdpspn 0, 1
 ; PC64LE9-NEXT:    xscvdpspn 1, 30
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI82_0@toc@ha
-; PC64LE9-NEXT:    xscvdpspn 36, 31
+; PC64LE9-NEXT:    addi 3, 3, .LCPI82_0@toc@l
+; PC64LE9-NEXT:    xxmrghw 34, 1, 0
+; PC64LE9-NEXT:    xscvdpspn 1, 31
+; PC64LE9-NEXT:    lxv 0, 0(3)
+; PC64LE9-NEXT:    xxperm 34, 1, 0
 ; PC64LE9-NEXT:    lxv 63, 32(1) # 16-byte Folded Reload
 ; PC64LE9-NEXT:    lfd 31, 56(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    addi 3, 3, .LCPI82_0@toc@l
 ; PC64LE9-NEXT:    lfd 30, 48(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    xxmrghw 34, 1, 0
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
 ; PC64LE9-NEXT:    addi 1, 1, 64
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %nearby = call <3 x float> @llvm.experimental.constrained.nearbyint.v3f32(
                               <3 x float> %x,
                               metadata !"round.dynamic",

 ; PC64LE9-NEXT:    xscvspdpn 1, 0
 ; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3
 ; PC64LE9-NEXT:    xscvspdpn 2, 0
 ; PC64LE9-NEXT:    bl fmaxf
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    xscvdpspn 0, 1
 ; PC64LE9-NEXT:    xscvdpspn 1, 30
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI87_0@toc@ha
-; PC64LE9-NEXT:    xscvdpspn 35, 31
+; PC64LE9-NEXT:    addi 3, 3, .LCPI87_0@toc@l
+; PC64LE9-NEXT:    xxmrghw 34, 1, 0
+; PC64LE9-NEXT:    xscvdpspn 0, 31
+; PC64LE9-NEXT:    lxv 1, 0(3)
+; PC64LE9-NEXT:    xxperm 34, 0, 1
 ; PC64LE9-NEXT:    lxv 63, 48(1) # 16-byte Folded Reload
 ; PC64LE9-NEXT:    lxv 62, 32(1) # 16-byte Folded Reload
 ; PC64LE9-NEXT:    lfd 31, 72(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    addi 3, 3, .LCPI87_0@toc@l
 ; PC64LE9-NEXT:    lfd 30, 64(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    lxv 36, 0(3)
-; PC64LE9-NEXT:    xxmrghw 34, 1, 0
-; PC64LE9-NEXT:    vperm 2, 3, 2, 4
 ; PC64LE9-NEXT:    addi 1, 1, 80
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %max = call <3 x float> @llvm.experimental.constrained.maxnum.v3f32(
                               <3 x float> %x,
                               <3 x float> %y,

 ; PC64LE9-NEXT:    xscvspdpn 1, 0
 ; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3
 ; PC64LE9-NEXT:    xscvspdpn 2, 0
 ; PC64LE9-NEXT:    bl fminf
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    xscvdpspn 0, 1
 ; PC64LE9-NEXT:    xscvdpspn 1, 30
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI92_0@toc@ha
-; PC64LE9-NEXT:    xscvdpspn 35, 31
+; PC64LE9-NEXT:    addi 3, 3, .LCPI92_0@toc@l
+; PC64LE9-NEXT:    xxmrghw 34, 1, 0
+; PC64LE9-NEXT:    xscvdpspn 0, 31
+; PC64LE9-NEXT:    lxv 1, 0(3)
+; PC64LE9-NEXT:    xxperm 34, 0, 1
 ; PC64LE9-NEXT:    lxv 63, 48(1) # 16-byte Folded Reload
 ; PC64LE9-NEXT:    lxv 62, 32(1) # 16-byte Folded Reload
 ; PC64LE9-NEXT:    lfd 31, 72(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    addi 3, 3, .LCPI92_0@toc@l
 ; PC64LE9-NEXT:    lfd 30, 64(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    lxv 36, 0(3)
-; PC64LE9-NEXT:    xxmrghw 34, 1, 0
-; PC64LE9-NEXT:    vperm 2, 3, 2, 4
 ; PC64LE9-NEXT:    addi 1, 1, 80
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %min = call <3 x float> @llvm.experimental.constrained.minnum.v3f32(
                               <3 x float> %x,
                               <3 x float> %y,

 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptosi_v3i32_v3f32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 3
 ; PC64LE9-NEXT:    xxswapd 1, 34
 ; PC64LE9-NEXT:    xscvspdpn 0, 0
 ; PC64LE9-NEXT:    xscvspdpn 1, 1
+; PC64LE9-NEXT:    xxsldwi 2, 34, 34, 1
+; PC64LE9-NEXT:    xscvspdpn 2, 2
 ; PC64LE9-NEXT:    xscvdpsxws 0, 0
 ; PC64LE9-NEXT:    xscvdpsxws 1, 1
+; PC64LE9-NEXT:    xscvdpsxws 2, 2
 ; PC64LE9-NEXT:    mffprwz 3, 0
 ; PC64LE9-NEXT:    mtfprwz 0, 3
 ; PC64LE9-NEXT:    mffprwz 3, 1
 ; PC64LE9-NEXT:    mtfprwz 1, 3
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI97_0@toc@ha
-; PC64LE9-NEXT:    xxmrghw 35, 1, 0
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI97_0@toc@l
-; PC64LE9-NEXT:    lxv 36, 0(3)
-; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    xscvdpsxws 0, 0
-; PC64LE9-NEXT:    mffprwz 3, 0
-; PC64LE9-NEXT:    mtvsrwz 34, 3
-; PC64LE9-NEXT:    vperm 2, 2, 3, 4
+; PC64LE9-NEXT:    xxmrghw 0, 1, 0
+; PC64LE9-NEXT:    lxv 1, 0(3)
+; PC64LE9-NEXT:    mffprwz 3, 2
+; PC64LE9-NEXT:    mtfprwz 2, 3
+; PC64LE9-NEXT:    xxperm 0, 2, 1
+; PC64LE9-NEXT:    xxlor 34, 0, 0
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <3 x i32> @llvm.experimental.constrained.fptosi.v3i32.v3f32(
                                 <3 x float> %x,
                                 metadata !"fpexcept.strict") #0
   ret <3 x i32> %result
 }
 

 ; PC64LE9-NEXT:    xscvdpsxws 0, 1
 ; PC64LE9-NEXT:    xscvdpsxws 1, 2
 ; PC64LE9-NEXT:    mffprwz 3, 0
 ; PC64LE9-NEXT:    mtfprwz 0, 3
 ; PC64LE9-NEXT:    mffprwz 3, 1
 ; PC64LE9-NEXT:    mtfprwz 1, 3
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI105_0@toc@ha
 ; PC64LE9-NEXT:    xxmrghw 34, 1, 0
-; PC64LE9-NEXT:    xscvdpsxws 0, 3
+; PC64LE9-NEXT:    xscvdpsxws 1, 3
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI105_0@toc@l
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    mffprwz 3, 0
-; PC64LE9-NEXT:    mtvsrwz 36, 3
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    lxv 0, 0(3)
+; PC64LE9-NEXT:    mffprwz 3, 1
+; PC64LE9-NEXT:    mtfprwz 1, 3
+; PC64LE9-NEXT:    xxperm 34, 1, 0
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <3 x i32> @llvm.experimental.constrained.fptosi.v3i32.v3f64(
                                 <3 x double> %x,
                                 metadata !"fpexcept.strict") #0
   ret <3 x i32> %result
 }
 

 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptoui_v3i32_v3f32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 3
 ; PC64LE9-NEXT:    xxswapd 1, 34
 ; PC64LE9-NEXT:    xscvspdpn 0, 0
 ; PC64LE9-NEXT:    xscvspdpn 1, 1
+; PC64LE9-NEXT:    xxsldwi 2, 34, 34, 1
+; PC64LE9-NEXT:    xscvspdpn 2, 2
 ; PC64LE9-NEXT:    xscvdpuxws 0, 0
 ; PC64LE9-NEXT:    xscvdpuxws 1, 1
+; PC64LE9-NEXT:    xscvdpuxws 2, 2
 ; PC64LE9-NEXT:    mffprwz 3, 0
 ; PC64LE9-NEXT:    mtfprwz 0, 3
 ; PC64LE9-NEXT:    mffprwz 3, 1
 ; PC64LE9-NEXT:    mtfprwz 1, 3
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI113_0@toc@ha
-; PC64LE9-NEXT:    xxmrghw 35, 1, 0
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI113_0@toc@l
-; PC64LE9-NEXT:    lxv 36, 0(3)
-; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    xscvdpuxws 0, 0
-; PC64LE9-NEXT:    mffprwz 3, 0
-; PC64LE9-NEXT:    mtvsrwz 34, 3
-; PC64LE9-NEXT:    vperm 2, 2, 3, 4
+; PC64LE9-NEXT:    xxmrghw 0, 1, 0
+; PC64LE9-NEXT:    lxv 1, 0(3)
+; PC64LE9-NEXT:    mffprwz 3, 2
+; PC64LE9-NEXT:    mtfprwz 2, 3
+; PC64LE9-NEXT:    xxperm 0, 2, 1
+; PC64LE9-NEXT:    xxlor 34, 0, 0
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <3 x i32> @llvm.experimental.constrained.fptoui.v3i32.v3f32(
                                 <3 x float> %x,
                                 metadata !"fpexcept.strict") #0
   ret <3 x i32> %result
 }
 

 ; PC64LE9-NEXT:    xscvdpuxws 0, 1
 ; PC64LE9-NEXT:    xscvdpuxws 1, 2
 ; PC64LE9-NEXT:    mffprwz 3, 0
 ; PC64LE9-NEXT:    mtfprwz 0, 3
 ; PC64LE9-NEXT:    mffprwz 3, 1
 ; PC64LE9-NEXT:    mtfprwz 1, 3
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI121_0@toc@ha
 ; PC64LE9-NEXT:    xxmrghw 34, 1, 0
-; PC64LE9-NEXT:    xscvdpuxws 0, 3
+; PC64LE9-NEXT:    xscvdpuxws 1, 3
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI121_0@toc@l
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    mffprwz 3, 0
-; PC64LE9-NEXT:    mtvsrwz 36, 3
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    lxv 0, 0(3)
+; PC64LE9-NEXT:    mffprwz 3, 1
+; PC64LE9-NEXT:    mtfprwz 1, 3
+; PC64LE9-NEXT:    xxperm 34, 1, 0
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <3 x i32> @llvm.experimental.constrained.fptoui.v3i32.v3f64(
                                 <3 x double> %x,
                                 metadata !"fpexcept.strict") #0
   ret <3 x i32> %result
 }
 

 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptrunc_v3f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    xsrsp 0, 1
 ; PC64LE9-NEXT:    xsrsp 1, 2
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI129_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI129_0@toc@l
-; PC64LE9-NEXT:    lxv 35, 0(3)
 ; PC64LE9-NEXT:    xscvdpspn 0, 0
 ; PC64LE9-NEXT:    xscvdpspn 1, 1
 ; PC64LE9-NEXT:    xxmrghw 34, 1, 0
-; PC64LE9-NEXT:    xsrsp 0, 3
-; PC64LE9-NEXT:    xscvdpspn 36, 0
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    xsrsp 1, 3
+; PC64LE9-NEXT:    lxv 0, 0(3)
+; PC64LE9-NEXT:    xscvdpspn 1, 1
+; PC64LE9-NEXT:    xxperm 34, 1, 0
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <3 x float> @llvm.experimental.constrained.fptrunc.v3f32.v3f64(
                                 <3 x double> %x,
                                 metadata !"round.dynamic",
                                 metadata !"fpexcept.strict") #1
   ret <3 x float> %result
 }

 ; PC64LE9-NEXT:    xxswapd 1, 34
 ; PC64LE9-NEXT:    xxsldwi 2, 34, 34, 3
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI137_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI137_0@toc@l
 ; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1
 ; PC64LE9-NEXT:    xscvspdpn 1, 1
 ; PC64LE9-NEXT:    xscvspdpn 2, 2
 ; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    lxv 35, 0(3)
 ; PC64LE9-NEXT:    xsrdpip 1, 1
 ; PC64LE9-NEXT:    xsrdpip 2, 2
 ; PC64LE9-NEXT:    xsrdpip 0, 0
 ; PC64LE9-NEXT:    xscvdpspn 2, 2
 ; PC64LE9-NEXT:    xscvdpspn 1, 1
-; PC64LE9-NEXT:    xscvdpspn 36, 0
+; PC64LE9-NEXT:    xscvdpspn 0, 0
 ; PC64LE9-NEXT:    xxmrghw 34, 1, 2
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    lxv 1, 0(3)
+; PC64LE9-NEXT:    xxperm 34, 0, 1
 ; PC64LE9-NEXT:    blr
 entry:
   %ceil = call <3 x float> @llvm.experimental.constrained.ceil.v3f32(
                               <3 x float> %x,
                               metadata !"fpexcept.strict") #1
   ret <3 x float> %ceil
 }
 

 ; PC64LE9-NEXT:    xxswapd 1, 34
 ; PC64LE9-NEXT:    xxsldwi 2, 34, 34, 3
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI141_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI141_0@toc@l
 ; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1
 ; PC64LE9-NEXT:    xscvspdpn 1, 1
 ; PC64LE9-NEXT:    xscvspdpn 2, 2
 ; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    lxv 35, 0(3)
 ; PC64LE9-NEXT:    xsrdpim 1, 1
 ; PC64LE9-NEXT:    xsrdpim 2, 2
 ; PC64LE9-NEXT:    xsrdpim 0, 0
 ; PC64LE9-NEXT:    xscvdpspn 2, 2
 ; PC64LE9-NEXT:    xscvdpspn 1, 1
-; PC64LE9-NEXT:    xscvdpspn 36, 0
+; PC64LE9-NEXT:    xscvdpspn 0, 0
 ; PC64LE9-NEXT:    xxmrghw 34, 1, 2
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    lxv 1, 0(3)
+; PC64LE9-NEXT:    xxperm 34, 0, 1
 ; PC64LE9-NEXT:    blr
 entry:
   %floor = call <3 x float> @llvm.experimental.constrained.floor.v3f32(
                               <3 x float> %x,
                               metadata !"fpexcept.strict") #1
   ret <3 x float> %floor
 }
 

 ; PC64LE9-NEXT:    xxswapd 1, 34
 ; PC64LE9-NEXT:    xxsldwi 2, 34, 34, 3
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI145_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI145_0@toc@l
 ; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1
 ; PC64LE9-NEXT:    xscvspdpn 1, 1
 ; PC64LE9-NEXT:    xscvspdpn 2, 2
 ; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    lxv 35, 0(3)
 ; PC64LE9-NEXT:    xsrdpi 1, 1
 ; PC64LE9-NEXT:    xsrdpi 2, 2
 ; PC64LE9-NEXT:    xsrdpi 0, 0
 ; PC64LE9-NEXT:    xscvdpspn 2, 2
 ; PC64LE9-NEXT:    xscvdpspn 1, 1
-; PC64LE9-NEXT:    xscvdpspn 36, 0
+; PC64LE9-NEXT:    xscvdpspn 0, 0
 ; PC64LE9-NEXT:    xxmrghw 34, 1, 2
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    lxv 1, 0(3)
+; PC64LE9-NEXT:    xxperm 34, 0, 1
 ; PC64LE9-NEXT:    blr
 entry:
   %round = call <3 x float> @llvm.experimental.constrained.round.v3f32(
                               <3 x float> %x,
                               metadata !"fpexcept.strict") #1
   ret <3 x float> %round
 }
 

 ; PC64LE9-NEXT:    xxswapd 1, 34
 ; PC64LE9-NEXT:    xxsldwi 2, 34, 34, 3
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI149_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI149_0@toc@l
 ; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1
 ; PC64LE9-NEXT:    xscvspdpn 1, 1
 ; PC64LE9-NEXT:    xscvspdpn 2, 2
 ; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    lxv 35, 0(3)
 ; PC64LE9-NEXT:    xsrdpiz 1, 1
 ; PC64LE9-NEXT:    xsrdpiz 2, 2
 ; PC64LE9-NEXT:    xsrdpiz 0, 0
 ; PC64LE9-NEXT:    xscvdpspn 2, 2
 ; PC64LE9-NEXT:    xscvdpspn 1, 1
-; PC64LE9-NEXT:    xscvdpspn 36, 0
+; PC64LE9-NEXT:    xscvdpspn 0, 0
 ; PC64LE9-NEXT:    xxmrghw 34, 1, 2
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    lxv 1, 0(3)
+; PC64LE9-NEXT:    xxperm 34, 0, 1
 ; PC64LE9-NEXT:    blr
 entry:
   %trunc = call <3 x float> @llvm.experimental.constrained.trunc.v3f32(
                               <3 x float> %x,
                               metadata !"fpexcept.strict") #1
   ret <3 x float> %trunc
 }
 

 ; PC64LE-NEXT:    vsrad 2, 2, 3
 ; PC64LE-NEXT:    xvcvsxddp 34, 34
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_sitofp_v2f64_v2i16:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI155_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI155_0@toc@l
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    vperm 2, 2, 2, 3
+; PC64LE9-NEXT:    lxv 0, 0(3)
+; PC64LE9-NEXT:    xxperm 34, 34, 0
 ; PC64LE9-NEXT:    vextsh2d 2, 2
 ; PC64LE9-NEXT:    xvcvsxddp 34, 34
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <2 x double>
            @llvm.experimental.constrained.sitofp.v2f64.v2i16(<2 x i16> %x,
                                                 metadata !"round.dynamic",
                                                 metadata !"fpexcept.strict") #0

 ; PC64LE9-NEXT:    li 3, 4
 ; PC64LE9-NEXT:    vextuwrx 3, 3, 2
 ; PC64LE9-NEXT:    xscvsxdsp 0, 0
 ; PC64LE9-NEXT:    mtfprwa 1, 3
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI161_0@toc@ha
 ; PC64LE9-NEXT:    xscvsxdsp 1, 1
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI161_0@toc@l
 ; PC64LE9-NEXT:    xscvdpspn 0, 0
-; PC64LE9-NEXT:    lxv 36, 0(3)
-; PC64LE9-NEXT:    mfvsrwz 3, 34
 ; PC64LE9-NEXT:    xscvdpspn 1, 1
-; PC64LE9-NEXT:    xxmrghw 35, 1, 0
-; PC64LE9-NEXT:    mtfprwa 0, 3
-; PC64LE9-NEXT:    xscvsxdsp 0, 0
-; PC64LE9-NEXT:    xscvdpspn 34, 0
-; PC64LE9-NEXT:    vperm 2, 2, 3, 4
+; PC64LE9-NEXT:    xxmrghw 0, 1, 0
+; PC64LE9-NEXT:    lxv 1, 0(3)
+; PC64LE9-NEXT:    mfvsrwz 3, 34
+; PC64LE9-NEXT:    mtfprwa 2, 3
+; PC64LE9-NEXT:    xscvsxdsp 2, 2
+; PC64LE9-NEXT:    xscvdpspn 2, 2
+; PC64LE9-NEXT:    xxperm 0, 2, 1
+; PC64LE9-NEXT:    xxlor 34, 0, 0
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <3 x float>
            @llvm.experimental.constrained.sitofp.v3f32.v3i32(<3 x i32> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <3 x float> %result
 }

 ; PC64LE9-LABEL: constrained_vector_sitofp_v3f32_v3i64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mtfprd 0, 3
 ; PC64LE9-NEXT:    mtfprd 1, 4
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI163_0@toc@ha
 ; PC64LE9-NEXT:    xscvsxdsp 0, 0
 ; PC64LE9-NEXT:    xscvsxdsp 1, 1
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI163_0@toc@l
-; PC64LE9-NEXT:    lxv 35, 0(3)
 ; PC64LE9-NEXT:    xscvdpspn 0, 0
 ; PC64LE9-NEXT:    xscvdpspn 1, 1
 ; PC64LE9-NEXT:    xxmrghw 34, 1, 0
-; PC64LE9-NEXT:    mtfprd 0, 5
-; PC64LE9-NEXT:    xscvsxdsp 0, 0
-; PC64LE9-NEXT:    xscvdpspn 36, 0
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    mtfprd 1, 5
+; PC64LE9-NEXT:    lxv 0, 0(3)
+; PC64LE9-NEXT:    xscvsxdsp 1, 1
+; PC64LE9-NEXT:    xscvdpspn 1, 1
+; PC64LE9-NEXT:    xxperm 34, 1, 0
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <3 x float>
            @llvm.experimental.constrained.sitofp.v3f32.v3i64(<3 x i64> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <3 x float> %result
 }

 ; PC64LE-NEXT:    xxswapd 35, 0
 ; PC64LE-NEXT:    vperm 2, 4, 2, 3
 ; PC64LE-NEXT:    xvcvuxddp 34, 34
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_uitofp_v2f64_v2i16:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI173_0@toc@ha
-; PC64LE9-NEXT:    xxlxor 36, 36, 36
+; PC64LE9-NEXT:    xxlxor 0, 0, 0
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI173_0@toc@l
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    lxv 1, 0(3)
+; PC64LE9-NEXT:    xxperm 34, 0, 1
 ; PC64LE9-NEXT:    xvcvuxddp 34, 34
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <2 x double>
            @llvm.experimental.constrained.uitofp.v2f64.v2i16(<2 x i16> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <2 x double> %result

 ; PC64LE9-NEXT:    li 3, 4
 ; PC64LE9-NEXT:    vextuwrx 3, 3, 2
 ; PC64LE9-NEXT:    xscvuxdsp 0, 0
 ; PC64LE9-NEXT:    mtfprwz 1, 3
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI179_0@toc@ha
 ; PC64LE9-NEXT:    xscvuxdsp 1, 1
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI179_0@toc@l
 ; PC64LE9-NEXT:    xscvdpspn 0, 0
-; PC64LE9-NEXT:    lxv 36, 0(3)
-; PC64LE9-NEXT:    mfvsrwz 3, 34
 ; PC64LE9-NEXT:    xscvdpspn 1, 1
-; PC64LE9-NEXT:    xxmrghw 35, 1, 0
-; PC64LE9-NEXT:    mtfprwz 0, 3
-; PC64LE9-NEXT:    xscvuxdsp 0, 0
-; PC64LE9-NEXT:    xscvdpspn 34, 0
-; PC64LE9-NEXT:    vperm 2, 2, 3, 4
+; PC64LE9-NEXT:    xxmrghw 0, 1, 0
+; PC64LE9-NEXT:    lxv 1, 0(3)
+; PC64LE9-NEXT:    mfvsrwz 3, 34
+; PC64LE9-NEXT:    mtfprwz 2, 3
+; PC64LE9-NEXT:    xscvuxdsp 2, 2
+; PC64LE9-NEXT:    xscvdpspn 2, 2
+; PC64LE9-NEXT:    xxperm 0, 2, 1
+; PC64LE9-NEXT:    xxlor 34, 0, 0
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <3 x float>
            @llvm.experimental.constrained.uitofp.v3f32.v3i32(<3 x i32> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <3 x float> %result
 }

 ; PC64LE9-LABEL: constrained_vector_uitofp_v3f32_v3i64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mtfprd 0, 3
 ; PC64LE9-NEXT:    mtfprd 1, 4
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI181_0@toc@ha
 ; PC64LE9-NEXT:    xscvuxdsp 0, 0
 ; PC64LE9-NEXT:    xscvuxdsp 1, 1
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI181_0@toc@l
-; PC64LE9-NEXT:    lxv 35, 0(3)
 ; PC64LE9-NEXT:    xscvdpspn 0, 0
 ; PC64LE9-NEXT:    xscvdpspn 1, 1
 ; PC64LE9-NEXT:    xxmrghw 34, 1, 0
-; PC64LE9-NEXT:    mtfprd 0, 5
-; PC64LE9-NEXT:    xscvuxdsp 0, 0
-; PC64LE9-NEXT:    xscvdpspn 36, 0
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    mtfprd 1, 5
+; PC64LE9-NEXT:    lxv 0, 0(3)
+; PC64LE9-NEXT:    xscvuxdsp 1, 1
+; PC64LE9-NEXT:    xscvdpspn 1, 1
+; PC64LE9-NEXT:    xxperm 34, 1, 0
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <3 x float>
            @llvm.experimental.constrained.uitofp.v3f32.v3i64(<3 x i64> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <3 x float> %result
 }