[RISCV] Add assertion of hasVecPolicyOp to catch masked intrinsic without policy operand.

[fakepaper56]

Summary

The original code may have incorrect result if there is a masked instruction
without policy operand to make us set its policy to TUMU. The patch adds an
assertion to catch the instruction.

[reames]

LGTM

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

while (Position != CurDAG->allnodes_begin()) {
     // Allow the peephole for non-exception True with VLMAX vector length, since
     // all the values after VL of N are dependent on Merge. VLMAX should be
     // lowered to (XLenVT -1).
     if (TrueVL != VL && !(IsNoFPExcept(True) && isAllOnesConstant(TrueVL)))
       continue;
 
     SDLoc DL(N);
     unsigned MaskedOpc = Info->MaskedPseudo;
+    assert(RISCVII::hasVecPolicyOp(TII->get(MaskedOpc).TSFlags) &&
+           "Expected instructions with mask have policy operand.");
+
     SmallVector<SDValue, 8> Ops;
     Ops.push_back(Merge);
     Ops.append(True->op_begin(), True->op_begin() + TrueVLIndex);
     Ops.append({Mask, VL, /* SEW */ True.getOperand(TrueVLIndex + 1)});
-
-    if (RISCVII::hasVecPolicyOp(TII->get(MaskedOpc).TSFlags))
-      Ops.push_back(
-          CurDAG->getTargetConstant(/* TUMU */ 0, DL, Subtarget->getXLenVT()));
 
     // Result node should have chain operand of True.
     if (HasChainOp)
       Ops.push_back(True.getOperand(True.getNumOperands() - 1));
 
     // Result node should take over glued node of N.
     if (N->getGluedNode())
       Ops.push_back(N->getOperand(N->getNumOperands() - 1));