[TypePromotion] Don't insert Truncate for a no-op ZExt

[avieira]

Summary

Hi,

As the title says, I don't believe there's a point in inserting Truncates before ZExt's that have no-effect, i.e. ZExts where the argument's type width is the same as the result's type width.

This is a prerequisite for the test in D111237 to pass.

[samparker]

Thanks.

[avieira]

I'm just gonna rebase this to see if I also get the failure on TypePromotion/ARM/calls.ll that the bot is reporting.

[avieira]

I had forgotten to build for ARM too, which had similar testisms as AArch64 where this patch removes unnecessary Truncates. Updated tests.

[samparker]

Good catch.

[barannikov88]

llvm/lib/CodeGen/TypePromotion.cpp

554

The comment is kind of misleading. According to LangRef, the size of the input operand of zext must be less than the size of the output operand. It is also asserted in the constructor of the operation (see CastInst::castIsValid).

[avieira]

Is that somewhat clearer? I suspect the reason we never see a failure is because we 'replace' the input, rather than create a new ZExt. But like I said in the comment, it get's deleted. And as it is the trunc would just stay there dangling and get in the way of things.

[barannikov88]

In D131487#3713019, @avieira wrote:

Is that somewhat clearer? I suspect the reason we never see a failure is because we 'replace' the input, rather than create a new ZExt. But like I said in the comment, it get's deleted. And as it is the trunc would just stay there dangling and get in the way of things.

With that comment is is pretty much clear now, thanks.

llvm/lib/CodeGen/TypePromotion.cpp

if (auto *Switch = dyn_cast<SwitchInst>(I)) {
       if (Instruction *Trunc = InsertTrunc(Switch->getCondition(), Ty)) {
         Trunc->moveBefore(Switch);
         Switch->setCondition(Trunc);
       }
       continue;
     }
 
     // Don't insert a trunc for a zext which can still legally promote.
+    // Nor insert a trunc when the input value to that trunc has the same width
+    // as the zext we are inserting it for.  When this happens the input operand
+    // for the zext will be promoted to the same width as the zext's return type
+    // rendering that zext unnecessary.  This zext gets removed before the end
+    // of the pass.
     if (auto ZExt = dyn_cast<ZExtInst>(I))
-      if (ZExt->getType()->getScalarSizeInBits() > PromotedWidth)
+      if (ZExt->getType()->getScalarSizeInBits() >= PromotedWidth)
         continue;
 
     // Now handle the others.
     for (unsigned i = 0; i < I->getNumOperands(); ++i) {
       Type *Ty = TruncTysMap[I][i];
       if (Instruction *Trunc = InsertTrunc(I->getOperand(i), Ty)) {
         Trunc->moveBefore(I);
         I->setOperand(i, Trunc);

llvm/test/Transforms/TypePromotion/AArch64/phi-zext-gep.ll

 ; CHECK-NEXT:    [[TAG_0_IN:%.*]] = load i8, i8* [[ARRAYIDX]], align 1
 ; CHECK-NEXT:    [[TMP1]] = zext i8 [[TAG_0_IN]] to i32
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 [[TMP1]], 100
 ; CHECK-NEXT:    br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_END_LOOPEXIT:%.*]]
 ; CHECK:       for.end.loopexit:
 ; CHECK-NEXT:    br label [[FOR_END]]
 ; CHECK:       for.end:
 ; CHECK-NEXT:    [[TAG_0_IN_LCSSA:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[TMP1]], [[FOR_END_LOOPEXIT]] ]
-; CHECK-NEXT:    [[TMP2:%.*]] = trunc i32 [[TAG_0_IN_LCSSA]] to i8
 ; CHECK-NEXT:    ret i32 [[TAG_0_IN_LCSSA]]
 ;
 entry:
   %tag.0.in8 = load i8, i8* %ip, align 1
   %cmp9 = icmp ult i8 %tag.0.in8, 100
   br i1 %cmp9, label %for.body.preheader, label %for.end
 
 for.body.preheader:                               ; preds = %entry

llvm/test/Transforms/TypePromotion/ARM/calls.ll

 ; CHECK-LABEL: @check_zext_phi_call_arg(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br label [[FOR_COND:%.*]]
 ; CHECK:       for.cond:
 ; CHECK-NEXT:    [[D_SROA_0_0:%.*]] = phi i32 [ 30, [[ENTRY:%.*]] ], [ [[D_SROA_0_0_BE:%.*]], [[FOR_COND_BACKEDGE:%.*]] ]
 ; CHECK-NEXT:    [[TOBOOL:%.*]] = icmp eq i32 [[D_SROA_0_0]], 0
 ; CHECK-NEXT:    br i1 [[TOBOOL]], label [[FOR_COND_BACKEDGE]], label [[IF_THEN:%.*]]
 ; CHECK:       for.cond.backedge:
-; CHECK-NEXT:    [[D_SROA_0_0_BE]] = phi i32 [ [[TMP1:%.*]], [[IF_THEN]] ], [ 0, [[FOR_COND]] ]
+; CHECK-NEXT:    [[D_SROA_0_0_BE]] = phi i32 [ [[TMP0:%.*]], [[IF_THEN]] ], [ 0, [[FOR_COND]] ]
 ; CHECK-NEXT:    br label [[FOR_COND]]
 ; CHECK:       if.then:
-; CHECK-NEXT:    [[TMP0:%.*]] = trunc i32 [[D_SROA_0_0]] to i16
 ; CHECK-NEXT:    [[CALL:%.*]] = tail call zeroext i16 bitcast (i16 (...)* @f to i16 (i32)*)(i32 [[D_SROA_0_0]])
-; CHECK-NEXT:    [[TMP1]] = zext i16 [[CALL]] to i32
+; CHECK-NEXT:    [[TMP0]] = zext i16 [[CALL]] to i32
 ; CHECK-NEXT:    br label [[FOR_COND_BACKEDGE]]
 ;
 entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.cond.backedge, %entry
   %d.sroa.0.0 = phi i16 [ 30, %entry ], [ %d.sroa.0.0.be, %for.cond.backedge ]
   %tobool = icmp eq i16 %d.sroa.0.0, 0

llvm/test/Transforms/TypePromotion/ARM/casts.ll

 ; CHECK-NEXT:    [[TMP0:%.*]] = load i8, i8* [[__SIZE__I_I_I_I]], align 4
 ; CHECK-NEXT:    [[TMP1:%.*]] = zext i8 [[TMP0]] to i32
 ; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], 1
 ; CHECK-NEXT:    [[TOBOOL_I_I_I_I:%.*]] = icmp eq i32 [[TMP2]], 0
 ; CHECK-NEXT:    [[__SIZE__I5_I_I:%.*]] = getelementptr inbounds i32*, i32** [[__STR]], i32 [[__N1:%.*]]
 ; CHECK-NEXT:    [[CAST:%.*]] = bitcast i32** [[__SIZE__I5_I_I]] to i32*
 ; CHECK-NEXT:    [[TMP3:%.*]] = load i32, i32* [[CAST]], align 4
 ; CHECK-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP1]], 1
-; CHECK-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8
 ; CHECK-NEXT:    [[COND_I_I:%.*]] = select i1 [[TOBOOL_I_I_I_I]], i32 [[TMP4]], i32 [[TMP3]]
 ; CHECK-NEXT:    [[__SIZE__I_I_I_I_I:%.*]] = bitcast i32* [[THIS:%.*]] to i8*
-; CHECK-NEXT:    [[TMP6:%.*]] = load i8, i8* [[__SIZE__I_I_I_I_I]], align 4
-; CHECK-NEXT:    [[TMP7:%.*]] = zext i8 [[TMP6]] to i32
-; CHECK-NEXT:    [[TMP8:%.*]] = and i32 [[TMP7]], 1
-; CHECK-NEXT:    [[TOBOOL_I_I_I_I_I:%.*]] = icmp eq i32 [[TMP8]], 0
-; CHECK-NEXT:    [[TMP9:%.*]] = getelementptr inbounds i8, i8* [[__SIZE__I_I_I_I]], i32 [[__POS1:%.*]]
-; CHECK-NEXT:    [[TMP10:%.*]] = getelementptr inbounds i8, i8* [[__SIZE__I_I_I_I]], i32 [[__POS2:%.*]]
-; CHECK-NEXT:    [[RES:%.*]] = select i1 [[TOBOOL_I_I_I_I_I]], i8* [[TMP9]], i8* [[TMP10]]
+; CHECK-NEXT:    [[TMP5:%.*]] = load i8, i8* [[__SIZE__I_I_I_I_I]], align 4
+; CHECK-NEXT:    [[TMP6:%.*]] = zext i8 [[TMP5]] to i32
+; CHECK-NEXT:    [[TMP7:%.*]] = and i32 [[TMP6]], 1
+; CHECK-NEXT:    [[TOBOOL_I_I_I_I_I:%.*]] = icmp eq i32 [[TMP7]], 0
+; CHECK-NEXT:    [[TMP8:%.*]] = getelementptr inbounds i8, i8* [[__SIZE__I_I_I_I]], i32 [[__POS1:%.*]]
+; CHECK-NEXT:    [[TMP9:%.*]] = getelementptr inbounds i8, i8* [[__SIZE__I_I_I_I]], i32 [[__POS2:%.*]]
+; CHECK-NEXT:    [[RES:%.*]] = select i1 [[TOBOOL_I_I_I_I_I]], i8* [[TMP8]], i8* [[TMP9]]
 ; CHECK-NEXT:    ret i8* [[RES]]
 ;
 entry:
   %__size_.i.i.i.i = bitcast i32** %__str to i8*
   %0 = load i8, i8* %__size_.i.i.i.i, align 4
   %1 = and i8 %0, 1
   %tobool.i.i.i.i = icmp eq i8 %1, 0
   %__size_.i5.i.i = getelementptr inbounds i32*, i32** %__str, i32 %__n1

 ; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i32 [[TMP1]], 8
 ; CHECK-NEXT:    [[NARROW:%.*]] = select i1 [[CMP]], i32 [[TMP1]], i32 0
 ; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[NARROW]], 255
 ; CHECK-NEXT:    [[TMP3:%.*]] = load i8, i8* [[B:%.*]], align 1
 ; CHECK-NEXT:    [[TMP4:%.*]] = zext i8 [[TMP3]] to i32
 ; CHECK-NEXT:    [[OR:%.*]] = or i32 [[TMP4]], [[TMP2]]
 ; CHECK-NEXT:    [[TMP5:%.*]] = trunc i32 [[OR]] to i8
 ; CHECK-NEXT:    store i8 [[TMP5]], i8* [[B]], align 1
-; CHECK-NEXT:    [[TMP6:%.*]] = trunc i32 [[OR]] to i8
 ; CHECK-NEXT:    ret i32 [[OR]]
 ;
 entry:
   %0 = load i16, i16* %a, align 2
   %cmp = icmp ugt i16 %0, 8
   %narrow = select i1 %cmp, i16 %0, i16 0
   %cond = trunc i16 %narrow to i8
   %1 = load i8, i8* %b, align 1

 ; CHECK-NEXT:    [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2
 ; CHECK-NEXT:    [[TMP1:%.*]] = zext i16 [[TMP0]] to i32
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[TMP1]], 0
 ; CHECK-NEXT:    br i1 [[CMP]], label [[COND_END:%.*]], label [[COND_FALSE:%.*]]
 ; CHECK:       cond.false:
 ; CHECK-NEXT:    [[TMP2:%.*]] = urem i32 535, [[TMP1]]
 ; CHECK-NEXT:    [[TMP3:%.*]] = and i32 [[TMP2]], 255
 ; CHECK-NEXT:    [[TMP4:%.*]] = udiv i32 [[TMP3]], 3
-; CHECK-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8
 ; CHECK-NEXT:    br label [[COND_END]]
 ; CHECK:       cond.end:
 ; CHECK-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP4]], [[COND_FALSE]] ], [ 0, [[ENTRY:%.*]] ]
 ; CHECK-NEXT:    ret i32 [[COND]]
 ;
 entry:
   %0 = load i16, i16* %a
   %cmp = icmp eq i16 %0, 0