[DAG] Ensure Legal BUILD_VECTOR elements types in shuffle->And combine

[dmgreen]

Summary

D129150 added a combine from shuffles to And that creates a BUILD_VECTOR of constant elements. We need to ensure that the elements are of a legal type, to prevent asserts during lowering.

Fixes #56970.

[RKSimon]

LGTM

llvm/test/CodeGen/ARM/vector-store.ll

401

Please can you add a comment referencing it fixes PR56970?

[RKSimon]

@dmgreen Please can you take a look at this breakage: https://lab.llvm.org/buildbot/#/builders/141/builds/284

[dmgreen]

Yeah I will take a look. It doesn't looks like the same error is happening on trunk? At least I see a different error in https://lab.llvm.org/buildbot/#/builders/16/builds/33479.

[RKSimon]

In D131350#3722669, @dmgreen wrote:

Yeah I will take a look. It doesn't looks like the same error is happening on trunk? At least I see a different error in https://lab.llvm.org/buildbot/#/builders/16/builds/33479.

Yeah - I reported that one as well: https://github.com/llvm/llvm-project/issues/57149

Mondays............

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

if (!IsInLaneMask &&
         (!DemandedLHS.isNullValue() || !DemandedRHS.isNullValue()) &&
         (DemandedLHS.isNullValue() ||
          DAG.MaskedVectorIsZero(N0, DemandedLHS)) &&
         (DemandedRHS.isNullValue() ||
          DAG.MaskedVectorIsZero(N1, DemandedRHS))) {
       SDLoc DL(N);
       EVT IntVT = VT.changeVectorElementTypeToInteger();
       EVT IntSVT = VT.getVectorElementType().changeTypeToInteger();
+      IntSVT = TLI.getTypeToTransformTo(*DAG.getContext(), IntSVT);
       SDValue ZeroElt = DAG.getConstant(0, DL, IntSVT);
       SDValue AllOnesElt = DAG.getAllOnesConstant(DL, IntSVT);
       SmallVector<SDValue, 16> AndMask(NumElts, DAG.getUNDEF(IntSVT));
       for (int I = 0; I != (int)NumElts; ++I)
         if (0 <= Mask[I])
           AndMask[I] = Mask[I] == I ? AllOnesElt : ZeroElt;
 
       // See if a clear mask is legal instead of going via

llvm/test/CodeGen/ARM/vector-store.ll

 ; CHECK-NEXT:    vst1.32 {d16, d17}, [r1], r0
 ; CHECK-NEXT:    mov r0, r1
 ; CHECK-NEXT:    bx lr
   %val = load <4 x i32>, <4 x i32>* %ptr.in
   store <4 x i32> %val, <4 x i32>* %ptr.out
   %next = getelementptr <4 x i32>, <4 x i32>* %ptr.out, i32 2
   ret <4 x i32>* %next
 }
+
+; PR56970
+define void @v3i8store(<3 x i8> *%p) {
+; CHECK-LABEL: v3i8store:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    sub sp, #4
+; CHECK-NEXT:    vmov.i32 d16, #0xff
+; CHECK-NEXT:    mov r1, sp
+; CHECK-NEXT:    vmov.i32 d17, #0x0
+; CHECK-NEXT:    movs r2, #0
+; CHECK-NEXT:    vand d16, d17, d16
+; CHECK-NEXT:    vst1.32 {d16[0]}, [r1:32]
+; CHECK-NEXT:    vld1.32 {d16[0]}, [r1:32]
+; CHECK-NEXT:    vmovl.u16 q8, d16
+; CHECK-NEXT:    strb r2, [r0, #2]
+; CHECK-NEXT:    vmov.32 r1, d16[0]
+; CHECK-NEXT:    strh r1, [r0]
+; CHECK-NEXT:    add sp, #4
+; CHECK-NEXT:    bx lr
+  store <3 x i8> zeroinitializer, <3 x i8> *%p, align 4
+  ret void
+}