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[RISCV] Reorder (and/or/xor (shl X, C1), C2) if we can form ANDI/ORI/XORI.
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Authored by craig.topper on Jul 26 2022, 5:58 PM.

Details

Summary

InstCombine and DAGCombine prefer to keep shl before binops.

This patch teaches isel to convert to (shl (and/or/xor X, C1 >> C2), C2)
if (C1 >> C2) is a simm12. The idea was taken from X86's isel code.

There's a special case implemented for a sext_inreg between the
shift and the binop.

Diff Detail

Event Timeline

craig.topper created this revision.Jul 26 2022, 5:58 PM
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craig.topper requested review of this revision.Jul 26 2022, 5:58 PM
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luismarques accepted this revision.Jul 27 2022, 3:19 PM

LGTM. Nice!

This revision is now accepted and ready to land.Jul 27 2022, 3:19 PM
This revision was landed with ongoing or failed builds.Jul 27 2022, 5:41 PM
This revision was automatically updated to reflect the committed changes.