[X86] Use generic tuning for "x86-64" if "tune-cpu" is not specified

[pengfei]

Summary

This is an alternative to D129154. See discussions on https://discourse.llvm.org/t/fast-scalar-fsqrt-tuning-in-x86/63605

[craig.topper]

This comment in X86.td is wrong now

// NOTE: As a default tuning, "generic" aims to produce code optimized for the   
// most common X86 processors. The tunings might be changed over time. It is     
// recommended to use "x86-64" in lit tests for consistency.

llvm/lib/Target/X86/X86TargetMachine.cpp

257–262

Probably worth a comment here

[andrew.w.kaylor]

This patch will make my proposed change in D129154 unnecessary, but can you copy the sqrt-fastmath-tunecpu-attr.ll (with a change to the @f32_tune_x86_64 test to reflect the current tuning when "tune-cpu"="x86-64" is used)?

[pengfei]

Address comments form Craig and Andy. Thanks!

[craig.topper]

LGTM

[pengfei]

Thanks Craig!

llvm/lib/Target/X86/X86.td

 
 // NOTE: CMPXCHG8B is here for legacy compatibility so that it is only disabled
 // if i386/i486 is specifically requested.
 // NOTE: 64Bit is here as "generic" is the default llc CPU. The X86Subtarget
 // constructor checks that any CPU used in 64-bit mode has FeatureX86_64
 // enabled. It has no effect on code generation.
 // NOTE: As a default tuning, "generic" aims to produce code optimized for the
 // most common X86 processors. The tunings might be changed over time. It is
-// recommended to use "x86-64" in lit tests for consistency.
+// recommended to use "tune-cpu"="x86-64" in function attribute for consistency.
 def : ProcModel<"generic", SandyBridgeModel,
                 [FeatureX87, FeatureCX8, FeatureX86_64],
                 [TuningSlow3OpsLEA,
                  TuningSlowDivide64,
                  TuningMacroFusion,
                  TuningFastScalarFSQRT,
                  TuningFast15ByteNOP,
                  TuningInsertVZEROUPPER]>;

llvm/lib/Target/X86/X86TargetMachine.cpp

 const X86Subtarget *
 X86TargetMachine::getSubtargetImpl(const Function &F) const {
   Attribute CPUAttr = F.getFnAttribute("target-cpu");
   Attribute TuneAttr = F.getFnAttribute("tune-cpu");
   Attribute FSAttr = F.getFnAttribute("target-features");
 
   StringRef CPU =
       CPUAttr.isValid() ? CPUAttr.getValueAsString() : (StringRef)TargetCPU;
-  StringRef TuneCPU =
-      TuneAttr.isValid() ? TuneAttr.getValueAsString() : (StringRef)CPU;
+  // "x86-64" is a default target setting for many front ends. In these cases,
+  // they actually request for "generic" tuning unless the "tune-cpu" was
+  // specified.
+  StringRef TuneCPU = TuneAttr.isValid() ? TuneAttr.getValueAsString()
+                      : CPU == "x86-64"  ? "generic"
+                                         : (StringRef)CPU;
   StringRef FS =
       FSAttr.isValid() ? FSAttr.getValueAsString() : (StringRef)TargetFS;
 
   SmallString<512> Key;
   // The additions here are ordered so that the definitely short strings are
   // added first so we won't exceed the small size. We append the
   // much longer FS string at the end so that we only heap allocate at most
   // one time.

llvm/test/CodeGen/X86/pow.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64 | FileCheck %s
 
 declare float @llvm.pow.f32(float, float)
 declare <4 x float> @llvm.pow.v4f32(<4 x float>, <4 x float>)
 
 declare double @llvm.pow.f64(double, double)
 declare <2 x double> @llvm.pow.v2f64(<2 x double>, <2 x double>)
 
 declare x86_fp80 @llvm.pow.f80(x86_fp80, x86_fp80)
 
 define float @pow_f32_one_fourth_fmf_ieee(float %x) nounwind {
 ; CHECK-LABEL: pow_f32_one_fourth_fmf_ieee:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rsqrtss %xmm0, %xmm1
-; CHECK-NEXT:    movaps %xmm0, %xmm3
-; CHECK-NEXT:    mulss %xmm1, %xmm3
-; CHECK-NEXT:    movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
-; CHECK-NEXT:    movaps %xmm3, %xmm4
-; CHECK-NEXT:    mulss %xmm2, %xmm4
-; CHECK-NEXT:    mulss %xmm1, %xmm3
-; CHECK-NEXT:    movss {{.*#+}} xmm5 = mem[0],zero,zero,zero
-; CHECK-NEXT:    addss %xmm5, %xmm3
-; CHECK-NEXT:    mulss %xmm4, %xmm3
-; CHECK-NEXT:    movaps {{.*#+}} xmm1 = [NaN,NaN,NaN,NaN]
-; CHECK-NEXT:    andps %xmm1, %xmm0
-; CHECK-NEXT:    movss {{.*#+}} xmm4 = mem[0],zero,zero,zero
-; CHECK-NEXT:    cmpltss %xmm4, %xmm0
-; CHECK-NEXT:    andnps %xmm3, %xmm0
-; CHECK-NEXT:    xorps %xmm3, %xmm3
-; CHECK-NEXT:    rsqrtss %xmm0, %xmm3
-; CHECK-NEXT:    andps %xmm0, %xmm1
-; CHECK-NEXT:    mulss %xmm3, %xmm0
-; CHECK-NEXT:    mulss %xmm0, %xmm2
-; CHECK-NEXT:    mulss %xmm3, %xmm0
-; CHECK-NEXT:    addss %xmm5, %xmm0
-; CHECK-NEXT:    mulss %xmm2, %xmm0
-; CHECK-NEXT:    cmpltss %xmm4, %xmm1
-; CHECK-NEXT:    andnps %xmm0, %xmm1
-; CHECK-NEXT:    movaps %xmm1, %xmm0
+; CHECK-NEXT:    sqrtss %xmm0, %xmm0
+; CHECK-NEXT:    sqrtss %xmm0, %xmm0
 ; CHECK-NEXT:    retq
   %r = call nsz ninf afn float @llvm.pow.f32(float %x, float 2.5e-01)
   ret float %r
 }
 
 define float @pow_f32_one_fourth_fmf_daz(float %x) #0 {
 ; CHECK-LABEL: pow_f32_one_fourth_fmf_daz:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rsqrtss %xmm0, %xmm1
-; CHECK-NEXT:    movaps %xmm0, %xmm2
-; CHECK-NEXT:    mulss %xmm1, %xmm2
-; CHECK-NEXT:    movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
-; CHECK-NEXT:    movaps %xmm2, %xmm4
-; CHECK-NEXT:    mulss %xmm3, %xmm4
-; CHECK-NEXT:    mulss %xmm1, %xmm2
-; CHECK-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; CHECK-NEXT:    addss %xmm1, %xmm2
-; CHECK-NEXT:    mulss %xmm4, %xmm2
-; CHECK-NEXT:    xorps %xmm4, %xmm4
-; CHECK-NEXT:    cmpeqss %xmm4, %xmm0
-; CHECK-NEXT:    andnps %xmm2, %xmm0
-; CHECK-NEXT:    xorps %xmm2, %xmm2
-; CHECK-NEXT:    rsqrtss %xmm0, %xmm2
-; CHECK-NEXT:    movaps %xmm0, %xmm5
-; CHECK-NEXT:    mulss %xmm2, %xmm5
-; CHECK-NEXT:    mulss %xmm5, %xmm3
-; CHECK-NEXT:    mulss %xmm2, %xmm5
-; CHECK-NEXT:    addss %xmm1, %xmm5
-; CHECK-NEXT:    mulss %xmm3, %xmm5
-; CHECK-NEXT:    cmpeqss %xmm4, %xmm0
-; CHECK-NEXT:    andnps %xmm5, %xmm0
+; CHECK-NEXT:    sqrtss %xmm0, %xmm0
+; CHECK-NEXT:    sqrtss %xmm0, %xmm0
 ; CHECK-NEXT:    retq
   %r = call nsz ninf afn float @llvm.pow.f32(float %x, float 2.5e-01)
   ret float %r
 }
 
 define double @pow_f64_one_fourth_fmf(double %x) nounwind {
 ; CHECK-LABEL: pow_f64_one_fourth_fmf:
 ; CHECK:       # %bb.0:

llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=nehalem     | FileCheck %s --check-prefixes=NHM
 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=sandybridge | FileCheck %s --check-prefixes=FAST-SCALAR,SNB
 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=broadwell   | FileCheck %s --check-prefixes=FAST-SCALAR,BDW
 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=skylake     | FileCheck %s --check-prefixes=FAST-SCALAR,FAST-VECTOR
 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver1      | FileCheck %s --check-prefixes=FAST-SCALAR,FAST-VECTOR
 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver3      | FileCheck %s --check-prefixes=FAST-SCALAR,FAST-VECTOR
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64      | FileCheck %s --check-prefixes=X86-64
 
 define float @f32_no_daz(float %f) #0 {
 ; NHM-LABEL: f32_no_daz:
 ; NHM:       # %bb.0:
 ; NHM-NEXT:    rsqrtss %xmm0, %xmm1
 ; NHM-NEXT:    movaps %xmm0, %xmm2
 ; NHM-NEXT:    mulss %xmm1, %xmm2
 ; NHM-NEXT:    movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
 ; NHM-NEXT:    mulss %xmm2, %xmm3
 ; NHM-NEXT:    mulss %xmm1, %xmm2
 ; NHM-NEXT:    addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
 ; NHM-NEXT:    mulss %xmm3, %xmm2
 ; NHM-NEXT:    andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
 ; NHM-NEXT:    cmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
 ; NHM-NEXT:    andnps %xmm2, %xmm0
 ; NHM-NEXT:    retq
 ;
 ; FAST-SCALAR-LABEL: f32_no_daz:
 ; FAST-SCALAR:       # %bb.0:
 ; FAST-SCALAR-NEXT:    vsqrtss %xmm0, %xmm0, %xmm0
 ; FAST-SCALAR-NEXT:    retq
+;
+; X86-64-LABEL: f32_no_daz:
+; X86-64:       # %bb.0:
+; X86-64-NEXT:    sqrtss %xmm0, %xmm0
+; X86-64-NEXT:    retq
   %call = tail call fast float @llvm.sqrt.f32(float %f) #2
   ret float %call
 }
 
 define <4 x float> @v4f32_no_daz(<4 x float> %f) #0 {
 ; NHM-LABEL: v4f32_no_daz:
 ; NHM:       # %bb.0:
 ; NHM-NEXT:    rsqrtps %xmm0, %xmm1

 ; BDW-NEXT:    vcmpleps %xmm0, %xmm2, %xmm0
 ; BDW-NEXT:    vandps %xmm1, %xmm0, %xmm0
 ; BDW-NEXT:    retq
 ;
 ; FAST-VECTOR-LABEL: v4f32_no_daz:
 ; FAST-VECTOR:       # %bb.0:
 ; FAST-VECTOR-NEXT:    vsqrtps %xmm0, %xmm0
 ; FAST-VECTOR-NEXT:    retq
+;
+; X86-64-LABEL: v4f32_no_daz:
+; X86-64:       # %bb.0:
+; X86-64-NEXT:    rsqrtps %xmm0, %xmm1
+; X86-64-NEXT:    movaps %xmm0, %xmm2
+; X86-64-NEXT:    mulps %xmm1, %xmm2
+; X86-64-NEXT:    movaps {{.*#+}} xmm3 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
+; X86-64-NEXT:    mulps %xmm2, %xmm3
+; X86-64-NEXT:    mulps %xmm1, %xmm2
+; X86-64-NEXT:    addps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
+; X86-64-NEXT:    mulps %xmm3, %xmm2
+; X86-64-NEXT:    andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X86-64-NEXT:    movaps {{.*#+}} xmm1 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38]
+; X86-64-NEXT:    cmpleps %xmm0, %xmm1
+; X86-64-NEXT:    andps %xmm2, %xmm1
+; X86-64-NEXT:    movaps %xmm1, %xmm0
+; X86-64-NEXT:    retq
   %call = tail call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> %f) #2
   ret <4 x float> %call
 }
 
 define <8 x float> @v8f32_no_daz(<8 x float> %f) #0 {
 ; NHM-LABEL: v8f32_no_daz:
 ; NHM:       # %bb.0:
 ; NHM-NEXT:    rsqrtps %xmm0, %xmm2

 ; BDW-NEXT:    vcmpleps %ymm0, %ymm2, %ymm0
 ; BDW-NEXT:    vandps %ymm1, %ymm0, %ymm0
 ; BDW-NEXT:    retq
 ;
 ; FAST-VECTOR-LABEL: v8f32_no_daz:
 ; FAST-VECTOR:       # %bb.0:
 ; FAST-VECTOR-NEXT:    vsqrtps %ymm0, %ymm0
 ; FAST-VECTOR-NEXT:    retq
+;
+; X86-64-LABEL: v8f32_no_daz:
+; X86-64:       # %bb.0:
+; X86-64-NEXT:    rsqrtps %xmm0, %xmm2
+; X86-64-NEXT:    movaps %xmm0, %xmm4
+; X86-64-NEXT:    mulps %xmm2, %xmm4
+; X86-64-NEXT:    movaps {{.*#+}} xmm5 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
+; X86-64-NEXT:    movaps %xmm4, %xmm3
+; X86-64-NEXT:    mulps %xmm5, %xmm3
+; X86-64-NEXT:    mulps %xmm2, %xmm4
+; X86-64-NEXT:    movaps {{.*#+}} xmm6 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0]
+; X86-64-NEXT:    addps %xmm6, %xmm4
+; X86-64-NEXT:    mulps %xmm3, %xmm4
+; X86-64-NEXT:    movaps {{.*#+}} xmm7 = [NaN,NaN,NaN,NaN]
+; X86-64-NEXT:    andps %xmm7, %xmm0
+; X86-64-NEXT:    movaps {{.*#+}} xmm2 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38]
+; X86-64-NEXT:    movaps %xmm2, %xmm3
+; X86-64-NEXT:    cmpleps %xmm0, %xmm3
+; X86-64-NEXT:    andps %xmm4, %xmm3
+; X86-64-NEXT:    rsqrtps %xmm1, %xmm0
+; X86-64-NEXT:    movaps %xmm1, %xmm4
+; X86-64-NEXT:    mulps %xmm0, %xmm4
+; X86-64-NEXT:    mulps %xmm4, %xmm5
+; X86-64-NEXT:    mulps %xmm0, %xmm4
+; X86-64-NEXT:    addps %xmm6, %xmm4
+; X86-64-NEXT:    mulps %xmm5, %xmm4
+; X86-64-NEXT:    andps %xmm7, %xmm1
+; X86-64-NEXT:    cmpleps %xmm1, %xmm2
+; X86-64-NEXT:    andps %xmm4, %xmm2
+; X86-64-NEXT:    movaps %xmm3, %xmm0
+; X86-64-NEXT:    movaps %xmm2, %xmm1
+; X86-64-NEXT:    retq
   %call = tail call fast <8 x float> @llvm.sqrt.v8f32(<8 x float> %f) #2
   ret <8 x float> %call
 }
 
 ; Repeat all tests with denorms-as-zero enabled.
 
 define float @f32_daz(float %f) #1 {
 ; NHM-LABEL: f32_daz:

 ; NHM-NEXT:    cmpeqss %xmm1, %xmm0
 ; NHM-NEXT:    andnps %xmm2, %xmm0
 ; NHM-NEXT:    retq
 ;
 ; FAST-SCALAR-LABEL: f32_daz:
 ; FAST-SCALAR:       # %bb.0:
 ; FAST-SCALAR-NEXT:    vsqrtss %xmm0, %xmm0, %xmm0
 ; FAST-SCALAR-NEXT:    retq
+;
+; X86-64-LABEL: f32_daz:
+; X86-64:       # %bb.0:
+; X86-64-NEXT:    sqrtss %xmm0, %xmm0
+; X86-64-NEXT:    retq
   %call = tail call fast float @llvm.sqrt.f32(float %f) #2
   ret float %call
 }
 
 define <4 x float> @v4f32_daz(<4 x float> %f) #1 {
 ; NHM-LABEL: v4f32_daz:
 ; NHM:       # %bb.0:
 ; NHM-NEXT:    rsqrtps %xmm0, %xmm1

 ; BDW-NEXT:    vcmpneqps %xmm2, %xmm0, %xmm0
 ; BDW-NEXT:    vandps %xmm1, %xmm0, %xmm0
 ; BDW-NEXT:    retq
 ;
 ; FAST-VECTOR-LABEL: v4f32_daz:
 ; FAST-VECTOR:       # %bb.0:
 ; FAST-VECTOR-NEXT:    vsqrtps %xmm0, %xmm0
 ; FAST-VECTOR-NEXT:    retq
+;
+; X86-64-LABEL: v4f32_daz:
+; X86-64:       # %bb.0:
+; X86-64-NEXT:    rsqrtps %xmm0, %xmm1
+; X86-64-NEXT:    movaps %xmm0, %xmm2
+; X86-64-NEXT:    mulps %xmm1, %xmm2
+; X86-64-NEXT:    movaps {{.*#+}} xmm3 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
+; X86-64-NEXT:    mulps %xmm2, %xmm3
+; X86-64-NEXT:    mulps %xmm1, %xmm2
+; X86-64-NEXT:    addps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
+; X86-64-NEXT:    mulps %xmm3, %xmm2
+; X86-64-NEXT:    xorps %xmm1, %xmm1
+; X86-64-NEXT:    cmpneqps %xmm1, %xmm0
+; X86-64-NEXT:    andps %xmm2, %xmm0
+; X86-64-NEXT:    retq
   %call = tail call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> %f) #2
   ret <4 x float> %call
 }
 
 define <8 x float> @v8f32_daz(<8 x float> %f) #1 {
 ; NHM-LABEL: v8f32_daz:
 ; NHM:       # %bb.0:
 ; NHM-NEXT:    rsqrtps %xmm0, %xmm2

 ; BDW-NEXT:    vcmpneqps %ymm2, %ymm0, %ymm0
 ; BDW-NEXT:    vandps %ymm1, %ymm0, %ymm0
 ; BDW-NEXT:    retq
 ;
 ; FAST-VECTOR-LABEL: v8f32_daz:
 ; FAST-VECTOR:       # %bb.0:
 ; FAST-VECTOR-NEXT:    vsqrtps %ymm0, %ymm0
 ; FAST-VECTOR-NEXT:    retq
+;
+; X86-64-LABEL: v8f32_daz:
+; X86-64:       # %bb.0:
+; X86-64-NEXT:    rsqrtps %xmm0, %xmm2
+; X86-64-NEXT:    movaps %xmm0, %xmm3
+; X86-64-NEXT:    mulps %xmm2, %xmm3
+; X86-64-NEXT:    movaps {{.*#+}} xmm4 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
+; X86-64-NEXT:    movaps %xmm3, %xmm5
+; X86-64-NEXT:    mulps %xmm4, %xmm5
+; X86-64-NEXT:    mulps %xmm2, %xmm3
+; X86-64-NEXT:    movaps {{.*#+}} xmm2 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0]
+; X86-64-NEXT:    addps %xmm2, %xmm3
+; X86-64-NEXT:    mulps %xmm5, %xmm3
+; X86-64-NEXT:    xorps %xmm5, %xmm5
+; X86-64-NEXT:    cmpneqps %xmm5, %xmm0
+; X86-64-NEXT:    andps %xmm3, %xmm0
+; X86-64-NEXT:    rsqrtps %xmm1, %xmm3
+; X86-64-NEXT:    movaps %xmm1, %xmm6
+; X86-64-NEXT:    mulps %xmm3, %xmm6
+; X86-64-NEXT:    mulps %xmm6, %xmm4
+; X86-64-NEXT:    mulps %xmm3, %xmm6
+; X86-64-NEXT:    addps %xmm2, %xmm6
+; X86-64-NEXT:    mulps %xmm4, %xmm6
+; X86-64-NEXT:    cmpneqps %xmm5, %xmm1
+; X86-64-NEXT:    andps %xmm6, %xmm1
+; X86-64-NEXT:    retq
   %call = tail call fast <8 x float> @llvm.sqrt.v8f32(<8 x float> %f) #2
   ret <8 x float> %call
 }
 
 declare float @llvm.sqrt.f32(float) #2
 declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) #2
 declare <8 x float> @llvm.sqrt.v8f32(<8 x float>) #2
 
 attributes #0 = { "denormal-fp-math"="ieee,ieee" }
 attributes #1 = { "denormal-fp-math"="ieee,preserve-sign" }
 attributes #2 = { nounwind readnone }

llvm/test/CodeGen/X86/sqrt-fastmath-tunecpu-attr.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=x86_64-- < %s | FileCheck %s
+
+define float @f32_tune_nhm(float %f) #0 {
+; CHECK-LABEL: f32_tune_nhm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    rsqrtss %xmm0, %xmm1
+; CHECK-NEXT:    movaps %xmm0, %xmm2
+; CHECK-NEXT:    mulss %xmm1, %xmm2
+; CHECK-NEXT:    movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
+; CHECK-NEXT:    mulss %xmm2, %xmm3
+; CHECK-NEXT:    mulss %xmm1, %xmm2
+; CHECK-NEXT:    addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
+; CHECK-NEXT:    mulss %xmm3, %xmm2
+; CHECK-NEXT:    andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT:    cmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT:    andnps %xmm2, %xmm0
+; CHECK-NEXT:    retq
+  %call = tail call fast float @llvm.sqrt.f32(float %f)
+  ret float %call
+}
+
+define float @f32_no_tune(float %f) #1 {
+; CHECK-LABEL: f32_no_tune:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sqrtss %xmm0, %xmm0
+; CHECK-NEXT:    retq
+  %call = tail call fast float @llvm.sqrt.f32(float %f)
+  ret float %call
+}
+
+define float @f32_tune_generic(float %f) #2 {
+; CHECK-LABEL: f32_tune_generic:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sqrtss %xmm0, %xmm0
+; CHECK-NEXT:    retq
+  %call = tail call fast float @llvm.sqrt.f32(float %f)
+  ret float %call
+}
+
+define float @f32_tune_x86_64(float %f) #3 {
+; CHECK-LABEL: f32_tune_x86_64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    rsqrtss %xmm0, %xmm1
+; CHECK-NEXT:    movaps %xmm0, %xmm2
+; CHECK-NEXT:    mulss %xmm1, %xmm2
+; CHECK-NEXT:    movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
+; CHECK-NEXT:    mulss %xmm2, %xmm3
+; CHECK-NEXT:    mulss %xmm1, %xmm2
+; CHECK-NEXT:    addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
+; CHECK-NEXT:    mulss %xmm3, %xmm2
+; CHECK-NEXT:    andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT:    cmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT:    andnps %xmm2, %xmm0
+; CHECK-NEXT:    retq
+  %call = tail call fast float @llvm.sqrt.f32(float %f)
+  ret float %call
+}
+
+define float @f32_tune_snb(float %f) #4 {
+; CHECK-LABEL: f32_tune_snb:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sqrtss %xmm0, %xmm0
+; CHECK-NEXT:    retq
+  %call = tail call fast float @llvm.sqrt.f32(float %f)
+  ret float %call
+}
+
+define float @f32_target_snb_tune_snb(float %f) #5 {
+; CHECK-LABEL: f32_target_snb_tune_snb:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsqrtss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT:    retq
+  %call = tail call fast float @llvm.sqrt.f32(float %f)
+  ret float %call
+}
+
+declare float @llvm.sqrt.f32(float)
+
+attributes #0 = { "target-cpu"="x86-64" "tune-cpu"="nehalem" }
+attributes #1 = { "target-cpu"="x86-64" }
+attributes #2 = { "target-cpu"="x86-64" "tune-cpu"="generic" }
+attributes #3 = { "target-cpu"="x86-64" "tune-cpu"="x86-64" }
+attributes #4 = { "target-cpu"="x86-64" "tune-cpu"="sandybridge" }
+attributes #5 = { "target-cpu"="sandybridge" "tune-cpu"="sandybridge" }

llvm/test/CodeGen/X86/sqrt-fastmath.ll

 ; AVX-NEXT:    retq
   %call = tail call float @__sqrtf_finite(float %f) #2
   ret float %call
 }
 
 define float @finite_f32_estimate_ieee_ninf(float %f) #1 {
 ; SSE-LABEL: finite_f32_estimate_ieee_ninf:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    rsqrtss %xmm0, %xmm1
-; SSE-NEXT:    movaps %xmm0, %xmm2
-; SSE-NEXT:    mulss %xmm1, %xmm2
-; SSE-NEXT:    movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
-; SSE-NEXT:    mulss %xmm2, %xmm3
-; SSE-NEXT:    mulss %xmm1, %xmm2
-; SSE-NEXT:    addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
-; SSE-NEXT:    mulss %xmm3, %xmm2
-; SSE-NEXT:    andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE-NEXT:    cmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE-NEXT:    andnps %xmm2, %xmm0
+; SSE-NEXT:    sqrtss %xmm0, %xmm0
 ; SSE-NEXT:    retq
 ;
-; AVX1-LABEL: finite_f32_estimate_ieee_ninf:
-; AVX1:       # %bb.0:
-; AVX1-NEXT:    vrsqrtss %xmm0, %xmm0, %xmm1
-; AVX1-NEXT:    vmulss %xmm1, %xmm0, %xmm2
-; AVX1-NEXT:    vmulss %xmm1, %xmm2, %xmm1
-; AVX1-NEXT:    vaddss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
-; AVX1-NEXT:    vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
-; AVX1-NEXT:    vmulss %xmm1, %xmm2, %xmm1
-; AVX1-NEXT:    vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX1-NEXT:    vcmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX1-NEXT:    vandnps %xmm1, %xmm0, %xmm0
-; AVX1-NEXT:    retq
-;
-; AVX512-LABEL: finite_f32_estimate_ieee_ninf:
-; AVX512:       # %bb.0:
-; AVX512-NEXT:    vrsqrtss %xmm0, %xmm0, %xmm1
-; AVX512-NEXT:    vbroadcastss {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
-; AVX512-NEXT:    vandps %xmm2, %xmm0, %xmm2
-; AVX512-NEXT:    vmulss %xmm1, %xmm0, %xmm0
-; AVX512-NEXT:    vfmadd213ss {{.*#+}} xmm1 = (xmm0 * xmm1) + mem
-; AVX512-NEXT:    vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX512-NEXT:    vcmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %k1
-; AVX512-NEXT:    vmulss %xmm1, %xmm0, %xmm0
-; AVX512-NEXT:    vxorps %xmm1, %xmm1, %xmm1
-; AVX512-NEXT:    vmovss %xmm1, %xmm0, %xmm0 {%k1}
-; AVX512-NEXT:    retq
+; AVX-LABEL: finite_f32_estimate_ieee_ninf:
+; AVX:       # %bb.0:
+; AVX-NEXT:    vsqrtss %xmm0, %xmm0, %xmm0
+; AVX-NEXT:    retq
   %call = tail call ninf afn float @__sqrtf_finite(float %f) #2
   ret float %call
 }
 
 define float @finite_f32_estimate_daz(float %f) #4 {
 ; SSE-LABEL: finite_f32_estimate_daz:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    sqrtss %xmm0, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: finite_f32_estimate_daz:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vsqrtss %xmm0, %xmm0, %xmm0
 ; AVX-NEXT:    retq
   %call = tail call float @__sqrtf_finite(float %f) #2
   ret float %call
 }
 
 define float @finite_f32_estimate_daz_ninf(float %f) #4 {
 ; SSE-LABEL: finite_f32_estimate_daz_ninf:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    rsqrtss %xmm0, %xmm1
-; SSE-NEXT:    movaps %xmm0, %xmm2
-; SSE-NEXT:    mulss %xmm1, %xmm2
-; SSE-NEXT:    movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
-; SSE-NEXT:    mulss %xmm2, %xmm3
-; SSE-NEXT:    mulss %xmm1, %xmm2
-; SSE-NEXT:    addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
-; SSE-NEXT:    mulss %xmm3, %xmm2
-; SSE-NEXT:    xorps %xmm1, %xmm1
-; SSE-NEXT:    cmpeqss %xmm1, %xmm0
-; SSE-NEXT:    andnps %xmm2, %xmm0
+; SSE-NEXT:    sqrtss %xmm0, %xmm0
 ; SSE-NEXT:    retq
 ;
-; AVX1-LABEL: finite_f32_estimate_daz_ninf:
-; AVX1:       # %bb.0:
-; AVX1-NEXT:    vrsqrtss %xmm0, %xmm0, %xmm1
-; AVX1-NEXT:    vmulss %xmm1, %xmm0, %xmm2
-; AVX1-NEXT:    vmulss %xmm1, %xmm2, %xmm1
-; AVX1-NEXT:    vaddss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
-; AVX1-NEXT:    vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
-; AVX1-NEXT:    vmulss %xmm1, %xmm2, %xmm1
-; AVX1-NEXT:    vxorps %xmm2, %xmm2, %xmm2
-; AVX1-NEXT:    vcmpeqss %xmm2, %xmm0, %xmm0
-; AVX1-NEXT:    vandnps %xmm1, %xmm0, %xmm0
-; AVX1-NEXT:    retq
-;
-; AVX512-LABEL: finite_f32_estimate_daz_ninf:
-; AVX512:       # %bb.0:
-; AVX512-NEXT:    vrsqrtss %xmm0, %xmm0, %xmm1
-; AVX512-NEXT:    vmulss %xmm1, %xmm0, %xmm2
-; AVX512-NEXT:    vfmadd213ss {{.*#+}} xmm1 = (xmm2 * xmm1) + mem
-; AVX512-NEXT:    vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
-; AVX512-NEXT:    vmulss %xmm1, %xmm2, %xmm1
-; AVX512-NEXT:    vxorps %xmm2, %xmm2, %xmm2
-; AVX512-NEXT:    vcmpeqss %xmm2, %xmm0, %k1
-; AVX512-NEXT:    vmovss %xmm2, %xmm1, %xmm1 {%k1}
-; AVX512-NEXT:    vmovaps %xmm1, %xmm0
-; AVX512-NEXT:    retq
+; AVX-LABEL: finite_f32_estimate_daz_ninf:
+; AVX:       # %bb.0:
+; AVX-NEXT:    vsqrtss %xmm0, %xmm0, %xmm0
+; AVX-NEXT:    retq
   %call = tail call ninf afn float @__sqrtf_finite(float %f) #2
   ret float %call
 }
 
 define x86_fp80 @finite_f80_no_estimate(x86_fp80 %ld) #0 {
 ; CHECK-LABEL: finite_f80_no_estimate:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fldt {{[0-9]+}}(%rsp)

 ; AVX-NEXT:    retq
   %call = tail call float @__sqrtf_finite(float %x) #2
   ret float %call
 }
 
 define float @sqrtf_check_denorms_ninf(float %x) #3 {
 ; SSE-LABEL: sqrtf_check_denorms_ninf:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    rsqrtss %xmm0, %xmm1
-; SSE-NEXT:    movaps %xmm0, %xmm2
-; SSE-NEXT:    mulss %xmm1, %xmm2
-; SSE-NEXT:    movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
-; SSE-NEXT:    mulss %xmm2, %xmm3
-; SSE-NEXT:    mulss %xmm1, %xmm2
-; SSE-NEXT:    addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
-; SSE-NEXT:    mulss %xmm3, %xmm2
-; SSE-NEXT:    andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE-NEXT:    cmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE-NEXT:    andnps %xmm2, %xmm0
+; SSE-NEXT:    sqrtss %xmm0, %xmm0
 ; SSE-NEXT:    retq
 ;
-; AVX1-LABEL: sqrtf_check_denorms_ninf:
-; AVX1:       # %bb.0:
-; AVX1-NEXT:    vrsqrtss %xmm0, %xmm0, %xmm1
-; AVX1-NEXT:    vmulss %xmm1, %xmm0, %xmm2
-; AVX1-NEXT:    vmulss %xmm1, %xmm2, %xmm1
-; AVX1-NEXT:    vaddss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
-; AVX1-NEXT:    vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
-; AVX1-NEXT:    vmulss %xmm1, %xmm2, %xmm1
-; AVX1-NEXT:    vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX1-NEXT:    vcmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX1-NEXT:    vandnps %xmm1, %xmm0, %xmm0
-; AVX1-NEXT:    retq
-;
-; AVX512-LABEL: sqrtf_check_denorms_ninf:
-; AVX512:       # %bb.0:
-; AVX512-NEXT:    vrsqrtss %xmm0, %xmm0, %xmm1
-; AVX512-NEXT:    vbroadcastss {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
-; AVX512-NEXT:    vandps %xmm2, %xmm0, %xmm2
-; AVX512-NEXT:    vmulss %xmm1, %xmm0, %xmm0
-; AVX512-NEXT:    vfmadd213ss {{.*#+}} xmm1 = (xmm0 * xmm1) + mem
-; AVX512-NEXT:    vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX512-NEXT:    vcmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %k1
-; AVX512-NEXT:    vmulss %xmm1, %xmm0, %xmm0
-; AVX512-NEXT:    vxorps %xmm1, %xmm1, %xmm1
-; AVX512-NEXT:    vmovss %xmm1, %xmm0, %xmm0 {%k1}
-; AVX512-NEXT:    retq
+; AVX-LABEL: sqrtf_check_denorms_ninf:
+; AVX:       # %bb.0:
+; AVX-NEXT:    vsqrtss %xmm0, %xmm0, %xmm0
+; AVX-NEXT:    retq
   %call = tail call ninf afn float @__sqrtf_finite(float %x) #2
   ret float %call
 }
 
 define <4 x float> @sqrt_v4f32_check_denorms(<4 x float> %x) #3 {
 ; SSE-LABEL: sqrt_v4f32_check_denorms:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    sqrtps %xmm0, %xmm0
; AVX512-NEXT:    retq
   %sqrt = tail call float @llvm.sqrt.f32(float %x)
   %div = fdiv fast float 1.0, %sqrt
   ret float %div
 }
 
 define float @f32_estimate2(float %x) #5 {
 ; SSE-LABEL: f32_estimate2:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    rsqrtss %xmm0, %xmm1
-; SSE-NEXT:    mulss %xmm0, %xmm1
-; SSE-NEXT:    andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE-NEXT:    cmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE-NEXT:    andnps %xmm1, %xmm0
+; SSE-NEXT:    sqrtss %xmm0, %xmm0
 ; SSE-NEXT:    retq
 ;
-; AVX1-LABEL: f32_estimate2:
-; AVX1:       # %bb.0:
-; AVX1-NEXT:    vrsqrtss %xmm0, %xmm0, %xmm1
-; AVX1-NEXT:    vmulss %xmm1, %xmm0, %xmm1
-; AVX1-NEXT:    vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX1-NEXT:    vcmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX1-NEXT:    vandnps %xmm1, %xmm0, %xmm0
-; AVX1-NEXT:    retq
-;
-; AVX512-LABEL: f32_estimate2:
-; AVX512:       # %bb.0:
-; AVX512-NEXT:    vbroadcastss {{.*#+}} xmm1 = [NaN,NaN,NaN,NaN]
-; AVX512-NEXT:    vrsqrtss %xmm0, %xmm0, %xmm2
-; AVX512-NEXT:    vandps %xmm1, %xmm0, %xmm1
-; AVX512-NEXT:    vcmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %k1
-; AVX512-NEXT:    vmulss %xmm2, %xmm0, %xmm0
-; AVX512-NEXT:    vxorps %xmm1, %xmm1, %xmm1
-; AVX512-NEXT:    vmovss %xmm1, %xmm0, %xmm0 {%k1}
-; AVX512-NEXT:    retq
+; AVX-LABEL: f32_estimate2:
+; AVX:       # %bb.0:
+; AVX-NEXT:    vsqrtss %xmm0, %xmm0, %xmm0
+; AVX-NEXT:    retq
   %sqrt = tail call fast float @llvm.sqrt.f32(float %x)
   ret float %sqrt
 }
 
 define <4 x float> @v4f32_no_estimate(<4 x float> %x) #0 {
 ; SSE-LABEL: v4f32_no_estimate:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    sqrtps %xmm0, %xmm1

llvm/test/CodeGen/X86/x86-cmov-converter.ll

loop.body:
   store i32 %data, ptr%dst2, align 4
   %iv.next = add i32 %phi.iv, 1
   %cond = icmp slt i32 %iv.next, 1024
   br i1 %cond, label %loop.body, label %exit
 exit:
   ret void
 }
 
-attributes #0 = {"target-cpu"="x86-64"}
+attributes #0 = {"target-cpu"="x86-64" "tune-cpu"="x86-64"}
 !0 = !{}

llvm/test/DebugInfo/COFF/register-variables.ll

 
 declare i32 @getint() #1
 
 declare void @putint(i32) #1
 
 ; Function Attrs: nounwind readnone
 declare void @llvm.dbg.value(metadata, metadata, metadata) #2
 
-attributes #0 = { nounwind uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #0 = { nounwind uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "tune-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" }
 attributes #1 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" }
 attributes #2 = { nounwind readnone }
 attributes #3 = { nounwind }
 
 !llvm.dbg.cu = !{!2}
 !llvm.module.flags = !{!8, !9, !10}
 !llvm.ident = !{!11}