Use TuningFastScalarFSQRT for default X86 tuning

[andrew.w.kaylor]

Summary

When the "tune-cpu" attribute is not set or is set to "x86-64", we currently use an approximation sequence (when permitted) rather than the sqrtss instruction. Since this instruction is available with the default x86-64 ISA and is more accurate, it is better to assume fast sqrt by default, as we do with "tune-cpu"="generic".

The clang front end sets "tune-cpu"="generic" if no tuning or target processor is specifically requested, but other front ends that set "target-cpu"="x86-64" will get the "x86-64" tuning, which is different from "generic".

I've also started a discussion of this here: https://discourse.llvm.org/t/fast-scalar-fsqrt-tuning-in-x86/63605

[RKSimon]

llvm/test/CodeGen/X86/sqrt-fastmath-tunecpu-attr.ll

2

add explicit triple for cases when its run on other arch

[RKSimon]

Abandon this after D129647?

[andrew.w.kaylor]

Superseded by D129647

llvm/lib/Target/X86/X86.td

 // knobs which need to be tuned differently for AMD chips, we might consider
 // forming a common base for them.
 def : ProcModel<"x86-64", SandyBridgeModel, ProcessorFeatures.X86_64V1Features,
 [
   TuningSlow3OpsLEA,
   TuningSlowDivide64,
   TuningSlowIncDec,
   TuningMacroFusion,
+  TuningFastScalarFSQRT,
   TuningInsertVZEROUPPER
 ]>;
 
 // x86-64 micro-architecture levels.
 def : ProcModel<"x86-64-v2", SandyBridgeModel, ProcessorFeatures.X86_64V2Features,
                 ProcessorFeatures.SNBTuning>;
 // Close to Haswell.
 def : ProcModel<"x86-64-v3", HaswellModel, ProcessorFeatures.X86_64V3Features,

llvm/test/CodeGen/X86/pow.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64 | FileCheck %s
 
 declare float @llvm.pow.f32(float, float)
 declare <4 x float> @llvm.pow.v4f32(<4 x float>, <4 x float>)
 
 declare double @llvm.pow.f64(double, double)
 declare <2 x double> @llvm.pow.v2f64(<2 x double>, <2 x double>)
 
 declare x86_fp80 @llvm.pow.f80(x86_fp80, x86_fp80)
 
 define float @pow_f32_one_fourth_fmf_ieee(float %x) nounwind {
 ; CHECK-LABEL: pow_f32_one_fourth_fmf_ieee:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rsqrtss %xmm0, %xmm1
-; CHECK-NEXT:    movaps %xmm0, %xmm3
-; CHECK-NEXT:    mulss %xmm1, %xmm3
-; CHECK-NEXT:    movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
-; CHECK-NEXT:    movaps %xmm3, %xmm4
-; CHECK-NEXT:    mulss %xmm2, %xmm4
-; CHECK-NEXT:    mulss %xmm1, %xmm3
-; CHECK-NEXT:    movss {{.*#+}} xmm5 = mem[0],zero,zero,zero
-; CHECK-NEXT:    addss %xmm5, %xmm3
-; CHECK-NEXT:    mulss %xmm4, %xmm3
-; CHECK-NEXT:    movaps {{.*#+}} xmm1 = [NaN,NaN,NaN,NaN]
-; CHECK-NEXT:    andps %xmm1, %xmm0
-; CHECK-NEXT:    movss {{.*#+}} xmm4 = mem[0],zero,zero,zero
-; CHECK-NEXT:    cmpltss %xmm4, %xmm0
-; CHECK-NEXT:    andnps %xmm3, %xmm0
-; CHECK-NEXT:    xorps %xmm3, %xmm3
-; CHECK-NEXT:    rsqrtss %xmm0, %xmm3
-; CHECK-NEXT:    andps %xmm0, %xmm1
-; CHECK-NEXT:    mulss %xmm3, %xmm0
-; CHECK-NEXT:    mulss %xmm0, %xmm2
-; CHECK-NEXT:    mulss %xmm3, %xmm0
-; CHECK-NEXT:    addss %xmm5, %xmm0
-; CHECK-NEXT:    mulss %xmm2, %xmm0
-; CHECK-NEXT:    cmpltss %xmm4, %xmm1
-; CHECK-NEXT:    andnps %xmm0, %xmm1
-; CHECK-NEXT:    movaps %xmm1, %xmm0
+; CHECK-NEXT:    sqrtss %xmm0, %xmm0
+; CHECK-NEXT:    sqrtss %xmm0, %xmm0
 ; CHECK-NEXT:    retq
   %r = call nsz ninf afn float @llvm.pow.f32(float %x, float 2.5e-01)
   ret float %r
 }
 
 define float @pow_f32_one_fourth_fmf_daz(float %x) #0 {
 ; CHECK-LABEL: pow_f32_one_fourth_fmf_daz:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rsqrtss %xmm0, %xmm1
-; CHECK-NEXT:    movaps %xmm0, %xmm2
-; CHECK-NEXT:    mulss %xmm1, %xmm2
-; CHECK-NEXT:    movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
-; CHECK-NEXT:    movaps %xmm2, %xmm4
-; CHECK-NEXT:    mulss %xmm3, %xmm4
-; CHECK-NEXT:    mulss %xmm1, %xmm2
-; CHECK-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; CHECK-NEXT:    addss %xmm1, %xmm2
-; CHECK-NEXT:    mulss %xmm4, %xmm2
-; CHECK-NEXT:    xorps %xmm4, %xmm4
-; CHECK-NEXT:    cmpeqss %xmm4, %xmm0
-; CHECK-NEXT:    andnps %xmm2, %xmm0
-; CHECK-NEXT:    xorps %xmm2, %xmm2
-; CHECK-NEXT:    rsqrtss %xmm0, %xmm2
-; CHECK-NEXT:    movaps %xmm0, %xmm5
-; CHECK-NEXT:    mulss %xmm2, %xmm5
-; CHECK-NEXT:    mulss %xmm5, %xmm3
-; CHECK-NEXT:    mulss %xmm2, %xmm5
-; CHECK-NEXT:    addss %xmm1, %xmm5
-; CHECK-NEXT:    mulss %xmm3, %xmm5
-; CHECK-NEXT:    cmpeqss %xmm4, %xmm0
-; CHECK-NEXT:    andnps %xmm5, %xmm0
+; CHECK-NEXT:    sqrtss %xmm0, %xmm0
+; CHECK-NEXT:    sqrtss %xmm0, %xmm0
 ; CHECK-NEXT:    retq
   %r = call nsz ninf afn float @llvm.pow.f32(float %x, float 2.5e-01)
   ret float %r
 }
 
 define double @pow_f64_one_fourth_fmf(double %x) nounwind {
 ; CHECK-LABEL: pow_f64_one_fourth_fmf:
 ; CHECK:       # %bb.0:

llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=nehalem     | FileCheck %s --check-prefixes=NHM
 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=sandybridge | FileCheck %s --check-prefixes=FAST-SCALAR,SNB
 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=broadwell   | FileCheck %s --check-prefixes=FAST-SCALAR,BDW
 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=skylake     | FileCheck %s --check-prefixes=FAST-SCALAR,FAST-VECTOR
 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver1      | FileCheck %s --check-prefixes=FAST-SCALAR,FAST-VECTOR
 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver3      | FileCheck %s --check-prefixes=FAST-SCALAR,FAST-VECTOR
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=generic     | FileCheck %s --check-prefixes=FAST-SCALAR-SSE,SSE-SLOWVEC
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64      | FileCheck %s --check-prefixes=FAST-SCALAR-SSE,SSE-SLOWVEC
 
 define float @f32_no_daz(float %f) #0 {
 ; NHM-LABEL: f32_no_daz:
 ; NHM:       # %bb.0:
 ; NHM-NEXT:    rsqrtss %xmm0, %xmm1
 ; NHM-NEXT:    movaps %xmm0, %xmm2
 ; NHM-NEXT:    mulss %xmm1, %xmm2
 ; NHM-NEXT:    movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
 ; NHM-NEXT:    mulss %xmm2, %xmm3
 ; NHM-NEXT:    mulss %xmm1, %xmm2
 ; NHM-NEXT:    addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
 ; NHM-NEXT:    mulss %xmm3, %xmm2
 ; NHM-NEXT:    andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
 ; NHM-NEXT:    cmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
 ; NHM-NEXT:    andnps %xmm2, %xmm0
 ; NHM-NEXT:    retq
 ;
+; FAST-SCALAR-SSE-LABEL: f32_no_daz:
+; FAST-SCALAR-SSE:       # %bb.0:
+; FAST-SCALAR-SSE-NEXT:    sqrtss %xmm0, %xmm0
+; FAST-SCALAR-SSE-NEXT:    retq
+;
 ; FAST-SCALAR-LABEL: f32_no_daz:
 ; FAST-SCALAR:       # %bb.0:
 ; FAST-SCALAR-NEXT:    vsqrtss %xmm0, %xmm0, %xmm0
 ; FAST-SCALAR-NEXT:    retq
   %call = tail call fast float @llvm.sqrt.f32(float %f) #2
   ret float %call
 }
 

 ; NHM-NEXT:    mulps %xmm3, %xmm2
 ; NHM-NEXT:    andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
 ; NHM-NEXT:    movaps {{.*#+}} xmm1 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38]
 ; NHM-NEXT:    cmpleps %xmm0, %xmm1
 ; NHM-NEXT:    andps %xmm2, %xmm1
 ; NHM-NEXT:    movaps %xmm1, %xmm0
 ; NHM-NEXT:    retq
 ;
+; SSE-SLOWVEC-LABEL: v4f32_no_daz:
+; SSE-SLOWVEC:       # %bb.0:
+; SSE-SLOWVEC-NEXT:    rsqrtps %xmm0, %xmm1
+; SSE-SLOWVEC-NEXT:    movaps %xmm0, %xmm2
+; SSE-SLOWVEC-NEXT:    mulps %xmm1, %xmm2
+; SSE-SLOWVEC-NEXT:    movaps {{.*#+}} xmm3 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
+; SSE-SLOWVEC-NEXT:    mulps %xmm2, %xmm3
+; SSE-SLOWVEC-NEXT:    mulps %xmm1, %xmm2
+; SSE-SLOWVEC-NEXT:    addps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
+; SSE-SLOWVEC-NEXT:    mulps %xmm3, %xmm2
+; SSE-SLOWVEC-NEXT:    andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-SLOWVEC-NEXT:    movaps {{.*#+}} xmm1 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38]
+; SSE-SLOWVEC-NEXT:    cmpleps %xmm0, %xmm1
+; SSE-SLOWVEC-NEXT:    andps %xmm2, %xmm1
+; SSE-SLOWVEC-NEXT:    movaps %xmm1, %xmm0
+; SSE-SLOWVEC-NEXT:    retq
+;
 ; SNB-LABEL: v4f32_no_daz:
 ; SNB:       # %bb.0:
 ; SNB-NEXT:    vrsqrtps %xmm0, %xmm1
 ; SNB-NEXT:    vmulps %xmm1, %xmm0, %xmm2
 ; SNB-NEXT:    vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm3
 ; SNB-NEXT:    vmulps %xmm1, %xmm2, %xmm1
 ; SNB-NEXT:    vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
 ; SNB-NEXT:    vmulps %xmm1, %xmm3, %xmm1

 ; NHM-NEXT:    mulps %xmm5, %xmm4
 ; NHM-NEXT:    andps %xmm7, %xmm1
 ; NHM-NEXT:    cmpleps %xmm1, %xmm2
 ; NHM-NEXT:    andps %xmm4, %xmm2
 ; NHM-NEXT:    movaps %xmm3, %xmm0
 ; NHM-NEXT:    movaps %xmm2, %xmm1
 ; NHM-NEXT:    retq
 ;
+; SSE-SLOWVEC-LABEL: v8f32_no_daz:
+; SSE-SLOWVEC:       # %bb.0:
+; SSE-SLOWVEC-NEXT:    rsqrtps %xmm0, %xmm2
+; SSE-SLOWVEC-NEXT:    movaps %xmm0, %xmm4
+; SSE-SLOWVEC-NEXT:    mulps %xmm2, %xmm4
+; SSE-SLOWVEC-NEXT:    movaps {{.*#+}} xmm5 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
+; SSE-SLOWVEC-NEXT:    movaps %xmm4, %xmm3
+; SSE-SLOWVEC-NEXT:    mulps %xmm5, %xmm3
+; SSE-SLOWVEC-NEXT:    mulps %xmm2, %xmm4
+; SSE-SLOWVEC-NEXT:    movaps {{.*#+}} xmm6 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0]
+; SSE-SLOWVEC-NEXT:    addps %xmm6, %xmm4
+; SSE-SLOWVEC-NEXT:    mulps %xmm3, %xmm4
+; SSE-SLOWVEC-NEXT:    movaps {{.*#+}} xmm7 = [NaN,NaN,NaN,NaN]
+; SSE-SLOWVEC-NEXT:    andps %xmm7, %xmm0
+; SSE-SLOWVEC-NEXT:    movaps {{.*#+}} xmm2 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38]
+; SSE-SLOWVEC-NEXT:    movaps %xmm2, %xmm3
+; SSE-SLOWVEC-NEXT:    cmpleps %xmm0, %xmm3
+; SSE-SLOWVEC-NEXT:    andps %xmm4, %xmm3
+; SSE-SLOWVEC-NEXT:    rsqrtps %xmm1, %xmm0
+; SSE-SLOWVEC-NEXT:    movaps %xmm1, %xmm4
+; SSE-SLOWVEC-NEXT:    mulps %xmm0, %xmm4
+; SSE-SLOWVEC-NEXT:    mulps %xmm4, %xmm5
+; SSE-SLOWVEC-NEXT:    mulps %xmm0, %xmm4
+; SSE-SLOWVEC-NEXT:    addps %xmm6, %xmm4
+; SSE-SLOWVEC-NEXT:    mulps %xmm5, %xmm4
+; SSE-SLOWVEC-NEXT:    andps %xmm7, %xmm1
+; SSE-SLOWVEC-NEXT:    cmpleps %xmm1, %xmm2
+; SSE-SLOWVEC-NEXT:    andps %xmm4, %xmm2
+; SSE-SLOWVEC-NEXT:    movaps %xmm3, %xmm0
+; SSE-SLOWVEC-NEXT:    movaps %xmm2, %xmm1
+; SSE-SLOWVEC-NEXT:    retq
+;
 ; SNB-LABEL: v8f32_no_daz:
 ; SNB:       # %bb.0:
 ; SNB-NEXT:    vrsqrtps %ymm0, %ymm1
 ; SNB-NEXT:    vmulps %ymm1, %ymm0, %ymm2
 ; SNB-NEXT:    vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm3
 ; SNB-NEXT:    vmulps %ymm1, %ymm2, %ymm1
 ; SNB-NEXT:    vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
 ; SNB-NEXT:    vmulps %ymm1, %ymm3, %ymm1

 ; NHM-NEXT:    mulss %xmm1, %xmm2
 ; NHM-NEXT:    addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
 ; NHM-NEXT:    mulss %xmm3, %xmm2
 ; NHM-NEXT:    xorps %xmm1, %xmm1
 ; NHM-NEXT:    cmpeqss %xmm1, %xmm0
 ; NHM-NEXT:    andnps %xmm2, %xmm0
 ; NHM-NEXT:    retq
 ;
+; FAST-SCALAR-SSE-LABEL: f32_daz:
+; FAST-SCALAR-SSE:       # %bb.0:
+; FAST-SCALAR-SSE-NEXT:    sqrtss %xmm0, %xmm0
+; FAST-SCALAR-SSE-NEXT:    retq
+;
 ; FAST-SCALAR-LABEL: f32_daz:
 ; FAST-SCALAR:       # %bb.0:
 ; FAST-SCALAR-NEXT:    vsqrtss %xmm0, %xmm0, %xmm0
 ; FAST-SCALAR-NEXT:    retq
   %call = tail call fast float @llvm.sqrt.f32(float %f) #2
   ret float %call
 }
 
 define <4 x float> @v4f32_daz(<4 x float> %f) #1 {
 ; NHM-LABEL: v4f32_daz:
 ; NHM:       # %bb.0:
 ; NHM-NEXT:    rsqrtps %xmm0, %xmm1
 ; NHM-NEXT:    movaps %xmm0, %xmm2
 ; NHM-NEXT:    mulps %xmm1, %xmm2
 ; NHM-NEXT:    movaps {{.*#+}} xmm3 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
 ; NHM-NEXT:    mulps %xmm2, %xmm3
 ; NHM-NEXT:    mulps %xmm1, %xmm2
 ; NHM-NEXT:    addps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
 ; NHM-NEXT:    mulps %xmm3, %xmm2
 ; NHM-NEXT:    xorps %xmm1, %xmm1
 ; NHM-NEXT:    cmpneqps %xmm1, %xmm0
 ; NHM-NEXT:    andps %xmm2, %xmm0
 ; NHM-NEXT:    retq
 ;
+; SSE-SLOWVEC-LABEL: v4f32_daz:
+; SSE-SLOWVEC:       # %bb.0:
+; SSE-SLOWVEC-NEXT:    rsqrtps %xmm0, %xmm1
+; SSE-SLOWVEC-NEXT:    movaps %xmm0, %xmm2
+; SSE-SLOWVEC-NEXT:    mulps %xmm1, %xmm2
+; SSE-SLOWVEC-NEXT:    movaps {{.*#+}} xmm3 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
+; SSE-SLOWVEC-NEXT:    mulps %xmm2, %xmm3
+; SSE-SLOWVEC-NEXT:    mulps %xmm1, %xmm2
+; SSE-SLOWVEC-NEXT:    addps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
+; SSE-SLOWVEC-NEXT:    mulps %xmm3, %xmm2
+; SSE-SLOWVEC-NEXT:    xorps %xmm1, %xmm1
+; SSE-SLOWVEC-NEXT:    cmpneqps %xmm1, %xmm0
+; SSE-SLOWVEC-NEXT:    andps %xmm2, %xmm0
+; SSE-SLOWVEC-NEXT:    retq
+;
 ; SNB-LABEL: v4f32_daz:
 ; SNB:       # %bb.0:
 ; SNB-NEXT:    vrsqrtps %xmm0, %xmm1
 ; SNB-NEXT:    vmulps %xmm1, %xmm0, %xmm2
 ; SNB-NEXT:    vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm3
 ; SNB-NEXT:    vmulps %xmm1, %xmm2, %xmm1
 ; SNB-NEXT:    vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
 ; SNB-NEXT:    vmulps %xmm1, %xmm3, %xmm1

 ; NHM-NEXT:    mulps %xmm6, %xmm4
 ; NHM-NEXT:    mulps %xmm3, %xmm6
 ; NHM-NEXT:    addps %xmm2, %xmm6
 ; NHM-NEXT:    mulps %xmm4, %xmm6
 ; NHM-NEXT:    cmpneqps %xmm5, %xmm1
 ; NHM-NEXT:    andps %xmm6, %xmm1
 ; NHM-NEXT:    retq
 ;
+; SSE-SLOWVEC-LABEL: v8f32_daz:
+; SSE-SLOWVEC:       # %bb.0:
+; SSE-SLOWVEC-NEXT:    rsqrtps %xmm0, %xmm2
+; SSE-SLOWVEC-NEXT:    movaps %xmm0, %xmm3
+; SSE-SLOWVEC-NEXT:    mulps %xmm2, %xmm3
+; SSE-SLOWVEC-NEXT:    movaps {{.*#+}} xmm4 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
+; SSE-SLOWVEC-NEXT:    movaps %xmm3, %xmm5
+; SSE-SLOWVEC-NEXT:    mulps %xmm4, %xmm5
+; SSE-SLOWVEC-NEXT:    mulps %xmm2, %xmm3
+; SSE-SLOWVEC-NEXT:    movaps {{.*#+}} xmm2 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0]
+; SSE-SLOWVEC-NEXT:    addps %xmm2, %xmm3
+; SSE-SLOWVEC-NEXT:    mulps %xmm5, %xmm3
+; SSE-SLOWVEC-NEXT:    xorps %xmm5, %xmm5
+; SSE-SLOWVEC-NEXT:    cmpneqps %xmm5, %xmm0
+; SSE-SLOWVEC-NEXT:    andps %xmm3, %xmm0
+; SSE-SLOWVEC-NEXT:    rsqrtps %xmm1, %xmm3
+; SSE-SLOWVEC-NEXT:    movaps %xmm1, %xmm6
+; SSE-SLOWVEC-NEXT:    mulps %xmm3, %xmm6
+; SSE-SLOWVEC-NEXT:    mulps %xmm6, %xmm4
+; SSE-SLOWVEC-NEXT:    mulps %xmm3, %xmm6
+; SSE-SLOWVEC-NEXT:    addps %xmm2, %xmm6
+; SSE-SLOWVEC-NEXT:    mulps %xmm4, %xmm6
+; SSE-SLOWVEC-NEXT:    cmpneqps %xmm5, %xmm1
+; SSE-SLOWVEC-NEXT:    andps %xmm6, %xmm1
+; SSE-SLOWVEC-NEXT:    retq
+;
 ; SNB-LABEL: v8f32_daz:
 ; SNB:       # %bb.0:
 ; SNB-NEXT:    vrsqrtps %ymm0, %ymm1
 ; SNB-NEXT:    vmulps %ymm1, %ymm0, %ymm2
 ; SNB-NEXT:    vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm3
 ; SNB-NEXT:    vmulps %ymm1, %ymm2, %ymm1
 ; SNB-NEXT:    vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
 ; SNB-NEXT:    vmulps %ymm1, %ymm3, %ymm1

llvm/test/CodeGen/X86/sqrt-fastmath-tunecpu-attr.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s | FileCheck %s
+
+define float @f32_tune_nhm(float %f) #0 {
+; CHECK-LABEL: f32_tune_nhm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    rsqrtss %xmm0, %xmm1
+; CHECK-NEXT:    movaps %xmm0, %xmm2
+; CHECK-NEXT:    mulss %xmm1, %xmm2
+; CHECK-NEXT:    movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
+; CHECK-NEXT:    mulss %xmm2, %xmm3
+; CHECK-NEXT:    mulss %xmm1, %xmm2
+; CHECK-NEXT:    addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
+; CHECK-NEXT:    mulss %xmm3, %xmm2
+; CHECK-NEXT:    andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT:    cmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT:    andnps %xmm2, %xmm0
+; CHECK-NEXT:    retq
+  %call = tail call fast float @llvm.sqrt.f32(float %f)
+  ret float %call
+}
+
+define float @f32_no_tune(float %f) #1 {
+; CHECK-LABEL: f32_no_tune:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sqrtss %xmm0, %xmm0
+; CHECK-NEXT:    retq
+  %call = tail call fast float @llvm.sqrt.f32(float %f)
+  ret float %call
+}
+
+define float @f32_tune_generic(float %f) #2 {
+; CHECK-LABEL: f32_tune_generic:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sqrtss %xmm0, %xmm0
+; CHECK-NEXT:    retq
+  %call = tail call fast float @llvm.sqrt.f32(float %f)
+  ret float %call
+}
+
+define float @f32_tune_x86_64(float %f) #3 {
+; CHECK-LABEL: f32_tune_x86_64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sqrtss %xmm0, %xmm0
+; CHECK-NEXT:    retq
+  %call = tail call fast float @llvm.sqrt.f32(float %f)
+  ret float %call
+}
+
+define float @f32_tune_snb(float %f) #4 {
+; CHECK-LABEL: f32_tune_snb:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sqrtss %xmm0, %xmm0
+; CHECK-NEXT:    retq
+  %call = tail call fast float @llvm.sqrt.f32(float %f)
+  ret float %call
+}
+
+define float @f32_target_snb_tune_snb(float %f) #5 {
+; CHECK-LABEL: f32_target_snb_tune_snb:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsqrtss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT:    retq
+  %call = tail call fast float @llvm.sqrt.f32(float %f)
+  ret float %call
+}
+
+declare float @llvm.sqrt.f32(float)
+
+attributes #0 = { "target-cpu"="x86-64" "tune-cpu"="nehalem" }
+attributes #1 = { "target-cpu"="x86-64" }
+attributes #2 = { "target-cpu"="x86-64" "tune-cpu"="generic" }
+attributes #3 = { "target-cpu"="x86-64" "tune-cpu"="x86-64" }
+attributes #4 = { "target-cpu"="x86-64" "tune-cpu"="sandybridge" }
+attributes #5 = { "target-cpu"="sandybridge" "tune-cpu"="sandybridge" }

llvm/test/CodeGen/X86/sqrt-fastmath.ll

 ; AVX-NEXT:    retq
   %call = tail call float @__sqrtf_finite(float %f) #2
   ret float %call
 }
 
 define float @finite_f32_estimate_ieee_ninf(float %f) #1 {
 ; SSE-LABEL: finite_f32_estimate_ieee_ninf:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    rsqrtss %xmm0, %xmm1
-; SSE-NEXT:    movaps %xmm0, %xmm2
-; SSE-NEXT:    mulss %xmm1, %xmm2
-; SSE-NEXT:    movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
-; SSE-NEXT:    mulss %xmm2, %xmm3
-; SSE-NEXT:    mulss %xmm1, %xmm2
-; SSE-NEXT:    addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
-; SSE-NEXT:    mulss %xmm3, %xmm2
-; SSE-NEXT:    andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE-NEXT:    cmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE-NEXT:    andnps %xmm2, %xmm0
+; SSE-NEXT:    sqrtss %xmm0, %xmm0
 ; SSE-NEXT:    retq
 ;
-; AVX1-LABEL: finite_f32_estimate_ieee_ninf:
-; AVX1:       # %bb.0:
-; AVX1-NEXT:    vrsqrtss %xmm0, %xmm0, %xmm1
-; AVX1-NEXT:    vmulss %xmm1, %xmm0, %xmm2
-; AVX1-NEXT:    vmulss %xmm1, %xmm2, %xmm1
-; AVX1-NEXT:    vaddss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
-; AVX1-NEXT:    vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
-; AVX1-NEXT:    vmulss %xmm1, %xmm2, %xmm1
-; AVX1-NEXT:    vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX1-NEXT:    vcmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX1-NEXT:    vandnps %xmm1, %xmm0, %xmm0
-; AVX1-NEXT:    retq
-;
-; AVX512-LABEL: finite_f32_estimate_ieee_ninf:
-; AVX512:       # %bb.0:
-; AVX512-NEXT:    vrsqrtss %xmm0, %xmm0, %xmm1
-; AVX512-NEXT:    vbroadcastss {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
-; AVX512-NEXT:    vandps %xmm2, %xmm0, %xmm2
-; AVX512-NEXT:    vmulss %xmm1, %xmm0, %xmm0
-; AVX512-NEXT:    vfmadd213ss {{.*#+}} xmm1 = (xmm0 * xmm1) + mem
-; AVX512-NEXT:    vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX512-NEXT:    vcmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %k1
-; AVX512-NEXT:    vmulss %xmm1, %xmm0, %xmm0
-; AVX512-NEXT:    vxorps %xmm1, %xmm1, %xmm1
-; AVX512-NEXT:    vmovss %xmm1, %xmm0, %xmm0 {%k1}
-; AVX512-NEXT:    retq
+; AVX-LABEL: finite_f32_estimate_ieee_ninf:
+; AVX:       # %bb.0:
+; AVX-NEXT:    vsqrtss %xmm0, %xmm0, %xmm0
+; AVX-NEXT:    retq
   %call = tail call ninf afn float @__sqrtf_finite(float %f) #2
   ret float %call
 }
 
 define float @finite_f32_estimate_daz(float %f) #4 {
 ; SSE-LABEL: finite_f32_estimate_daz:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    sqrtss %xmm0, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: finite_f32_estimate_daz:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vsqrtss %xmm0, %xmm0, %xmm0
 ; AVX-NEXT:    retq
   %call = tail call float @__sqrtf_finite(float %f) #2
   ret float %call
 }
 
 define float @finite_f32_estimate_daz_ninf(float %f) #4 {
 ; SSE-LABEL: finite_f32_estimate_daz_ninf:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    rsqrtss %xmm0, %xmm1
-; SSE-NEXT:    movaps %xmm0, %xmm2
-; SSE-NEXT:    mulss %xmm1, %xmm2
-; SSE-NEXT:    movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
-; SSE-NEXT:    mulss %xmm2, %xmm3
-; SSE-NEXT:    mulss %xmm1, %xmm2
-; SSE-NEXT:    addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
-; SSE-NEXT:    mulss %xmm3, %xmm2
-; SSE-NEXT:    xorps %xmm1, %xmm1
-; SSE-NEXT:    cmpeqss %xmm1, %xmm0
-; SSE-NEXT:    andnps %xmm2, %xmm0
+; SSE-NEXT:    sqrtss %xmm0, %xmm0
 ; SSE-NEXT:    retq
 ;
-; AVX1-LABEL: finite_f32_estimate_daz_ninf:
-; AVX1:       # %bb.0:
-; AVX1-NEXT:    vrsqrtss %xmm0, %xmm0, %xmm1
-; AVX1-NEXT:    vmulss %xmm1, %xmm0, %xmm2
-; AVX1-NEXT:    vmulss %xmm1, %xmm2, %xmm1
-; AVX1-NEXT:    vaddss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
-; AVX1-NEXT:    vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
-; AVX1-NEXT:    vmulss %xmm1, %xmm2, %xmm1
-; AVX1-NEXT:    vxorps %xmm2, %xmm2, %xmm2
-; AVX1-NEXT:    vcmpeqss %xmm2, %xmm0, %xmm0
-; AVX1-NEXT:    vandnps %xmm1, %xmm0, %xmm0
-; AVX1-NEXT:    retq
-;
-; AVX512-LABEL: finite_f32_estimate_daz_ninf:
-; AVX512:       # %bb.0:
-; AVX512-NEXT:    vrsqrtss %xmm0, %xmm0, %xmm1
-; AVX512-NEXT:    vmulss %xmm1, %xmm0, %xmm2
-; AVX512-NEXT:    vfmadd213ss {{.*#+}} xmm1 = (xmm2 * xmm1) + mem
-; AVX512-NEXT:    vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
-; AVX512-NEXT:    vmulss %xmm1, %xmm2, %xmm1
-; AVX512-NEXT:    vxorps %xmm2, %xmm2, %xmm2
-; AVX512-NEXT:    vcmpeqss %xmm2, %xmm0, %k1
-; AVX512-NEXT:    vmovss %xmm2, %xmm1, %xmm1 {%k1}
-; AVX512-NEXT:    vmovaps %xmm1, %xmm0
-; AVX512-NEXT:    retq
+; AVX-LABEL: finite_f32_estimate_daz_ninf:
+; AVX:       # %bb.0:
+; AVX-NEXT:    vsqrtss %xmm0, %xmm0, %xmm0
+; AVX-NEXT:    retq
   %call = tail call ninf afn float @__sqrtf_finite(float %f) #2
   ret float %call
 }
 
 define x86_fp80 @finite_f80_no_estimate(x86_fp80 %ld) #0 {
 ; CHECK-LABEL: finite_f80_no_estimate:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fldt {{[0-9]+}}(%rsp)

 ; AVX-NEXT:    retq
   %call = tail call float @__sqrtf_finite(float %x) #2
   ret float %call
 }
 
 define float @sqrtf_check_denorms_ninf(float %x) #3 {
 ; SSE-LABEL: sqrtf_check_denorms_ninf:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    rsqrtss %xmm0, %xmm1
-; SSE-NEXT:    movaps %xmm0, %xmm2
-; SSE-NEXT:    mulss %xmm1, %xmm2
-; SSE-NEXT:    movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
-; SSE-NEXT:    mulss %xmm2, %xmm3
-; SSE-NEXT:    mulss %xmm1, %xmm2
-; SSE-NEXT:    addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
-; SSE-NEXT:    mulss %xmm3, %xmm2
-; SSE-NEXT:    andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE-NEXT:    cmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE-NEXT:    andnps %xmm2, %xmm0
+; SSE-NEXT:    sqrtss %xmm0, %xmm0
 ; SSE-NEXT:    retq
 ;
-; AVX1-LABEL: sqrtf_check_denorms_ninf:
-; AVX1:       # %bb.0:
-; AVX1-NEXT:    vrsqrtss %xmm0, %xmm0, %xmm1
-; AVX1-NEXT:    vmulss %xmm1, %xmm0, %xmm2
-; AVX1-NEXT:    vmulss %xmm1, %xmm2, %xmm1
-; AVX1-NEXT:    vaddss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
-; AVX1-NEXT:    vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
-; AVX1-NEXT:    vmulss %xmm1, %xmm2, %xmm1
-; AVX1-NEXT:    vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX1-NEXT:    vcmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX1-NEXT:    vandnps %xmm1, %xmm0, %xmm0
-; AVX1-NEXT:    retq
-;
-; AVX512-LABEL: sqrtf_check_denorms_ninf:
-; AVX512:       # %bb.0:
-; AVX512-NEXT:    vrsqrtss %xmm0, %xmm0, %xmm1
-; AVX512-NEXT:    vbroadcastss {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
-; AVX512-NEXT:    vandps %xmm2, %xmm0, %xmm2
-; AVX512-NEXT:    vmulss %xmm1, %xmm0, %xmm0
-; AVX512-NEXT:    vfmadd213ss {{.*#+}} xmm1 = (xmm0 * xmm1) + mem
-; AVX512-NEXT:    vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX512-NEXT:    vcmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %k1
-; AVX512-NEXT:    vmulss %xmm1, %xmm0, %xmm0
-; AVX512-NEXT:    vxorps %xmm1, %xmm1, %xmm1
-; AVX512-NEXT:    vmovss %xmm1, %xmm0, %xmm0 {%k1}
-; AVX512-NEXT:    retq
+; AVX-LABEL: sqrtf_check_denorms_ninf:
+; AVX:       # %bb.0:
+; AVX-NEXT:    vsqrtss %xmm0, %xmm0, %xmm0
+; AVX-NEXT:    retq
   %call = tail call ninf afn float @__sqrtf_finite(float %x) #2
   ret float %call
 }
 
 define <4 x float> @sqrt_v4f32_check_denorms(<4 x float> %x) #3 {
 ; SSE-LABEL: sqrt_v4f32_check_denorms:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    sqrtps %xmm0, %xmm0
; AVX512-NEXT:    retq
   %sqrt = tail call float @llvm.sqrt.f32(float %x)
   %div = fdiv fast float 1.0, %sqrt
   ret float %div
 }
 
 define float @f32_estimate2(float %x) #5 {
 ; SSE-LABEL: f32_estimate2:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    rsqrtss %xmm0, %xmm1
-; SSE-NEXT:    mulss %xmm0, %xmm1
-; SSE-NEXT:    andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE-NEXT:    cmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE-NEXT:    andnps %xmm1, %xmm0
+; SSE-NEXT:    sqrtss %xmm0, %xmm0
 ; SSE-NEXT:    retq
 ;
-; AVX1-LABEL: f32_estimate2:
-; AVX1:       # %bb.0:
-; AVX1-NEXT:    vrsqrtss %xmm0, %xmm0, %xmm1
-; AVX1-NEXT:    vmulss %xmm1, %xmm0, %xmm1
-; AVX1-NEXT:    vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX1-NEXT:    vcmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX1-NEXT:    vandnps %xmm1, %xmm0, %xmm0
-; AVX1-NEXT:    retq
-;
-; AVX512-LABEL: f32_estimate2:
-; AVX512:       # %bb.0:
-; AVX512-NEXT:    vbroadcastss {{.*#+}} xmm1 = [NaN,NaN,NaN,NaN]
-; AVX512-NEXT:    vrsqrtss %xmm0, %xmm0, %xmm2
-; AVX512-NEXT:    vandps %xmm1, %xmm0, %xmm1
-; AVX512-NEXT:    vcmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %k1
-; AVX512-NEXT:    vmulss %xmm2, %xmm0, %xmm0
-; AVX512-NEXT:    vxorps %xmm1, %xmm1, %xmm1
-; AVX512-NEXT:    vmovss %xmm1, %xmm0, %xmm0 {%k1}
-; AVX512-NEXT:    retq
+; AVX-LABEL: f32_estimate2:
+; AVX:       # %bb.0:
+; AVX-NEXT:    vsqrtss %xmm0, %xmm0, %xmm0
+; AVX-NEXT:    retq
   %sqrt = tail call fast float @llvm.sqrt.f32(float %x)
   ret float %sqrt
 }
 
 define <4 x float> @v4f32_no_estimate(<4 x float> %x) #0 {
 ; SSE-LABEL: v4f32_no_estimate:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    sqrtps %xmm0, %xmm1