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Differential D129449

[AArch64] Update latencies for Cortex-A55 schedule.
AcceptedPublic

Authored by dmgreen on Jul 10 2022, 10:03 AM.

Details

Reviewers
SjoerdMeijer
samtebbs
kristof.beyls
t.p.northover
NickGuy
andreadb
sjarus
Summary

The Cortex-A55 schedule currently attempts to model a lot of the effective latencies by marking most integer instructions as having a latency of 3, and then adding forwarding latencies between classes of instructions. When this works it does OK, but is very easy to either get the effective latencies wrong or be tripped up by instructions like pseudo instructions that knock the latency back to 3 without considering forwarding. That in turn can make the decisions it makes suboptimal. This patch simplifies that by just setting the latencies more directly, lining the latencies up with the values from the Software Optimization Guide. In reality the core is more sophisticated than either scheme.

As expected for the AArch64 default schedule, this alters quite a lot of codegen. Almost all of the tests are the same instructions in a slightly different order. The ones with interesting differences are:

  • andorbrcompare.ll - Now choses ccmp vs branch, due to some bad use of latencies in the AArch64ConditionalCompares pass.
  • arm64-ldp.ll - Now uses more postinc. Yay.
  • arm64-neon-mul-div.ll - Has slightly more spills. Boo.
  • Some other changes like this, where there are slightly less or more instructions.
  • neon-mla-mls.ll - Chooses mul;sub as opposed to neg;mla. I believe this is generally better, and the differences are coming from better considering of COPYs.
  • llvm-mca tests no longer show instructions taking three cycles.

For all the measurements I've been collecting, the performance is on average between flat and a slight performance increase, depending on the core and the benchmarks being run. The knock-on effects from different instruction ordering can make any individual test better or worse, but from a range of benchmarks they tend to roughly average one another out.

Diff Detail

Event Timeline

dmgreen created this revision.Jul 10 2022, 10:03 AM
Herald added a reviewer: andreadb. · View Herald TranscriptJul 10 2022, 10:03 AM
Herald added a reviewer: sjarus. · View Herald Transcript
Herald added a project: Restricted Project. · View Herald Transcript
Herald added subscribers: armkevincheng, eric-k256, asbirlea and 4 others. · View Herald Transcript
dmgreen requested review of this revision.Jul 10 2022, 10:03 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 10 2022, 10:03 AM
Harbormaster completed remote builds in B174572: Diff 443510.Jul 10 2022, 10:03 AM
SjoerdMeijer accepted this revision.Jul 11 2022, 1:00 AM

I think you just love updating a lot of tests... ;-)

More serious, the change makes sense because like you said latencies line up better with the SWOG.
But since perf is flat or a slight performance increase, I was just curious about your motivation for doing this. I.e., is the slight perf increase worth it, or is this an enabler for other things?

This revision is now accepted and ready to land.Jul 11 2022, 1:00 AM
dmgreen added a comment.Jul 13 2022, 8:33 AM

Thanks. The latest issue we ran into was from the machine combiner costmodel in D125588, but we've been noticing the increased latencies causing issues here and there for a while now. I'm hoping with more normal values it can generally make better decisions.

But I may wait until after the branch point to commit this, as it does change a lot of codegen and we are not very far away now.

Matt added a subscriber: Matt.Jul 13 2022, 4:15 PM
SjoerdMeijer added a comment.Jul 14 2022, 12:38 AM

Cheers, sounds good.

Large Diff

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Diff 443510

llvm/lib/Target/AArch64/AArch64SchedA55.td

llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll

llvm/test/CodeGen/AArch64/GlobalISel/call-translator-variadic-musttail.ll

llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll

llvm/test/CodeGen/AArch64/GlobalISel/select-bitfield-insert.ll

llvm/test/CodeGen/AArch64/GlobalISel/store-merging.ll

llvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll

llvm/test/CodeGen/AArch64/aarch64-be-bv.ll

llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll

llvm/test/CodeGen/AArch64/aarch64-load-ext.ll

llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll

llvm/test/CodeGen/AArch64/aarch64-mops-consecutive.ll

llvm/test/CodeGen/AArch64/aarch64-smull.ll

llvm/test/CodeGen/AArch64/aarch64-tail-dup-size.ll

llvm/test/CodeGen/AArch64/aarch64_win64cc_vararg.ll

llvm/test/CodeGen/AArch64/active_lane_mask.ll

llvm/test/CodeGen/AArch64/align-down.ll

llvm/test/CodeGen/AArch64/and-mask-removal.ll

llvm/test/CodeGen/AArch64/andorbrcompare.ll

llvm/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll

llvm/test/CodeGen/AArch64/arm64-addr-type-promotion.ll

llvm/test/CodeGen/AArch64/arm64-addrmode.ll

llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll

llvm/test/CodeGen/AArch64/arm64-cse.ll

llvm/test/CodeGen/AArch64/arm64-fcopysign.ll

llvm/test/CodeGen/AArch64/arm64-fmadd.ll

llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog-no-helper.ll

llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll

llvm/test/CodeGen/AArch64/arm64-inline-asm.ll

llvm/test/CodeGen/AArch64/arm64-instruction-mix-remarks.ll

llvm/test/CodeGen/AArch64/arm64-ldp.ll

llvm/test/CodeGen/AArch64/arm64-neon-copy.ll

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llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-frame-offests-crash.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-insert-vector-elt.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-int-compares.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-int-div.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-int-log.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-int-minmax.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-int-reduce.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-int-select.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-int-shifts.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-int-to-fp.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-int-vselect.ll

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llvm/test/CodeGen/AArch64/sve-fixed-length-log-reduce.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-masked-stores.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-permute-rev.ll

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llvm/test/CodeGen/AArch64/sve-fixed-length-sdiv-pow2.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll

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llvm/test/CodeGen/AArch64/sve-fp-reduce.ll

llvm/test/CodeGen/AArch64/sve-gather-scatter-addr-opts.ll

llvm/test/CodeGen/AArch64/sve-implicit-zero-filling.ll

llvm/test/CodeGen/AArch64/sve-insert-element.ll

llvm/test/CodeGen/AArch64/sve-insert-vector.ll

llvm/test/CodeGen/AArch64/sve-int-arith.ll

llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems-i32.ll

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llvm/test/CodeGen/AArch64/sve-masked-ldst-sext.ll

llvm/test/CodeGen/AArch64/sve-select.ll

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llvm/test/CodeGen/AArch64/sve-split-fcvt.ll

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llvm/test/CodeGen/AArch64/urem-lkk.ll

llvm/test/CodeGen/AArch64/urem-seteq-illegal-types.ll

llvm/test/CodeGen/AArch64/urem-seteq-vec-nonsplat.ll

llvm/test/CodeGen/AArch64/urem-seteq-vec-nonzero.ll

llvm/test/CodeGen/AArch64/urem-seteq-vec-splat.ll

llvm/test/CodeGen/AArch64/urem-seteq-vec-tautological.ll

llvm/test/CodeGen/AArch64/urem-vector-lkk.ll

llvm/test/CodeGen/AArch64/usub_sat_vec.ll

llvm/test/CodeGen/AArch64/vec_uaddo.ll

llvm/test/CodeGen/AArch64/vec_umulo.ll

llvm/test/CodeGen/AArch64/vecreduce-add.ll

llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization-strict.ll

llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization.ll

llvm/test/CodeGen/AArch64/vecreduce-fadd.ll

llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll

llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll

llvm/test/CodeGen/AArch64/vector-fcopysign.ll

llvm/test/CodeGen/AArch64/vector-gep.ll

llvm/test/CodeGen/AArch64/vector-popcnt-128-ult-ugt.ll

llvm/test/CodeGen/AArch64/vselect-constants.ll

llvm/test/CodeGen/AArch64/vselect-ext.ll

llvm/test/CodeGen/AArch64/win64_vararg.ll

llvm/test/CodeGen/AArch64/win64_vararg_float.ll

llvm/test/CodeGen/AArch64/win64_vararg_float_cc.ll

llvm/test/CodeGen/AArch64/zero-call-used-regs.ll

llvm/test/MC/AArch64/elf-globaladdress.ll

llvm/test/Transforms/CanonicalizeFreezeInLoops/aarch64.ll

llvm/test/Transforms/CodeGenPrepare/AArch64/large-offset-gep.ll

llvm/test/Transforms/LoopStrengthReduce/AArch64/lsr-ldp.ll

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.generated.expected

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.nogenerated.expected

llvm/test/tools/llvm-mca/AArch64/Cortex/A55-add-sequence.s

llvm/test/tools/llvm-mca/AArch64/Cortex/A55-all-stats.s

llvm/test/tools/llvm-mca/AArch64/Cortex/A55-all-views.s

llvm/test/tools/llvm-mca/AArch64/Cortex/A55-basic-instructions.s

llvm/test/tools/llvm-mca/AArch64/Cortex/A55-in-order-retire.s

llvm/test/tools/llvm-mca/AArch64/Cortex/A55-load-readadv.s

llvm/test/tools/llvm-mca/AArch64/Cortex/A55-out-of-order-retire.s

llvm/test/tools/llvm-mca/AArch64/Cortex/A55-store-readadv.s

llvm/test/tools/llvm-mca/AArch64/Cortex/IPC/A55-0-single-add.s

llvm/test/tools/llvm-mca/AArch64/Cortex/IPC/A55-1-add-seq.s

llvm/test/tools/llvm-mca/AArch64/Cortex/IPC/A55-3-mul.s

llvm/test/tools/llvm-mca/AArch64/Cortex/IPC/A55-4-sdiv.s

llvm/test/tools/llvm-mca/AArch64/Cortex/IPC/A55-5-mul-sdiv.s

llvm/test/tools/llvm-mca/AArch64/Cortex/IPC/A55-6-mul.s

llvm/test/tools/llvm-mca/AArch64/Cortex/IPC/A55-7-cmp.s