[globalisel] Select register bank for DBG_VALUE

[LuoYuanke]

Summary

The register operand of DBG_VALUE is not selected to a proper register
bank in both AArch64 and X86. This would cause getRegClass crash after
global ISel. After discussion, we think the MIR should assume all
vritual register should be set proper register class after global ISel,
so this patch is to fix the gap of DBG_VALUE for AArch64 and X86.

[LuoYuanke]

This patch is to fix the global ISel issue encountered in D126771 and http://45.33.8.238/macm1/37938/step_11.txt.

[arsenm]

llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp

611–613

This should get a mir test that just runs regbankselect

llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

910–911

I would expect this to be handled by generic code. However, last I looked at handling selection of another pseudo generically, I think we were missing API to allow generic code to constrain registers

912

This should guard the call, not be in it

920

While getType does check for physical registers, I think it shouldn't. Can you change !Reg to Reg.isPhysical()?

928–929

I don't understand why you are looping over to precheck all operands. You can process each register individually

937–952

This looks unnecessarily complicated, but I do think we have some API issues here

[LuoYuanke]

llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp

611–613

We have test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir to cover this scenario.

llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

920

This follow the same check of RegBankSelect.cpp:730. The RegBankSelect accept 0 register, but not accept physical register. I can add another check for Reg.isPhysical().

928–929

The precheck is to make sure there is no physical register or invalid type for an operand. If there is one, then we bail out for the whole operands. This is to avoid such scenario we handled some virtual register before we encounter a physical register operand.
We either hanldle all operands or we abandon for the whole instruction.

[LuoYuanke]

llvm/lib/Target/X86/X86RegisterBankInfo.cpp

117

This scenario can be covered by test/CodeGen/X86/GlobalISel/x86-calllowering-dbg-trunc.ll.

133

This scenario can be covered by test/CodeGen/X86/GlobalISel/x86-calllowering-dbg-trunc.ll.

[LuoYuanke]

llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp

736

There are 3 cases that I encounter when debuging test case failure.

1. 0 register.
2. physical register.
3. virtual register that has been assigned to a register class.

I changed the code to check Reg.isPhysical(), but I got a failure for the case 3. So I have to check if Ty is valid here.

DBG_VALUE %0:gpr32, $noreg, !"6", !DIExpression(), debug-location !35; test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir:6:1 line no:6

[LuoYuanke]

Address Arsenault's comments.

[arsenm]

llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp

734

Typo virutal

738

I wouldn't assume if one operand doesn't need assignment, then none do. Treat each operand individually

llvm/test/CodeGen/AArch64/GlobalISel/select-hint.mir

17–21

These baseline check updates should be pre-committed

[LuoYuanke]

llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp

738

Yes, I agree, but this patch just to be conservative to constrain the logic in handling debug instruction, so that it can avoid causing much regression.
I think inline assembly also has such issue, because it may be mixed with physical register and virtual register.
How about adding a TODO here, so that we can improve it in another patch that handle the physical register or register that is assigned register class in underlying code?

[LuoYuanke]

Address Arsenault's comments.

[LuoYuanke]

Add TODO for debug instructions and rebase.

[LuoYuanke]

@arsenm, is there anything more I need to address?

[arsenm]

llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp

738

I don't see this as conservative, just weirdly inconsistent. It would simplify the code and be more correct to just handle all virtual register operands

llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

928–929

Same, better to have simpler code that handles each register individually

[LuoYuanke]

Address Arsenault's comments.

[LuoYuanke]

@arsenm, any other comments?

[LuoYuanke]

ping

[arsenm]

LGTM, although this leaves AMDGPU and all other targets broken. I'm going to file a GitHub issue for this

llvm/lib/CodeGen/RegisterBankInfo.cpp

452–454

I almost think debug instrs shouldn't go through applyDefaultMapping but maybe it is easier this way

llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

910

This should really go to generic code, but I won't insist on you doing that in this patch. We still need a better generic API for constraining. Can you add a fix to move this?

llvm/lib/Target/X86/X86InstructionSelector.cpp

235–237

Same, should get a fixme

[arsenm]

Filed https://github.com/llvm/llvm-project/issues/57010

[LuoYuanke]

Address Arsenault's comments. Thank you for review.

llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp

RegBankSelect::MappingCost RegBankSelect::computeMapping(
   assert(!Saturated && "Possible mapping saturated the cost");
   LLVM_DEBUG(dbgs() << "Evaluating mapping cost for: " << MI);
   LLVM_DEBUG(dbgs() << "With: " << InstrMapping << '\n');
   RepairPts.clear();
   if (BestCost && Cost > *BestCost) {
     LLVM_DEBUG(dbgs() << "Mapping is too expensive from the start\n");
     return Cost;
   }
+  const MachineRegisterInfo &MRI = MI.getMF()->getRegInfo();
 
   // Moreover, to realize this mapping, the register bank of each operand must
   // match this mapping. In other words, we may need to locally reassign the
   // register banks. Account for that repairing cost as well.
   // In this context, local means in the surrounding of MI.
   for (unsigned OpIdx = 0, EndOpIdx = InstrMapping.getNumOperands();
        OpIdx != EndOpIdx; ++OpIdx) {
     const MachineOperand &MO = MI.getOperand(OpIdx);
     if (!MO.isReg())
       continue;
     Register Reg = MO.getReg();
     if (!Reg)
       continue;
+    LLT Ty = MRI.getType(Reg);
+    if (!Ty.isValid())
+      continue;
+
     LLVM_DEBUG(dbgs() << "Opd" << OpIdx << '\n');
     const RegisterBankInfo::ValueMapping &ValMapping =
         InstrMapping.getOperandMapping(OpIdx);
     // If Reg is already properly mapped, this is free.
     bool Assign;
     if (assignmentMatch(Reg, ValMapping, Assign)) {
       LLVM_DEBUG(dbgs() << "=> is free (match).\n");
       continue;
for (RepairingPlacement &RepairPt : RepairPts) {
 
     switch (RepairPt.getKind()) {
     case RepairingPlacement::Reassign:
       assert(ValMapping.NumBreakDowns == 1 &&
              "Reassignment should only be for simple mapping");
       MRI->setRegBank(Reg, *ValMapping.BreakDown[0].RegBank);
       break;
     case RepairingPlacement::Insert:
+      // Don't insert additional instruction for debug instruction.
+      if (MI.isDebugInstr())
+        break;
       OpdMapper.createVRegs(OpIdx);
       if (!repairReg(MO, ValMapping, RepairPt, OpdMapper.getVRegs(OpIdx)))
         return false;
       break;
     default:
       llvm_unreachable("Other kind should not happen");
     }
   }
while (!WorkList.empty()) {
       if (isTargetSpecificOpcode(MI.getOpcode()) && !MI.isPreISelOpcode())
         continue;
 
       // Ignore inline asm instructions: they should use physical
       // registers/regclasses
       if (MI.isInlineAsm())
         continue;
 
-      // Ignore debug info.
-      if (MI.isDebugInstr())
-        continue;
-
       // Ignore IMPLICIT_DEF which must have a regclass.
       if (MI.isImplicitDef())
         continue;
 
       if (!assignInstr(MI)) {
         reportGISelFailure(MF, *TPC, *MORE, "gisel-regbankselect",
                            "unable to map instruction", MI);
         return false;
       }
     }
   }
 
   OptMode = SaveOptMode;
   return false;
 }
 
 //------------------------------------------------------------------------------
 //                  Helper Classes Implementation
 //------------------------------------------------------------------------------
 RegBankSelect::RepairingPlacement::RepairingPlacement(

llvm/lib/CodeGen/RegisterBankInfo.cpp

for (unsigned OpIdx = 0,
     if (!MO.isReg()) {
       LLVM_DEBUG(dbgs() << " is not a register, nothing to be done\n");
       continue;
     }
     if (!MO.getReg()) {
       LLVM_DEBUG(dbgs() << " is $noreg, nothing to be done\n");
       continue;
     }
+    LLT Ty = MRI.getType(MO.getReg());
+    if (!Ty.isValid())
+      continue;
     assert(OpdMapper.getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns !=
                0 &&
            "Invalid mapping");
     assert(OpdMapper.getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns ==
                1 &&
            "This mapping is too complex for this function");
     iterator_range<SmallVectorImpl<Register>::const_iterator> NewRegs =
         OpdMapper.getVRegs(OpIdx);
bool RegisterBankInfo::InstructionMapping::verify(
   // For PHI, we only care about mapping the definition.
   assert(NumOperands == (isCopyLike(MI) ? 1 : MI.getNumOperands()) &&
          "NumOperands must match, see constructor");
   assert(MI.getParent() && MI.getMF() &&
          "MI must be connected to a MachineFunction");
   const MachineFunction &MF = *MI.getMF();
   const RegisterBankInfo *RBI = MF.getSubtarget().getRegBankInfo();
   (void)RBI;
+  const MachineRegisterInfo &MRI = MF.getRegInfo();
 
   for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
     const MachineOperand &MO = MI.getOperand(Idx);
     if (!MO.isReg()) {
       assert(!getOperandMapping(Idx).isValid() &&
              "We should not care about non-reg mapping");
       continue;
     }
     Register Reg = MO.getReg();
     if (!Reg)
       continue;
+    LLT Ty = MRI.getType(Reg);
+    if (!Ty.isValid())
+      continue;
     assert(getOperandMapping(Idx).isValid() &&
            "We must have a mapping for reg operands");
     const RegisterBankInfo::ValueMapping &MOMapping = getOperandMapping(Idx);
     (void)MOMapping;
     // Register size in bits.
     // This size must match what the mapping expects.
     assert(MOMapping.verify(RBI->getSizeInBits(
                Reg, MF.getRegInfo(), *MF.getSubtarget().getRegisterInfo())) &&

llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

getRegClassesForCopy(MachineInstr &I, const TargetInstrInfo &TII,
   // information.
   if (SrcRegBank != DstRegBank && (DstSize == 1 && SrcSize == 1))
     SrcSize = DstSize = 32;
 
   return {getMinClassForRegBank(SrcRegBank, SrcSize, true),
           getMinClassForRegBank(DstRegBank, DstSize, true)};
 }
 
+// FIXME: We need some sort of API in RBI/TRI to allow generic code to
+// constrain operands of simple instructions given a TargetRegisterClass
+// and LLT
+static bool selectDebugInstr(MachineInstr &I, MachineRegisterInfo &MRI,
+                             const RegisterBankInfo &RBI) {
+  for (MachineOperand &MO : I.operands()) {
+    if (!MO.isReg())
+      continue;
+    Register Reg = MO.getReg();
+    if (!Reg)
+      continue;
+    if (Reg.isPhysical())
+      continue;
+    LLT Ty = MRI.getType(Reg);
+    const RegClassOrRegBank &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
+    const TargetRegisterClass *RC =
+        RegClassOrBank.dyn_cast<const TargetRegisterClass *>();
+    if (!RC) {
+      const RegisterBank &RB = *RegClassOrBank.get<const RegisterBank *>();
+      RC = getRegClassForTypeOnBank(Ty, RB);
+      if (!RC) {
+        LLVM_DEBUG(
+            dbgs() << "Warning: DBG_VALUE operand has unexpected size/bank\n");
+        break;
+      }
+    }
+    RBI.constrainGenericRegister(Reg, *RC, MRI);
+  }
+
+  return true;
+}
+
 static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
                        MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
                        const RegisterBankInfo &RBI) {
   Register DstReg = I.getOperand(0).getReg();
   Register SrcReg = I.getOperand(1).getReg();
   const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI);
   const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI);
 
   // Find the correct register classes for the source and destination registers.
   const TargetRegisterClass *SrcRC;
   const TargetRegisterClass *DstRC;
   std::tie(SrcRC, DstRC) = getRegClassesForCopy(I, TII, MRI, TRI, RBI);
 
   if (!DstRC) {
     LLVM_DEBUG(dbgs() << "Unexpected dest size "
                       << RBI.getSizeInBits(DstReg, MRI, TRI) << '\n');
     return false;
   }
 
if (Opcode == TargetOpcode::PHI || Opcode == TargetOpcode::G_PHI) {
       I.setDesc(TII.get(TargetOpcode::PHI));
 
       return RBI.constrainGenericRegister(DefReg, *DefRC, MRI);
     }
 
     if (I.isCopy())
       return selectCopy(I, TII, MRI, TRI, RBI);
 
+    if (I.isDebugInstr())
+      return selectDebugInstr(I, MRI, RBI);
+
     return true;
   }
 
 
   if (I.getNumOperands() != I.getNumExplicitOperands()) {
     LLVM_DEBUG(
         dbgs() << "Generic instruction has unexpected implicit operands\n");
     return false;

llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp

AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   SmallVector<unsigned, 4> OpSize(NumOperands);
   SmallVector<PartialMappingIdx, 4> OpRegBankIdx(NumOperands);
   for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
     auto &MO = MI.getOperand(Idx);
     if (!MO.isReg() || !MO.getReg())
       continue;
 
     LLT Ty = MRI.getType(MO.getReg());
+    if (!Ty.isValid())
+      continue;
     OpSize[Idx] = Ty.getSizeInBits();
 
     // As a top-level guess, vectors go in FPRs, scalars and pointers in GPRs.
     // For floating-point instructions, scalars go in FPRs.
     if (Ty.isVector() || isPreISelGenericFloatingPointOpcode(Opc) ||
         Ty.getSizeInBits() > 64)
       OpRegBankIdx[Idx] = PMI_FirstFPR;
     else
case TargetOpcode::G_LLROUND: {
     break;
   }
   }
 
   // Finally construct the computed mapping.
   SmallVector<const ValueMapping *, 8> OpdsMapping(NumOperands);
   for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
     if (MI.getOperand(Idx).isReg() && MI.getOperand(Idx).getReg()) {
+      LLT Ty = MRI.getType(MI.getOperand(Idx).getReg());
+      if (!Ty.isValid())
+        continue;
       auto Mapping = getValueMapping(OpRegBankIdx[Idx], OpSize[Idx]);
       if (!Mapping->isValid())
         return getInvalidInstructionMapping();
 
       OpdsMapping[Idx] = Mapping;
     }
   }
 
   return getInstructionMapping(DefaultMappingID, Cost,
                                getOperandsMapping(OpdsMapping), NumOperands);
 }

llvm/lib/Target/X86/X86InstructionSelector.cpp

private:
   bool selectAnyext(MachineInstr &I, MachineRegisterInfo &MRI,
                     MachineFunction &MF) const;
   bool selectCmp(MachineInstr &I, MachineRegisterInfo &MRI,
                  MachineFunction &MF) const;
   bool selectFCmp(MachineInstr &I, MachineRegisterInfo &MRI,
                   MachineFunction &MF) const;
   bool selectUadde(MachineInstr &I, MachineRegisterInfo &MRI,
                    MachineFunction &MF) const;
+  bool selectDebugInstr(MachineInstr &I, MachineRegisterInfo &MRI) const;
   bool selectCopy(MachineInstr &I, MachineRegisterInfo &MRI) const;
   bool selectUnmergeValues(MachineInstr &I, MachineRegisterInfo &MRI,
                            MachineFunction &MF);
   bool selectMergeValues(MachineInstr &I, MachineRegisterInfo &MRI,
                          MachineFunction &MF);
   bool selectInsert(MachineInstr &I, MachineRegisterInfo &MRI,
                     MachineFunction &MF) const;
   bool selectExtract(MachineInstr &I, MachineRegisterInfo &MRI,
static const TargetRegisterClass *getRegClassFromGRPhysReg(Register Reg) {
   if (X86::GR16RegClass.contains(Reg))
     return &X86::GR16RegClass;
   if (X86::GR8RegClass.contains(Reg))
     return &X86::GR8RegClass;
 
   llvm_unreachable("Unknown RegClass for PhysReg!");
 }
 
+// FIXME: We need some sort of API in RBI/TRI to allow generic code to
+// constrain operands of simple instructions given a TargetRegisterClass
+// and LLT
+bool X86InstructionSelector::selectDebugInstr(MachineInstr &I,
+                                              MachineRegisterInfo &MRI) const {
+  for (MachineOperand &MO : I.operands()) {
+    if (!MO.isReg())
+      continue;
+    Register Reg = MO.getReg();
+    if (!Reg)
+      continue;
+    if (Reg.isPhysical())
+      continue;
+    LLT Ty = MRI.getType(Reg);
+    const RegClassOrRegBank &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
+    const TargetRegisterClass *RC =
+        RegClassOrBank.dyn_cast<const TargetRegisterClass *>();
+    if (!RC) {
+      const RegisterBank &RB = *RegClassOrBank.get<const RegisterBank *>();
+      RC = getRegClass(Ty, RB);
+      if (!RC) {
+        LLVM_DEBUG(
+            dbgs() << "Warning: DBG_VALUE operand has unexpected size/bank\n");
+        break;
+      }
+    }
+    RBI.constrainGenericRegister(Reg, *RC, MRI);
+  }
+
+  return true;
+}
+
 // Set X86 Opcode and constrain DestReg.
 bool X86InstructionSelector::selectCopy(MachineInstr &I,
                                         MachineRegisterInfo &MRI) const {
   Register DstReg = I.getOperand(0).getReg();
   const unsigned DstSize = RBI.getSizeInBits(DstReg, MRI, TRI);
   const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI);
 
   Register SrcReg = I.getOperand(1).getReg();
if (!isPreISelGenericOpcode(Opcode)) {
     // Certain non-generic instructions also need some special handling.
 
     if (Opcode == TargetOpcode::LOAD_STACK_GUARD)
       return false;
 
     if (I.isCopy())
       return selectCopy(I, MRI);
 
+    if (I.isDebugInstr())
+      return selectDebugInstr(I, MRI);
+
     return true;
   }
 
   assert(I.getNumOperands() == I.getNumExplicitOperands() &&
          "Generic instruction has unexpected implicit operands\n");
 
   if (selectImpl(I, *CoverageInfo))
     return true;

llvm/lib/Target/X86/X86RegisterBankInfo.cpp

 
 void X86RegisterBankInfo::getInstrPartialMappingIdxs(
     const MachineInstr &MI, const MachineRegisterInfo &MRI, const bool isFP,
     SmallVectorImpl<PartialMappingIdx> &OpRegBankIdx) {
 
   unsigned NumOperands = MI.getNumOperands();
   for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
     auto &MO = MI.getOperand(Idx);
-    if (!MO.isReg())
+    if (!MO.isReg() || !MO.getReg())
       OpRegBankIdx[Idx] = PMI_None;
     else
       OpRegBankIdx[Idx] = getPartialMappingIdx(MRI.getType(MO.getReg()), isFP);
   }
 }
 
 bool X86RegisterBankInfo::getInstrValueMapping(
     const MachineInstr &MI,
     const SmallVectorImpl<PartialMappingIdx> &OpRegBankIdx,
     SmallVectorImpl<const ValueMapping *> &OpdsMapping) {
 
   unsigned NumOperands = MI.getNumOperands();
   for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
     if (!MI.getOperand(Idx).isReg())
       continue;
+    if (!MI.getOperand(Idx).getReg())
+      continue;
 
     auto Mapping = getValueMapping(OpRegBankIdx[Idx], 1);
     if (!Mapping->isValid())
       return false;
 
     OpdsMapping[Idx] = Mapping;
   }
   return true;

llvm/test/CodeGen/AArch64/GlobalISel/select-dbg-value.mir

 legalized:       true
 regBankSelected: true
 body: |
   bb.0:
     liveins: $w0
     ; CHECK-LABEL: name: test_dbg_value_dead
     ; CHECK: liveins: $w0
     ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: DBG_VALUE %0:gpr, $noreg, !7, !DIExpression(), debug-location !9
+    ; CHECK-NEXT: DBG_VALUE %0:gpr32, $noreg, !7, !DIExpression(), debug-location !9
     %0:gpr(s32) = COPY $w0
     DBG_VALUE %0(s32), $noreg, !7, !DIExpression(), debug-location !9
 ...

llvm/test/CodeGen/AArch64/GlobalISel/select-hint.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple aarch64 -debugify-and-strip-all-safe -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
 
 # Check that we remove hints during selection.
 
 ...
 ---
 name:            assert_zext_gpr
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: assert_zext_gpr
     ; CHECK: liveins: $w0, $w1
     ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: %copy:gpr32all = COPY $w0
+    ; CHECK-NEXT: %copy:gpr32 = COPY $w0
     ; CHECK-NEXT: $w1 = COPY %copy
     ; CHECK-NEXT: RET_ReallyLR implicit $w1
     %copy:gpr(s32) = COPY $w0
     %copy_assert_zext:gpr(s32) = G_ASSERT_ZEXT %copy, 16
     $w1 = COPY %copy_assert_zext(s32)
     RET_ReallyLR implicit $w1
 
 ...
 ---
 name:            assert_zext_fpr

 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: assert_sext_gpr
     ; CHECK: liveins: $w0, $w1
     ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: %copy:gpr32all = COPY $w0
+    ; CHECK-NEXT: %copy:gpr32 = COPY $w0
     ; CHECK-NEXT: $w1 = COPY %copy
     ; CHECK-NEXT: RET_ReallyLR implicit $w1
     %copy:gpr(s32) = COPY $w0
     %copy_assert_sext:gpr(s32) = G_ASSERT_SEXT %copy, 16
     $w1 = COPY %copy_assert_sext(s32)
     RET_ReallyLR implicit $w1
 
 ...

llvm/test/DebugInfo/AArch64/debug-reg-bank.ll

 ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 ; RUN: llc < %s -mtriple=aarch64-linux-gnu -O0 -global-isel -stop-after instruction-select | FileCheck %s
 
 define void @foo(i32 %n) !dbg !7 {
   ; CHECK-LABEL: name: foo
   ; CHECK: bb.1.entry:
   ; CHECK-NEXT:   liveins: $w0
   ; CHECK-NEXT: {{  $}}
-  ; CHECK-NEXT:   DBG_VALUE %{{[0-9]+}}:_, $noreg, !12, !DIExpression(), debug-location !19
+  ; CHECK-NEXT:   DBG_VALUE %2:gpr32, $noreg, !12, !DIExpression(), debug-location !19
   ; CHECK-NEXT:   RET_ReallyLR debug-location !20
 entry:
   %m = mul i32 %n, 13
   call void @llvm.dbg.value(metadata i32 %m, i64 0, metadata !12, metadata !19), !dbg !20
   ret void, !dbg !21
 }
 
 declare void @llvm.dbg.value(metadata, i64, metadata, metadata)

llvm/test/DebugInfo/X86/debug-reg-bank.ll

 ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-linux-gnu -O0 -global-isel -stop-after instruction-select | FileCheck %s
 
 define void @foo(i32 %n) !dbg !7 {
   ; CHECK-LABEL: name: foo
   ; CHECK: bb.1.entry:
   ; CHECK-NEXT:   liveins: $edi
   ; CHECK-NEXT: {{  $}}
-  ; CHECK-NEXT:   DBG_VALUE %{{[0-9]+}}:_, $noreg, !12, !DIExpression(), debug-location !19
+  ; CHECK-NEXT:   DBG_VALUE %2:gr32, $noreg, !12, !DIExpression(), debug-location !19
   ; CHECK-NEXT:   RET 0, debug-location !20
 entry:
   %m = mul i32 %n, 13
   call void @llvm.dbg.value(metadata i32 %m, i64 0, metadata !12, metadata !19), !dbg !20
   ret void, !dbg !21
 }
 
 declare void @llvm.dbg.value(metadata, i64, metadata, metadata)