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Differential D127043

[X86][AMX] Fill the shape information with virtual register.
Needs ReviewPublic

Authored by LuoYuanke on Jun 3 2022, 8:36 PM.

Details

Reviewers
xiangzhangllvm
yubing
Summary

When fill the shape information of tile configure, we need to know
the tile physical register. If the shape (row, column) is allocated with
physical register, the physical register may be re-defined before
writing it to stack. The re-def may happen during split or spill
registers. If the shape is in virtual register, there is no such
problem. In below example, the value 2 of %al is filled to config
register. The actual value should be 8.
%al = 8
mov %al, %bl ; register split
%al = 2
store stack.cfg, %al ; config
ldtilecfg
...
%t = tilezero %al,...
With virtual register, there is no such issue.
%row = 8
store stack.cfg, %row ; config
ldtilecfg
...
%t = tilezero %row,...

Diff Detail

Revision Contents

PathSize
llvm/
include/
llvm/
CodeGen/
4 lines
lib/
CodeGen/
3 lines
Target/
X86/
5 lines
10 lines
test/
CodeGen/
X86/
AMX/
15 lines
11 lines
12 lines
6 lines
2 lines

Diff 434237

llvm/include/llvm/CodeGen/TargetPassConfig.h

Show First 20 Lines • Show All 398 Lines • ▼ Show 20 Linesprotected:
/// ///
/// Note if the target overloads addRegAssignAndRewriteOptimized, this may not /// Note if the target overloads addRegAssignAndRewriteOptimized, this may not
/// be honored. This is also not generally used for the the fast variant, /// be honored. This is also not generally used for the the fast variant,
/// where the allocation and rewriting are done in one pass. /// where the allocation and rewriting are done in one pass.
virtual bool addPreRewrite() { virtual bool addPreRewrite() {
return false; return false;
} }
/// addPostFastRegAllocRewrite - Add passes to the optimized register
/// allocation pipeline after fast register allocation is complete.
virtual bool addPostFastRegAllocRewrite() { return false; }
/// Add passes to be run immediately after virtual registers are rewritten /// Add passes to be run immediately after virtual registers are rewritten
/// to physical registers. /// to physical registers.
virtual void addPostRewrite() { } virtual void addPostRewrite() { }
/// This method may be implemented by targets that want to run passes after /// This method may be implemented by targets that want to run passes after
/// register allocation pass pipeline but before prolog-epilog insertion. /// register allocation pass pipeline but before prolog-epilog insertion.
virtual void addPostRegAlloc() { } virtual void addPostRegAlloc() { }
▲ Show 20 Lines • Show All 54 Lines • Show Last 20 Lines

llvm/lib/CodeGen/TargetPassConfig.cpp

Show First 20 Lines • Show All 1,408 Lines • ▼ Show 20 Lines
bool TargetPassConfig::addRegAssignAndRewriteFast() { bool TargetPassConfig::addRegAssignAndRewriteFast() {
if (RegAlloc != (RegisterRegAlloc::FunctionPassCtor)&useDefaultRegisterAllocator && if (RegAlloc != (RegisterRegAlloc::FunctionPassCtor)&useDefaultRegisterAllocator &&
RegAlloc != (RegisterRegAlloc::FunctionPassCtor)&createFastRegisterAllocator) RegAlloc != (RegisterRegAlloc::FunctionPassCtor)&createFastRegisterAllocator)
report_fatal_error("Must use fast (default) register allocator for unoptimized regalloc."); report_fatal_error("Must use fast (default) register allocator for unoptimized regalloc.");
addPass(createRegAllocPass(false)); addPass(createRegAllocPass(false));
// Allow targets to change the register assignments after
// fast register allocation.
addPostFastRegAllocRewrite();
return true; return true;
} }
bool TargetPassConfig::addRegAssignAndRewriteOptimized() { bool TargetPassConfig::addRegAssignAndRewriteOptimized() {
// Add the selected register allocation pass. // Add the selected register allocation pass.
addPass(createRegAllocPass(true)); addPass(createRegAllocPass(true));
// Allow targets to change the register assignments before rewriting. // Allow targets to change the register assignments before rewriting.
▲ Show 20 Lines • Show All 147 Lines • Show Last 20 Lines

llvm/lib/Target/X86/X86FastTileConfig.cpp

Show First 20 Lines • Show All 140 Lines • ▼ Show 20 Lines if (MI.getOpcode() != X86::PLDTILECFGV) {
// 49 tile1.rows Tile 1 rows. // 49 tile1.rows Tile 1 rows.
// 50 tile2.rows Tile 2 rows. // 50 tile2.rows Tile 2 rows.
// ... (sequence continues) // ... (sequence continues)
// 55 tile7.rows Tile 7 rows. // 55 tile7.rows Tile 7 rows.
// 56-63 reserved, must be zero // 56-63 reserved, must be zero
int RowOffset = 48 + TMMIdx; int RowOffset = 48 + TMMIdx;
int ColOffset = 16 + TMMIdx * 2; int ColOffset = 16 + TMMIdx * 2;
Register SubRowReg = TRI->getSubReg(RowReg, X86::sub_8bit);
BuildMI(MBB, MI, DL, TII->get(X86::IMPLICIT_DEF), SubRowReg);
MachineInstrBuilder StoreRow = MachineInstrBuilder StoreRow =
BuildMI(MBB, MI, DL, TII->get(X86::MOV8mr)); BuildMI(MBB, MI, DL, TII->get(X86::MOV8mr));
addFrameReference(StoreRow, SS, RowOffset).addReg(SubRowReg); addFrameReference(StoreRow, SS, RowOffset)
.addReg(RowReg, 0, X86::sub_8bit);
MachineInstrBuilder StoreCol = MachineInstrBuilder StoreCol =
BuildMI(MBB, MI, DL, TII->get(X86::MOV16mr)); BuildMI(MBB, MI, DL, TII->get(X86::MOV16mr));
addFrameReference(StoreCol, SS, ColOffset).addReg(ColReg); addFrameReference(StoreCol, SS, ColOffset).addReg(ColReg);
} }
ShapeInfos.clear(); ShapeInfos.clear();
Change = true; Change = true;
} }
Show All 27 Lines

llvm/lib/Target/X86/X86TargetMachine.cpp

Show First 20 Lines • Show All 379 Lines • ▼ Show 20 Linespublic:
bool addIRTranslator() override; bool addIRTranslator() override;
bool addLegalizeMachineIR() override; bool addLegalizeMachineIR() override;
bool addRegBankSelect() override; bool addRegBankSelect() override;
bool addGlobalInstructionSelect() override; bool addGlobalInstructionSelect() override;
bool addILPOpts() override; bool addILPOpts() override;
bool addPreISel() override; bool addPreISel() override;
void addMachineSSAOptimization() override; void addMachineSSAOptimization() override;
void addPreRegAlloc() override; void addPreRegAlloc() override;
bool addPostFastRegAllocRewrite() override;
void addPostRegAlloc() override; void addPostRegAlloc() override;
void addPreEmitPass() override; void addPreEmitPass() override;
void addPreEmitPass2() override; void addPreEmitPass2() override;
void addPreSched2() override; void addPreSched2() override;
bool addPreRewrite() override; bool addPreRewrite() override;
bool addRegAssignAndRewriteFast() override; bool addRegAssignAndRewriteFast() override;
std::unique_ptr<CSEConfigBase> getCSEConfig() const override; std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
▲ Show 20 Lines • Show All 217 Lines • ▼ Show 20 Lines
static bool onlyAllocateTileRegisters(const TargetRegisterInfo &TRI, static bool onlyAllocateTileRegisters(const TargetRegisterInfo &TRI,
const TargetRegisterClass &RC) { const TargetRegisterClass &RC) {
return static_cast<const X86RegisterInfo &>(TRI).isTileRegisterClass(&RC); return static_cast<const X86RegisterInfo &>(TRI).isTileRegisterClass(&RC);
} }
bool X86PassConfig::addRegAssignAndRewriteFast() { bool X86PassConfig::addRegAssignAndRewriteFast() {
// Allocate AMX registers separately. // Allocate AMX registers separately.
if (EnableTileRAPass) if (EnableTileRAPass) {
addPass(createFastRegisterAllocator(onlyAllocateTileRegisters, false)); addPass(createFastRegisterAllocator(onlyAllocateTileRegisters, false));
return TargetPassConfig::addRegAssignAndRewriteFast();
}
bool X86PassConfig::addPostFastRegAllocRewrite() {
addPass(createX86FastTileConfigPass()); addPass(createX86FastTileConfigPass());
return true; }
return TargetPassConfig::addRegAssignAndRewriteFast();
} }
bool X86PassConfig::addPreRewrite() { bool X86PassConfig::addPreRewrite() {
addPass(createX86TileConfigPass()); addPass(createX86TileConfigPass());
return true; return true;
} }
std::unique_ptr<CSEConfigBase> X86PassConfig::getCSEConfig() const { std::unique_ptr<CSEConfigBase> X86PassConfig::getCSEConfig() const {
return getStandardCSEConfigForOpt(TM->getOptLevel()); return getStandardCSEConfigForOpt(TM->getOptLevel());
} }

llvm/test/CodeGen/X86/AMX/amx-across-func.ll

Show First 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; O0-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; O0-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; O0-NEXT: leaq {{[0-9]+}}(%rsp), %rdx ; O0-NEXT: leaq {{[0-9]+}}(%rsp), %rdx
; O0-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; O0-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; O0-NEXT: leaq {{[0-9]+}}(%rsp), %rdi ; O0-NEXT: leaq {{[0-9]+}}(%rsp), %rdi
; O0-NEXT: movq %rdi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; O0-NEXT: movq %rdi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; O0-NEXT: movl $buf, %r8d ; O0-NEXT: movl $buf, %r8d
; O0-NEXT: movl $32, %r9d ; O0-NEXT: movl $32, %r9d
; O0-NEXT: movw $8, %si ; O0-NEXT: movw $8, %si
; O0-NEXT: # implicit-def: $al
; O0-NEXT: movb %al, {{[0-9]+}}(%rsp) ; O0-NEXT: movb %al, {{[0-9]+}}(%rsp)
; O0-NEXT: movw %si, {{[0-9]+}}(%rsp) ; O0-NEXT: movw %si, {{[0-9]+}}(%rsp)
; O0-NEXT: ldtilecfg {{[0-9]+}}(%rsp) ; O0-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
; O0-NEXT: tileloadd (%r8,%r9), %tmm0 ; O0-NEXT: tileloadd (%r8,%r9), %tmm0
; O0-NEXT: movl $64, %r8d ; O0-NEXT: movl $64, %r8d
; O0-NEXT: movw $8, %si ; O0-NEXT: movw $8, %si
; O0-NEXT: tilestored %tmm0, (%rdi,%r8) ; O0-NEXT: tilestored %tmm0, (%rdi,%r8)
; O0-NEXT: movl $32, %edi ; O0-NEXT: movl $32, %edi
; O0-NEXT: movl $buf+1024, %esi ; O0-NEXT: movl $buf+1024, %esi
; O0-NEXT: movw $8, %ax ; O0-NEXT: movw $8, %ax
; O0-NEXT: # implicit-def: $al
; O0-NEXT: movb %al, {{[0-9]+}}(%rsp) ; O0-NEXT: movb %al, {{[0-9]+}}(%rsp)
; O0-NEXT: movw %cx, {{[0-9]+}}(%rsp) ; O0-NEXT: movw %cx, {{[0-9]+}}(%rsp)
; O0-NEXT: ldtilecfg {{[0-9]+}}(%rsp) ; O0-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
; O0-NEXT: tileloadd (%rsi,%rdi), %tmm0 ; O0-NEXT: tileloadd (%rsi,%rdi), %tmm0
; O0-NEXT: movl $64, %esi ; O0-NEXT: movl $64, %esi
; O0-NEXT: movw $8, %ax ; O0-NEXT: movw $8, %ax
; O0-NEXT: tilestored %tmm0, (%rdx,%rsi) ; O0-NEXT: tilestored %tmm0, (%rdx,%rsi)
; O0-NEXT: vzeroupper ; O0-NEXT: vzeroupper
; O0-NEXT: callq foo ; O0-NEXT: callq foo
; O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r8 # 8-byte Reload ; O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r8 # 8-byte Reload
; O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r9 # 8-byte Reload ; O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r9 # 8-byte Reload
; O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rsi # 8-byte Reload ; O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rsi # 8-byte Reload
; O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload ; O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload
; O0-NEXT: movw {{[-0-9]+}}(%r{{[sb]}}p), %cx # 2-byte Reload ; O0-NEXT: movw {{[-0-9]+}}(%r{{[sb]}}p), %cx # 2-byte Reload
; O0-NEXT: movw {{[-0-9]+}}(%r{{[sb]}}p), %ax # 2-byte Reload ; O0-NEXT: movw {{[-0-9]+}}(%r{{[sb]}}p), %ax # 2-byte Reload
; O0-NEXT: # implicit-def: $al
; O0-NEXT: movb %al, {{[0-9]+}}(%rsp) ; O0-NEXT: movb %al, {{[0-9]+}}(%rsp)
; O0-NEXT: movw %cx, {{[0-9]+}}(%rsp) ; O0-NEXT: movw %cx, {{[0-9]+}}(%rsp)
; O0-NEXT: ldtilecfg {{[0-9]+}}(%rsp) ; O0-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
; O0-NEXT: movl $32, %r10d ; O0-NEXT: movl $32, %r10d
; O0-NEXT: movl $buf+2048, %edi ; O0-NEXT: movl $buf+2048, %edi
; O0-NEXT: tileloadd (%rdi,%r10), %tmm0 ; O0-NEXT: tileloadd (%rdi,%r10), %tmm0
; O0-NEXT: movl $64, %edi ; O0-NEXT: movl $64, %edi
; O0-NEXT: tilestored %tmm0, (%rsi,%rdi) ; O0-NEXT: tilestored %tmm0, (%rsi,%rdi)
; O0-NEXT: movl $64, %r10d ; O0-NEXT: movl $64, %r10d
; O0-NEXT: movw $8, %di ; O0-NEXT: movw $8, %di
; O0-NEXT: # implicit-def: $al
; O0-NEXT: movb %al, {{[0-9]+}}(%rsp) ; O0-NEXT: movb %al, {{[0-9]+}}(%rsp)
; O0-NEXT: movw %di, {{[0-9]+}}(%rsp) ; O0-NEXT: movw %di, {{[0-9]+}}(%rsp)
; O0-NEXT: ldtilecfg {{[0-9]+}}(%rsp) ; O0-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
; O0-NEXT: tileloadd (%r8,%r10), %tmm0 ; O0-NEXT: tileloadd (%r8,%r10), %tmm0
; O0-NEXT: movabsq $64, %r8 ; O0-NEXT: movabsq $64, %r8
; O0-NEXT: tilestored %tmm0, 1024(%rsp,%r8) # 1024-byte Folded Spill ; O0-NEXT: tilestored %tmm0, 1024(%rsp,%r8) # 1024-byte Folded Spill
; O0-NEXT: movl $64, %r10d ; O0-NEXT: movl $64, %r10d
; O0-NEXT: movw $8, %r8w ; O0-NEXT: movw $8, %r8w
; O0-NEXT: # implicit-def: $al
; O0-NEXT: movb %al, {{[0-9]+}}(%rsp) ; O0-NEXT: movb %al, {{[0-9]+}}(%rsp)
; O0-NEXT: movw %cx, {{[0-9]+}}(%rsp) ; O0-NEXT: movw %cx, {{[0-9]+}}(%rsp)
; O0-NEXT: # implicit-def: $al
; O0-NEXT: movb %al, {{[0-9]+}}(%rsp) ; O0-NEXT: movb %al, {{[0-9]+}}(%rsp)
; O0-NEXT: movw %cx, {{[0-9]+}}(%rsp) ; O0-NEXT: movw %cx, {{[0-9]+}}(%rsp)
; O0-NEXT: # implicit-def: $al
; O0-NEXT: movb %al, {{[0-9]+}}(%rsp) ; O0-NEXT: movb %al, {{[0-9]+}}(%rsp)
; O0-NEXT: movw %di, {{[0-9]+}}(%rsp) ; O0-NEXT: movw %di, {{[0-9]+}}(%rsp)
; O0-NEXT: # implicit-def: $al
; O0-NEXT: movb %al, {{[0-9]+}}(%rsp) ; O0-NEXT: movb %al, {{[0-9]+}}(%rsp)
; O0-NEXT: movw %cx, {{[0-9]+}}(%rsp) ; O0-NEXT: movw %cx, {{[0-9]+}}(%rsp)
; O0-NEXT: # implicit-def: $r8b
; O0-NEXT: movb %r8b, {{[0-9]+}}(%rsp) ; O0-NEXT: movb %r8b, {{[0-9]+}}(%rsp)
; O0-NEXT: movw %cx, {{[0-9]+}}(%rsp) ; O0-NEXT: movw %cx, {{[0-9]+}}(%rsp)
; O0-NEXT: ldtilecfg {{[0-9]+}}(%rsp) ; O0-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
; O0-NEXT: tileloadd (%r9,%r10), %tmm2 ; O0-NEXT: tileloadd (%r9,%r10), %tmm2
; O0-NEXT: movl $64, %r8d ; O0-NEXT: movl $64, %r8d
; O0-NEXT: tileloadd (%rsi,%r8), %tmm0 ; O0-NEXT: tileloadd (%rsi,%r8), %tmm0
; O0-NEXT: movw $8, %si ; O0-NEXT: movw $8, %si
; O0-NEXT: movabsq $64, %r8 ; O0-NEXT: movabsq $64, %r8
▲ Show 20 Lines • Show All 174 Lines • ▼ Show 20 Lines
; O0-NEXT: jmp .LBB2_4 ; O0-NEXT: jmp .LBB2_4
; O0-NEXT: .LBB2_3: # =>This Inner Loop Header: Depth=1 ; O0-NEXT: .LBB2_3: # =>This Inner Loop Header: Depth=1
; O0-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; O0-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload
; O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload ; O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload
; O0-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill ; O0-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
; O0-NEXT: movl $buf, %edx ; O0-NEXT: movl $buf, %edx
; O0-NEXT: movl $32, %esi ; O0-NEXT: movl $32, %esi
; O0-NEXT: movw $8, %ax ; O0-NEXT: movw $8, %ax
; O0-NEXT: # implicit-def: $al
; O0-NEXT: movb %al, {{[0-9]+}}(%rsp) ; O0-NEXT: movb %al, {{[0-9]+}}(%rsp)
; O0-NEXT: movw %ax, {{[0-9]+}}(%rsp) ; O0-NEXT: movw %ax, {{[0-9]+}}(%rsp)
; O0-NEXT: ldtilecfg {{[0-9]+}}(%rsp) ; O0-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
; O0-NEXT: tileloadd (%rdx,%rsi), %tmm0 ; O0-NEXT: tileloadd (%rdx,%rsi), %tmm0
; O0-NEXT: movl $64, %edx ; O0-NEXT: movl $64, %edx
; O0-NEXT: movw $8, %ax ; O0-NEXT: movw $8, %ax
; O0-NEXT: tilestored %tmm0, (%rcx,%rdx) ; O0-NEXT: tilestored %tmm0, (%rcx,%rdx)
; O0-NEXT: callq foo ; O0-NEXT: callq foo
; O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload ; O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload
; O0-NEXT: movl $64, %edx ; O0-NEXT: movl $64, %edx
; O0-NEXT: movw $8, %ax ; O0-NEXT: movw $8, %ax
; O0-NEXT: # implicit-def: $al
; O0-NEXT: movb %al, {{[0-9]+}}(%rsp) ; O0-NEXT: movb %al, {{[0-9]+}}(%rsp)
; O0-NEXT: movw %ax, {{[0-9]+}}(%rsp) ; O0-NEXT: movw %ax, {{[0-9]+}}(%rsp)
; O0-NEXT: ldtilecfg {{[0-9]+}}(%rsp) ; O0-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
; O0-NEXT: tileloadd (%rcx,%rdx), %tmm0 ; O0-NEXT: tileloadd (%rcx,%rdx), %tmm0
; O0-NEXT: movl $32, %edx ; O0-NEXT: movl $32, %edx
; O0-NEXT: movl $buf+2048, %ecx ; O0-NEXT: movl $buf+2048, %ecx
; O0-NEXT: movw $8, %ax ; O0-NEXT: movw $8, %ax
; O0-NEXT: tilestored %tmm0, (%rcx,%rdx) ; O0-NEXT: tilestored %tmm0, (%rcx,%rdx)
; O0-NEXT: callq foo ; O0-NEXT: callq foo
; O0-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; O0-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload
; O0-NEXT: addl $1, %eax ; O0-NEXT: addl $1, %eax
; O0-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill ; O0-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
; O0-NEXT: cmpl $0, %eax ; O0-NEXT: cmpl $0, %eax
; O0-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill ; O0-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
; O0-NEXT: je .LBB2_2 ; O0-NEXT: je .LBB2_2
; O0-NEXT: jmp .LBB2_3 ; O0-NEXT: jmp .LBB2_3
; O0-NEXT: .LBB2_4: ; O0-NEXT: .LBB2_4:
; O0-NEXT: callq foo ; O0-NEXT: callq foo
; O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload ; O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload
; O0-NEXT: movl $32, %esi ; O0-NEXT: movl $32, %esi
; O0-NEXT: movl $buf+1024, %edx ; O0-NEXT: movl $buf+1024, %edx
; O0-NEXT: movw $8, %ax ; O0-NEXT: movw $8, %ax
; O0-NEXT: # implicit-def: $al
; O0-NEXT: movb %al, {{[0-9]+}}(%rsp) ; O0-NEXT: movb %al, {{[0-9]+}}(%rsp)
; O0-NEXT: movw %ax, {{[0-9]+}}(%rsp) ; O0-NEXT: movw %ax, {{[0-9]+}}(%rsp)
; O0-NEXT: ldtilecfg {{[0-9]+}}(%rsp) ; O0-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
; O0-NEXT: tileloadd (%rdx,%rsi), %tmm0 ; O0-NEXT: tileloadd (%rdx,%rsi), %tmm0
; O0-NEXT: movl $64, %edx ; O0-NEXT: movl $64, %edx
; O0-NEXT: movw $8, %ax ; O0-NEXT: movw $8, %ax
; O0-NEXT: tilestored %tmm0, (%rcx,%rdx) ; O0-NEXT: tilestored %tmm0, (%rcx,%rdx)
; O0-NEXT: movl $64, %edx ; O0-NEXT: movl $64, %edx
; O0-NEXT: movw $8, %ax ; O0-NEXT: movw $8, %ax
; O0-NEXT: # implicit-def: $al
; O0-NEXT: movb %al, {{[0-9]+}}(%rsp) ; O0-NEXT: movb %al, {{[0-9]+}}(%rsp)
; O0-NEXT: movw %ax, {{[0-9]+}}(%rsp) ; O0-NEXT: movw %ax, {{[0-9]+}}(%rsp)
; O0-NEXT: ldtilecfg {{[0-9]+}}(%rsp) ; O0-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
; O0-NEXT: tileloadd (%rcx,%rdx), %tmm0 ; O0-NEXT: tileloadd (%rcx,%rdx), %tmm0
; O0-NEXT: movl $32, %edx ; O0-NEXT: movl $32, %edx
; O0-NEXT: movl $buf+1024, %ecx ; O0-NEXT: movl $buf+1024, %ecx
; O0-NEXT: movw $8, %ax ; O0-NEXT: movw $8, %ax
; O0-NEXT: tilestored %tmm0, (%rcx,%rdx) ; O0-NEXT: tilestored %tmm0, (%rcx,%rdx)
▲ Show 20 Lines • Show All 152 Lines • ▼ Show 20 Lines
; O0-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; O0-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload
; O0-NEXT: cmpl $0, %eax ; O0-NEXT: cmpl $0, %eax
; O0-NEXT: jle .LBB3_3 ; O0-NEXT: jle .LBB3_3
; O0-NEXT: # %bb.2: # in Loop: Header=BB3_1 Depth=1 ; O0-NEXT: # %bb.2: # in Loop: Header=BB3_1 Depth=1
; O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload ; O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload
; O0-NEXT: movl $buf, %edx ; O0-NEXT: movl $buf, %edx
; O0-NEXT: movl $32, %esi ; O0-NEXT: movl $32, %esi
; O0-NEXT: movw $8, %ax ; O0-NEXT: movw $8, %ax
; O0-NEXT: # implicit-def: $al
; O0-NEXT: movb %al, {{[0-9]+}}(%rsp) ; O0-NEXT: movb %al, {{[0-9]+}}(%rsp)
; O0-NEXT: movw %ax, {{[0-9]+}}(%rsp) ; O0-NEXT: movw %ax, {{[0-9]+}}(%rsp)
; O0-NEXT: ldtilecfg {{[0-9]+}}(%rsp) ; O0-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
; O0-NEXT: tileloadd (%rdx,%rsi), %tmm0 ; O0-NEXT: tileloadd (%rdx,%rsi), %tmm0
; O0-NEXT: movl $64, %edx ; O0-NEXT: movl $64, %edx
; O0-NEXT: movw $8, %ax ; O0-NEXT: movw $8, %ax
; O0-NEXT: tilestored %tmm0, (%rcx,%rdx) ; O0-NEXT: tilestored %tmm0, (%rcx,%rdx)
; O0-NEXT: callq foo ; O0-NEXT: callq foo
; O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload ; O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload
; O0-NEXT: movl $64, %edx ; O0-NEXT: movl $64, %edx
; O0-NEXT: movw $8, %ax ; O0-NEXT: movw $8, %ax
; O0-NEXT: # implicit-def: $al
; O0-NEXT: movb %al, {{[0-9]+}}(%rsp) ; O0-NEXT: movb %al, {{[0-9]+}}(%rsp)
; O0-NEXT: movw %ax, {{[0-9]+}}(%rsp) ; O0-NEXT: movw %ax, {{[0-9]+}}(%rsp)
; O0-NEXT: ldtilecfg {{[0-9]+}}(%rsp) ; O0-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
; O0-NEXT: tileloadd (%rcx,%rdx), %tmm0 ; O0-NEXT: tileloadd (%rcx,%rdx), %tmm0
; O0-NEXT: movl $32, %edx ; O0-NEXT: movl $32, %edx
; O0-NEXT: movl $buf+2048, %ecx ; O0-NEXT: movl $buf+2048, %ecx
; O0-NEXT: movw $8, %ax ; O0-NEXT: movw $8, %ax
; O0-NEXT: tilestored %tmm0, (%rcx,%rdx) ; O0-NEXT: tilestored %tmm0, (%rcx,%rdx)
Show All 30 Lines

llvm/test/CodeGen/X86/AMX/amx-configO0toO0.ll

Show First 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rcx ; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rcx
; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rax ; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rax
; AVX512-NEXT: movw %si, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movw %si, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movw %dx, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movw %dx, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movq %rcx, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movq %rcx, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movq %rax, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movq %rax, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movw {{[0-9]+}}(%rsp), %ax ; AVX512-NEXT: movw {{[0-9]+}}(%rsp), %ax
; AVX512-NEXT: movw {{[0-9]+}}(%rsp), %cx ; AVX512-NEXT: movw {{[0-9]+}}(%rsp), %cx
; AVX512-NEXT: # implicit-def: $al
; AVX512-NEXT: movb %al, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movb %al, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movw %cx, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movw %cx, {{[0-9]+}}(%rsp)
; AVX512-NEXT: ldtilecfg {{[0-9]+}}(%rsp) ; AVX512-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rdx ; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rdx
; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rsi ; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rsi
; AVX512-NEXT: tileloadd (%rdx,%rsi), %tmm0 ; AVX512-NEXT: tileloadd (%rdx,%rsi), %tmm0
; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rdx ; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rdx
; AVX512-NEXT: addq $64, %rdx ; AVX512-NEXT: addq $64, %rdx
Show All 11 Lines
; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rcx ; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rcx
; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rax ; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rax
; AVX512-NEXT: movw %si, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movw %si, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movw %dx, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movw %dx, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movq %rcx, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movq %rcx, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movq %rax, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movq %rax, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movw {{[0-9]+}}(%rsp), %ax ; AVX512-NEXT: movw {{[0-9]+}}(%rsp), %ax
; AVX512-NEXT: movw {{[0-9]+}}(%rsp), %cx ; AVX512-NEXT: movw {{[0-9]+}}(%rsp), %cx
; AVX512-NEXT: # implicit-def: $al
; AVX512-NEXT: movb %al, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movb %al, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movw %cx, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movw %cx, {{[0-9]+}}(%rsp)
; AVX512-NEXT: ldtilecfg {{[0-9]+}}(%rsp) ; AVX512-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rdx ; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rdx
; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rsi ; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rsi
; AVX512-NEXT: tileloadd (%rdx,%rsi), %tmm0 ; AVX512-NEXT: tileloadd (%rdx,%rsi), %tmm0
; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rdx ; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rdx
; AVX512-NEXT: addq $64, %rdx ; AVX512-NEXT: addq $64, %rdx
Show All 11 Lines
; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rcx ; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rcx
; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rax ; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rax
; AVX512-NEXT: movw %si, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movw %si, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movw %dx, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movw %dx, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movq %rcx, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movq %rcx, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movq %rax, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movq %rax, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movw {{[0-9]+}}(%rsp), %ax ; AVX512-NEXT: movw {{[0-9]+}}(%rsp), %ax
; AVX512-NEXT: movw {{[0-9]+}}(%rsp), %cx ; AVX512-NEXT: movw {{[0-9]+}}(%rsp), %cx
; AVX512-NEXT: # implicit-def: $al
; AVX512-NEXT: movb %al, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movb %al, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movw %cx, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movw %cx, {{[0-9]+}}(%rsp)
; AVX512-NEXT: ldtilecfg {{[0-9]+}}(%rsp) ; AVX512-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rdx ; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rdx
; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rsi ; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rsi
; AVX512-NEXT: tileloadd (%rdx,%rsi), %tmm0 ; AVX512-NEXT: tileloadd (%rdx,%rsi), %tmm0
; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rdx ; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rdx
; AVX512-NEXT: addq $64, %rdx ; AVX512-NEXT: addq $64, %rdx
Show All 13 Lines
; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rcx ; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rcx
; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rax ; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rax
; AVX512-NEXT: movw %si, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movw %si, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movw %dx, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movw %dx, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movq %rcx, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movq %rcx, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movq %rax, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movq %rax, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movw {{[0-9]+}}(%rsp), %ax ; AVX512-NEXT: movw {{[0-9]+}}(%rsp), %ax
; AVX512-NEXT: movw {{[0-9]+}}(%rsp), %cx ; AVX512-NEXT: movw {{[0-9]+}}(%rsp), %cx
; AVX512-NEXT: # implicit-def: $al
; AVX512-NEXT: movb %al, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movb %al, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movw %cx, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movw %cx, {{[0-9]+}}(%rsp)
; AVX512-NEXT: ldtilecfg {{[0-9]+}}(%rsp) ; AVX512-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rdx ; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rdx
; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rsi ; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rsi
; AVX512-NEXT: tileloadd (%rdx,%rsi), %tmm0 ; AVX512-NEXT: tileloadd (%rdx,%rsi), %tmm0
; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rdx ; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rdx
; AVX512-NEXT: addq $64, %rdx ; AVX512-NEXT: addq $64, %rdx
Show All 11 Lines
; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rcx ; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rcx
; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rax ; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rax
; AVX512-NEXT: movw %si, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movw %si, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movw %dx, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movw %dx, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movq %rcx, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movq %rcx, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movq %rax, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movq %rax, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movw {{[0-9]+}}(%rsp), %ax ; AVX512-NEXT: movw {{[0-9]+}}(%rsp), %ax
; AVX512-NEXT: movw {{[0-9]+}}(%rsp), %cx ; AVX512-NEXT: movw {{[0-9]+}}(%rsp), %cx
; AVX512-NEXT: # implicit-def: $al
; AVX512-NEXT: movb %al, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movb %al, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movw %cx, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movw %cx, {{[0-9]+}}(%rsp)
; AVX512-NEXT: ldtilecfg {{[0-9]+}}(%rsp) ; AVX512-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rdx ; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rdx
; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rsi ; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rsi
; AVX512-NEXT: tileloadd (%rdx,%rsi), %tmm0 ; AVX512-NEXT: tileloadd (%rdx,%rsi), %tmm0
; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rdx ; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rdx
; AVX512-NEXT: addq $64, %rdx ; AVX512-NEXT: addq $64, %rdx
Show All 11 Lines
; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rcx ; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rcx
; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rax ; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rax
; AVX512-NEXT: movw %si, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movw %si, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movw %dx, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movw %dx, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movq %rcx, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movq %rcx, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movq %rax, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movq %rax, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movw {{[0-9]+}}(%rsp), %ax ; AVX512-NEXT: movw {{[0-9]+}}(%rsp), %ax
; AVX512-NEXT: movw {{[0-9]+}}(%rsp), %cx ; AVX512-NEXT: movw {{[0-9]+}}(%rsp), %cx
; AVX512-NEXT: # implicit-def: $al
; AVX512-NEXT: movb %al, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movb %al, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movw %cx, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movw %cx, {{[0-9]+}}(%rsp)
; AVX512-NEXT: ldtilecfg {{[0-9]+}}(%rsp) ; AVX512-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rdx ; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rdx
; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rsi ; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rsi
; AVX512-NEXT: tileloadd (%rdx,%rsi), %tmm0 ; AVX512-NEXT: tileloadd (%rdx,%rsi), %tmm0
; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rdx ; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rdx
; AVX512-NEXT: addq $64, %rdx ; AVX512-NEXT: addq $64, %rdx
▲ Show 20 Lines • Show All 299 Lines • ▼ Show 20 Lines
; AVX512-NEXT: vmovdqa64 %zmm1, {{[0-9]+}}(%rsp) ; AVX512-NEXT: vmovdqa64 %zmm1, {{[0-9]+}}(%rsp)
; AVX512-NEXT: vmovdqa64 %zmm0, {{[0-9]+}}(%rsp) ; AVX512-NEXT: vmovdqa64 %zmm0, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movw {{[0-9]+}}(%rsp), %ax ; AVX512-NEXT: movw {{[0-9]+}}(%rsp), %ax
; AVX512-NEXT: movw {{[0-9]+}}(%rsp), %cx ; AVX512-NEXT: movw {{[0-9]+}}(%rsp), %cx
; AVX512-NEXT: movzwl {{[0-9]+}}(%rsp), %r8d ; AVX512-NEXT: movzwl {{[0-9]+}}(%rsp), %r8d
; AVX512-NEXT: movw %r8w, %di ; AVX512-NEXT: movw %r8w, %di
; AVX512-NEXT: shrl $2, %r8d ; AVX512-NEXT: shrl $2, %r8d
; AVX512-NEXT: movw %r8w, %r9w ; AVX512-NEXT: movw %r8w, %r9w
; AVX512-NEXT: # implicit-def: $al
; AVX512-NEXT: movb %al, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movb %al, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movw %cx, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movw %cx, {{[0-9]+}}(%rsp)
; AVX512-NEXT: # implicit-def: $r9b
; AVX512-NEXT: movb %r9b, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movb %r9b, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movw %cx, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movw %cx, {{[0-9]+}}(%rsp)
; AVX512-NEXT: # implicit-def: $al
; AVX512-NEXT: movb %al, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movb %al, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movw %di, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movw %di, {{[0-9]+}}(%rsp)
; AVX512-NEXT: # implicit-def: $al
; AVX512-NEXT: movb %al, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movb %al, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movw %cx, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movw %cx, {{[0-9]+}}(%rsp)
; AVX512-NEXT: ldtilecfg {{[0-9]+}}(%rsp) ; AVX512-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
; AVX512-NEXT: movl $64, %r8d ; AVX512-NEXT: movl $64, %r8d
; AVX512-NEXT: leaq {{[0-9]+}}(%rsp), %r10 ; AVX512-NEXT: leaq {{[0-9]+}}(%rsp), %r10
; AVX512-NEXT: tileloadd (%r10,%r8), %tmm0 ; AVX512-NEXT: tileloadd (%r10,%r8), %tmm0
; AVX512-NEXT: leaq {{[0-9]+}}(%rsp), %r10 ; AVX512-NEXT: leaq {{[0-9]+}}(%rsp), %r10
; AVX512-NEXT: tileloadd (%r10,%r8), %tmm1 ; AVX512-NEXT: tileloadd (%r10,%r8), %tmm1
▲ Show 20 Lines • Show All 91 Lines • ▼ Show 20 Lines
; AVX512-NEXT: vmovdqa64 %zmm5, {{[0-9]+}}(%rsp) ; AVX512-NEXT: vmovdqa64 %zmm5, {{[0-9]+}}(%rsp)
; AVX512-NEXT: vmovdqa64 %zmm4, {{[0-9]+}}(%rsp) ; AVX512-NEXT: vmovdqa64 %zmm4, {{[0-9]+}}(%rsp)
; AVX512-NEXT: vmovdqa64 %zmm3, {{[0-9]+}}(%rsp) ; AVX512-NEXT: vmovdqa64 %zmm3, {{[0-9]+}}(%rsp)
; AVX512-NEXT: vmovdqa64 %zmm2, {{[0-9]+}}(%rsp) ; AVX512-NEXT: vmovdqa64 %zmm2, {{[0-9]+}}(%rsp)
; AVX512-NEXT: vmovdqa64 %zmm1, {{[0-9]+}}(%rsp) ; AVX512-NEXT: vmovdqa64 %zmm1, {{[0-9]+}}(%rsp)
; AVX512-NEXT: vmovdqa64 %zmm0, {{[0-9]+}}(%rsp) ; AVX512-NEXT: vmovdqa64 %zmm0, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movw {{[0-9]+}}(%rsp), %ax ; AVX512-NEXT: movw {{[0-9]+}}(%rsp), %ax
; AVX512-NEXT: movw {{[0-9]+}}(%rsp), %cx ; AVX512-NEXT: movw {{[0-9]+}}(%rsp), %cx
; AVX512-NEXT: # implicit-def: $al
; AVX512-NEXT: movb %al, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movb %al, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movw %cx, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movw %cx, {{[0-9]+}}(%rsp)
; AVX512-NEXT: ldtilecfg {{[0-9]+}}(%rsp) ; AVX512-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rdx ; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rdx
; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rsi ; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rsi
; AVX512-NEXT: leaq {{[0-9]+}}(%rsp), %rdi ; AVX512-NEXT: leaq {{[0-9]+}}(%rsp), %rdi
; AVX512-NEXT: movl $64, %r8d ; AVX512-NEXT: movl $64, %r8d
; AVX512-NEXT: tileloadd (%rdi,%r8), %tmm0 ; AVX512-NEXT: tileloadd (%rdi,%r8), %tmm0
▲ Show 20 Lines • Show All 358 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/AMX/amx-configO2toO0.ll

Show All 31 Lines
; AVX512-NEXT: movw {{[-0-9]+}}(%r{{[sb]}}p), %ax # 2-byte Reload ; AVX512-NEXT: movw {{[-0-9]+}}(%r{{[sb]}}p), %ax # 2-byte Reload
; AVX512-NEXT: movw {{[-0-9]+}}(%r{{[sb]}}p), %cx # 2-byte Reload ; AVX512-NEXT: movw {{[-0-9]+}}(%r{{[sb]}}p), %cx # 2-byte Reload
; AVX512-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload ; AVX512-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload
; AVX512-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdi # 8-byte Reload ; AVX512-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdi # 8-byte Reload
; AVX512-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r8 # 8-byte Reload ; AVX512-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r8 # 8-byte Reload
; AVX512-NEXT: movl $buf, %r9d ; AVX512-NEXT: movl $buf, %r9d
; AVX512-NEXT: movl $32, %r10d ; AVX512-NEXT: movl $32, %r10d
; AVX512-NEXT: movw $8, %si ; AVX512-NEXT: movw $8, %si
; AVX512-NEXT: # implicit-def: $al
; AVX512-NEXT: movb %al, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movb %al, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movw %si, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movw %si, {{[0-9]+}}(%rsp)
; AVX512-NEXT: ldtilecfg {{[0-9]+}}(%rsp) ; AVX512-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
; AVX512-NEXT: tileloadd (%r9,%r10), %tmm0 ; AVX512-NEXT: tileloadd (%r9,%r10), %tmm0
; AVX512-NEXT: movl $64, %r9d ; AVX512-NEXT: movl $64, %r9d
; AVX512-NEXT: movw $8, %si ; AVX512-NEXT: movw $8, %si
; AVX512-NEXT: tilestored %tmm0, (%r8,%r9) ; AVX512-NEXT: tilestored %tmm0, (%r8,%r9)
; AVX512-NEXT: movl $buf, %r8d ; AVX512-NEXT: movl $buf, %r8d
; AVX512-NEXT: movl $32, %r9d ; AVX512-NEXT: movl $32, %r9d
; AVX512-NEXT: movw $8, %si ; AVX512-NEXT: movw $8, %si
; AVX512-NEXT: # implicit-def: $al
; AVX512-NEXT: movb %al, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movb %al, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movw %cx, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movw %cx, {{[0-9]+}}(%rsp)
; AVX512-NEXT: # implicit-def: $sil
; AVX512-NEXT: movb %sil, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movb %sil, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movw %cx, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movw %cx, {{[0-9]+}}(%rsp)
; AVX512-NEXT: ldtilecfg {{[0-9]+}}(%rsp) ; AVX512-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
; AVX512-NEXT: tileloadd (%r8,%r9), %tmm0 ; AVX512-NEXT: tileloadd (%r8,%r9), %tmm0
; AVX512-NEXT: movl $64, %r8d ; AVX512-NEXT: movl $64, %r8d
; AVX512-NEXT: movw $8, %si ; AVX512-NEXT: movw $8, %si
; AVX512-NEXT: tilestored %tmm0, (%rdi,%r8) ; AVX512-NEXT: tilestored %tmm0, (%rdi,%r8)
; AVX512-NEXT: movl $buf, %esi ; AVX512-NEXT: movl $buf, %esi
; AVX512-NEXT: movl $32, %edi ; AVX512-NEXT: movl $32, %edi
; AVX512-NEXT: tileloadd (%rsi,%rdi), %tmm0 ; AVX512-NEXT: tileloadd (%rsi,%rdi), %tmm0
; AVX512-NEXT: movl $64, %esi ; AVX512-NEXT: movl $64, %esi
; AVX512-NEXT: tilestored %tmm0, (%rdx,%rsi) ; AVX512-NEXT: tilestored %tmm0, (%rdx,%rsi)
; AVX512-NEXT: jmp .LBB0_3 ; AVX512-NEXT: jmp .LBB0_3
; AVX512-NEXT: .LBB0_2: # %if.else ; AVX512-NEXT: .LBB0_2: # %if.else
; AVX512-NEXT: movw {{[-0-9]+}}(%r{{[sb]}}p), %ax # 2-byte Reload ; AVX512-NEXT: movw {{[-0-9]+}}(%r{{[sb]}}p), %ax # 2-byte Reload
; AVX512-NEXT: movw {{[-0-9]+}}(%r{{[sb]}}p), %cx # 2-byte Reload ; AVX512-NEXT: movw {{[-0-9]+}}(%r{{[sb]}}p), %cx # 2-byte Reload
; AVX512-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload ; AVX512-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload
; AVX512-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdi # 8-byte Reload ; AVX512-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdi # 8-byte Reload
; AVX512-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r8 # 8-byte Reload ; AVX512-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r8 # 8-byte Reload
; AVX512-NEXT: movl $buf2, %r9d ; AVX512-NEXT: movl $buf2, %r9d
; AVX512-NEXT: movl $32, %r10d ; AVX512-NEXT: movl $32, %r10d
; AVX512-NEXT: movw $8, %si ; AVX512-NEXT: movw $8, %si
; AVX512-NEXT: # implicit-def: $al
; AVX512-NEXT: movb %al, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movb %al, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movw %si, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movw %si, {{[0-9]+}}(%rsp)
; AVX512-NEXT: ldtilecfg {{[0-9]+}}(%rsp) ; AVX512-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
; AVX512-NEXT: tileloadd (%r9,%r10), %tmm0 ; AVX512-NEXT: tileloadd (%r9,%r10), %tmm0
; AVX512-NEXT: movl $64, %r9d ; AVX512-NEXT: movl $64, %r9d
; AVX512-NEXT: movw $8, %si ; AVX512-NEXT: movw $8, %si
; AVX512-NEXT: tilestored %tmm0, (%r8,%r9) ; AVX512-NEXT: tilestored %tmm0, (%r8,%r9)
; AVX512-NEXT: movl $buf2, %r8d ; AVX512-NEXT: movl $buf2, %r8d
; AVX512-NEXT: movl $32, %r9d ; AVX512-NEXT: movl $32, %r9d
; AVX512-NEXT: movw $8, %si ; AVX512-NEXT: movw $8, %si
; AVX512-NEXT: # implicit-def: $al
; AVX512-NEXT: movb %al, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movb %al, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movw %cx, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movw %cx, {{[0-9]+}}(%rsp)
; AVX512-NEXT: # implicit-def: $sil
; AVX512-NEXT: movb %sil, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movb %sil, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movw %cx, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movw %cx, {{[0-9]+}}(%rsp)
; AVX512-NEXT: ldtilecfg {{[0-9]+}}(%rsp) ; AVX512-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
; AVX512-NEXT: tileloadd (%r8,%r9), %tmm0 ; AVX512-NEXT: tileloadd (%r8,%r9), %tmm0
; AVX512-NEXT: movl $64, %r8d ; AVX512-NEXT: movl $64, %r8d
; AVX512-NEXT: movw $8, %si ; AVX512-NEXT: movw $8, %si
; AVX512-NEXT: tilestored %tmm0, (%rdi,%r8) ; AVX512-NEXT: tilestored %tmm0, (%rdi,%r8)
; AVX512-NEXT: movl $buf2, %esi ; AVX512-NEXT: movl $buf2, %esi
; AVX512-NEXT: movl $32, %edi ; AVX512-NEXT: movl $32, %edi
; AVX512-NEXT: tileloadd (%rsi,%rdi), %tmm0 ; AVX512-NEXT: tileloadd (%rsi,%rdi), %tmm0
; AVX512-NEXT: movl $64, %esi ; AVX512-NEXT: movl $64, %esi
; AVX512-NEXT: tilestored %tmm0, (%rdx,%rsi) ; AVX512-NEXT: tilestored %tmm0, (%rdx,%rsi)
; AVX512-NEXT: .LBB0_3: # %if.end ; AVX512-NEXT: .LBB0_3: # %if.end
; AVX512-NEXT: movw {{[-0-9]+}}(%r{{[sb]}}p), %ax # 2-byte Reload ; AVX512-NEXT: movw {{[-0-9]+}}(%r{{[sb]}}p), %ax # 2-byte Reload
; AVX512-NEXT: movw {{[-0-9]+}}(%r{{[sb]}}p), %cx # 2-byte Reload ; AVX512-NEXT: movw {{[-0-9]+}}(%r{{[sb]}}p), %cx # 2-byte Reload
; AVX512-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload ; AVX512-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload
; AVX512-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rsi # 8-byte Reload ; AVX512-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rsi # 8-byte Reload
; AVX512-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r9 # 8-byte Reload ; AVX512-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r9 # 8-byte Reload
; AVX512-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r8 # 8-byte Reload ; AVX512-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r8 # 8-byte Reload
; AVX512-NEXT: movl $64, %r10d ; AVX512-NEXT: movl $64, %r10d
; AVX512-NEXT: movw $8, %di ; AVX512-NEXT: movw $8, %di
; AVX512-NEXT: # implicit-def: $al
; AVX512-NEXT: movb %al, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movb %al, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movw %di, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movw %di, {{[0-9]+}}(%rsp)
; AVX512-NEXT: ldtilecfg {{[0-9]+}}(%rsp) ; AVX512-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
; AVX512-NEXT: tileloadd (%r8,%r10), %tmm0 ; AVX512-NEXT: tileloadd (%r8,%r10), %tmm0
; AVX512-NEXT: movabsq $64, %r8 ; AVX512-NEXT: movabsq $64, %r8
; AVX512-NEXT: tilestored %tmm0, 1024(%rsp,%r8) # 1024-byte Folded Spill ; AVX512-NEXT: tilestored %tmm0, 1024(%rsp,%r8) # 1024-byte Folded Spill
; AVX512-NEXT: movl $64, %r10d ; AVX512-NEXT: movl $64, %r10d
; AVX512-NEXT: movw $8, %r8w ; AVX512-NEXT: movw $8, %r8w
; AVX512-NEXT: # implicit-def: $al
; AVX512-NEXT: movb %al, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movb %al, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movw %cx, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movw %cx, {{[0-9]+}}(%rsp)
; AVX512-NEXT: # implicit-def: $al
; AVX512-NEXT: movb %al, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movb %al, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movw %cx, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movw %cx, {{[0-9]+}}(%rsp)
; AVX512-NEXT: # implicit-def: $al
; AVX512-NEXT: movb %al, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movb %al, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movw %di, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movw %di, {{[0-9]+}}(%rsp)
; AVX512-NEXT: # implicit-def: $al
; AVX512-NEXT: movb %al, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movb %al, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movw %cx, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movw %cx, {{[0-9]+}}(%rsp)
; AVX512-NEXT: # implicit-def: $r8b
; AVX512-NEXT: movb %r8b, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movb %r8b, {{[0-9]+}}(%rsp)
; AVX512-NEXT: movw %cx, {{[0-9]+}}(%rsp) ; AVX512-NEXT: movw %cx, {{[0-9]+}}(%rsp)
; AVX512-NEXT: ldtilecfg {{[0-9]+}}(%rsp) ; AVX512-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
; AVX512-NEXT: tileloadd (%r9,%r10), %tmm2 ; AVX512-NEXT: tileloadd (%r9,%r10), %tmm2
; AVX512-NEXT: movl $64, %r8d ; AVX512-NEXT: movl $64, %r8d
; AVX512-NEXT: tileloadd (%rsi,%r8), %tmm0 ; AVX512-NEXT: tileloadd (%rsi,%r8), %tmm0
; AVX512-NEXT: movw $8, %si ; AVX512-NEXT: movw $8, %si
; AVX512-NEXT: movabsq $64, %r8 ; AVX512-NEXT: movabsq $64, %r8
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llvm/test/CodeGen/X86/AMX/amx-zero-config.ll

Show First 20 Lines • Show All 67 Lines • ▼ Show 20 Lines
; AVX512-O0-NEXT: andq $-1024, %rsp # imm = 0xFC00 ; AVX512-O0-NEXT: andq $-1024, %rsp # imm = 0xFC00
; AVX512-O0-NEXT: subq $3072, %rsp # imm = 0xC00 ; AVX512-O0-NEXT: subq $3072, %rsp # imm = 0xC00
; AVX512-O0-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX512-O0-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX512-O0-NEXT: vmovups %zmm0, {{[0-9]+}}(%rsp) ; AVX512-O0-NEXT: vmovups %zmm0, {{[0-9]+}}(%rsp)
; AVX512-O0-NEXT: movb $1, {{[0-9]+}}(%rsp) ; AVX512-O0-NEXT: movb $1, {{[0-9]+}}(%rsp)
; AVX512-O0-NEXT: leaq {{[0-9]+}}(%rsp), %rdx ; AVX512-O0-NEXT: leaq {{[0-9]+}}(%rsp), %rdx
; AVX512-O0-NEXT: movw $32, %cx ; AVX512-O0-NEXT: movw $32, %cx
; AVX512-O0-NEXT: movw $8, %ax ; AVX512-O0-NEXT: movw $8, %ax
; AVX512-O0-NEXT: # implicit-def: $al
; AVX512-O0-NEXT: movb %al, {{[0-9]+}}(%rsp) ; AVX512-O0-NEXT: movb %al, {{[0-9]+}}(%rsp)
; AVX512-O0-NEXT: movw %cx, {{[0-9]+}}(%rsp) ; AVX512-O0-NEXT: movw %cx, {{[0-9]+}}(%rsp)
; AVX512-O0-NEXT: ldtilecfg {{[0-9]+}}(%rsp) ; AVX512-O0-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
; AVX512-O0-NEXT: tilezero %tmm0 ; AVX512-O0-NEXT: tilezero %tmm0
; AVX512-O0-NEXT: movl $64, %esi ; AVX512-O0-NEXT: movl $64, %esi
; AVX512-O0-NEXT: movw $32, %cx ; AVX512-O0-NEXT: movw $32, %cx
; AVX512-O0-NEXT: movw $8, %ax ; AVX512-O0-NEXT: movw $8, %ax
; AVX512-O0-NEXT: tilestored %tmm0, (%rdx,%rsi) ; AVX512-O0-NEXT: tilestored %tmm0, (%rdx,%rsi)
; AVX512-O0-NEXT: movl $64, %esi ; AVX512-O0-NEXT: movl $64, %esi
; AVX512-O0-NEXT: movw $32, %cx ; AVX512-O0-NEXT: movw $32, %cx
; AVX512-O0-NEXT: movw $8, %ax ; AVX512-O0-NEXT: movw $8, %ax
; AVX512-O0-NEXT: # implicit-def: $al
; AVX512-O0-NEXT: movb %al, {{[0-9]+}}(%rsp) ; AVX512-O0-NEXT: movb %al, {{[0-9]+}}(%rsp)
; AVX512-O0-NEXT: movw %cx, {{[0-9]+}}(%rsp) ; AVX512-O0-NEXT: movw %cx, {{[0-9]+}}(%rsp)
; AVX512-O0-NEXT: ldtilecfg {{[0-9]+}}(%rsp) ; AVX512-O0-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
; AVX512-O0-NEXT: tileloadd (%rdx,%rsi), %tmm0 ; AVX512-O0-NEXT: tileloadd (%rdx,%rsi), %tmm0
; AVX512-O0-NEXT: movl $1024, %edx # imm = 0x400 ; AVX512-O0-NEXT: movl $1024, %edx # imm = 0x400
; AVX512-O0-NEXT: movw $32, %cx ; AVX512-O0-NEXT: movw $32, %cx
; AVX512-O0-NEXT: movw $8, %ax ; AVX512-O0-NEXT: movw $8, %ax
; AVX512-O0-NEXT: tilestored %tmm0, (%rdi,%rdx) ; AVX512-O0-NEXT: tilestored %tmm0, (%rdi,%rdx)
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; AVX2-O0-NEXT: subq $3072, %rsp # imm = 0xC00 ; AVX2-O0-NEXT: subq $3072, %rsp # imm = 0xC00
; AVX2-O0-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX2-O0-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX2-O0-NEXT: vmovups %ymm0, {{[0-9]+}}(%rsp) ; AVX2-O0-NEXT: vmovups %ymm0, {{[0-9]+}}(%rsp)
; AVX2-O0-NEXT: vmovups %ymm0, {{[0-9]+}}(%rsp) ; AVX2-O0-NEXT: vmovups %ymm0, {{[0-9]+}}(%rsp)
; AVX2-O0-NEXT: movb $1, {{[0-9]+}}(%rsp) ; AVX2-O0-NEXT: movb $1, {{[0-9]+}}(%rsp)
; AVX2-O0-NEXT: leaq {{[0-9]+}}(%rsp), %rdx ; AVX2-O0-NEXT: leaq {{[0-9]+}}(%rsp), %rdx
; AVX2-O0-NEXT: movw $32, %cx ; AVX2-O0-NEXT: movw $32, %cx
; AVX2-O0-NEXT: movw $8, %ax ; AVX2-O0-NEXT: movw $8, %ax
; AVX2-O0-NEXT: # implicit-def: $al
; AVX2-O0-NEXT: movb %al, {{[0-9]+}}(%rsp) ; AVX2-O0-NEXT: movb %al, {{[0-9]+}}(%rsp)
; AVX2-O0-NEXT: movw %cx, {{[0-9]+}}(%rsp) ; AVX2-O0-NEXT: movw %cx, {{[0-9]+}}(%rsp)
; AVX2-O0-NEXT: ldtilecfg {{[0-9]+}}(%rsp) ; AVX2-O0-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
; AVX2-O0-NEXT: tilezero %tmm0 ; AVX2-O0-NEXT: tilezero %tmm0
; AVX2-O0-NEXT: movl $64, %esi ; AVX2-O0-NEXT: movl $64, %esi
; AVX2-O0-NEXT: movw $32, %cx ; AVX2-O0-NEXT: movw $32, %cx
; AVX2-O0-NEXT: movw $8, %ax ; AVX2-O0-NEXT: movw $8, %ax
; AVX2-O0-NEXT: tilestored %tmm0, (%rdx,%rsi) ; AVX2-O0-NEXT: tilestored %tmm0, (%rdx,%rsi)
; AVX2-O0-NEXT: movl $64, %esi ; AVX2-O0-NEXT: movl $64, %esi
; AVX2-O0-NEXT: movw $32, %cx ; AVX2-O0-NEXT: movw $32, %cx
; AVX2-O0-NEXT: movw $8, %ax ; AVX2-O0-NEXT: movw $8, %ax
; AVX2-O0-NEXT: # implicit-def: $al
; AVX2-O0-NEXT: movb %al, {{[0-9]+}}(%rsp) ; AVX2-O0-NEXT: movb %al, {{[0-9]+}}(%rsp)
; AVX2-O0-NEXT: movw %cx, {{[0-9]+}}(%rsp) ; AVX2-O0-NEXT: movw %cx, {{[0-9]+}}(%rsp)
; AVX2-O0-NEXT: ldtilecfg {{[0-9]+}}(%rsp) ; AVX2-O0-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
; AVX2-O0-NEXT: tileloadd (%rdx,%rsi), %tmm0 ; AVX2-O0-NEXT: tileloadd (%rdx,%rsi), %tmm0
; AVX2-O0-NEXT: movl $1024, %edx # imm = 0x400 ; AVX2-O0-NEXT: movl $1024, %edx # imm = 0x400
; AVX2-O0-NEXT: movw $32, %cx ; AVX2-O0-NEXT: movw $32, %cx
; AVX2-O0-NEXT: movw $8, %ax ; AVX2-O0-NEXT: movw $8, %ax
; AVX2-O0-NEXT: tilestored %tmm0, (%rdi,%rdx) ; AVX2-O0-NEXT: tilestored %tmm0, (%rdi,%rdx)
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; SSE2-O0-NEXT: movups %xmm0, {{[0-9]+}}(%rsp) ; SSE2-O0-NEXT: movups %xmm0, {{[0-9]+}}(%rsp)
; SSE2-O0-NEXT: movups %xmm0, {{[0-9]+}}(%rsp) ; SSE2-O0-NEXT: movups %xmm0, {{[0-9]+}}(%rsp)
; SSE2-O0-NEXT: movups %xmm0, {{[0-9]+}}(%rsp) ; SSE2-O0-NEXT: movups %xmm0, {{[0-9]+}}(%rsp)
; SSE2-O0-NEXT: movups %xmm0, {{[0-9]+}}(%rsp) ; SSE2-O0-NEXT: movups %xmm0, {{[0-9]+}}(%rsp)
; SSE2-O0-NEXT: movb $1, {{[0-9]+}}(%rsp) ; SSE2-O0-NEXT: movb $1, {{[0-9]+}}(%rsp)
; SSE2-O0-NEXT: leaq {{[0-9]+}}(%rsp), %rdx ; SSE2-O0-NEXT: leaq {{[0-9]+}}(%rsp), %rdx
; SSE2-O0-NEXT: movw $32, %cx ; SSE2-O0-NEXT: movw $32, %cx
; SSE2-O0-NEXT: movw $8, %ax ; SSE2-O0-NEXT: movw $8, %ax
; SSE2-O0-NEXT: # implicit-def: $al
; SSE2-O0-NEXT: movb %al, {{[0-9]+}}(%rsp) ; SSE2-O0-NEXT: movb %al, {{[0-9]+}}(%rsp)
; SSE2-O0-NEXT: movw %cx, {{[0-9]+}}(%rsp) ; SSE2-O0-NEXT: movw %cx, {{[0-9]+}}(%rsp)
; SSE2-O0-NEXT: ldtilecfg {{[0-9]+}}(%rsp) ; SSE2-O0-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
; SSE2-O0-NEXT: tilezero %tmm0 ; SSE2-O0-NEXT: tilezero %tmm0
; SSE2-O0-NEXT: movl $64, %esi ; SSE2-O0-NEXT: movl $64, %esi
; SSE2-O0-NEXT: movw $32, %cx ; SSE2-O0-NEXT: movw $32, %cx
; SSE2-O0-NEXT: movw $8, %ax ; SSE2-O0-NEXT: movw $8, %ax
; SSE2-O0-NEXT: tilestored %tmm0, (%rdx,%rsi) ; SSE2-O0-NEXT: tilestored %tmm0, (%rdx,%rsi)
; SSE2-O0-NEXT: movl $64, %esi ; SSE2-O0-NEXT: movl $64, %esi
; SSE2-O0-NEXT: movw $32, %cx ; SSE2-O0-NEXT: movw $32, %cx
; SSE2-O0-NEXT: movw $8, %ax ; SSE2-O0-NEXT: movw $8, %ax
; SSE2-O0-NEXT: # implicit-def: $al
; SSE2-O0-NEXT: movb %al, {{[0-9]+}}(%rsp) ; SSE2-O0-NEXT: movb %al, {{[0-9]+}}(%rsp)
; SSE2-O0-NEXT: movw %cx, {{[0-9]+}}(%rsp) ; SSE2-O0-NEXT: movw %cx, {{[0-9]+}}(%rsp)
; SSE2-O0-NEXT: ldtilecfg {{[0-9]+}}(%rsp) ; SSE2-O0-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
; SSE2-O0-NEXT: tileloadd (%rdx,%rsi), %tmm0 ; SSE2-O0-NEXT: tileloadd (%rdx,%rsi), %tmm0
; SSE2-O0-NEXT: movl $1024, %edx # imm = 0x400 ; SSE2-O0-NEXT: movl $1024, %edx # imm = 0x400
; SSE2-O0-NEXT: movw $32, %cx ; SSE2-O0-NEXT: movw $32, %cx
; SSE2-O0-NEXT: movw $8, %ax ; SSE2-O0-NEXT: movw $8, %ax
; SSE2-O0-NEXT: tilestored %tmm0, (%rdi,%rdx) ; SSE2-O0-NEXT: tilestored %tmm0, (%rdi,%rdx)
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llvm/test/CodeGen/X86/O0-pipeline.ll

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; CHECK-NEXT: X86 speculative load hardening ; CHECK-NEXT: X86 speculative load hardening
; CHECK-NEXT: MachineDominator Tree Construction ; CHECK-NEXT: MachineDominator Tree Construction
; CHECK-NEXT: X86 EFLAGS copy lowering ; CHECK-NEXT: X86 EFLAGS copy lowering
; CHECK-NEXT: X86 DynAlloca Expander ; CHECK-NEXT: X86 DynAlloca Expander
; CHECK-NEXT: Fast Tile Register Preconfigure ; CHECK-NEXT: Fast Tile Register Preconfigure
; CHECK-NEXT: Eliminate PHI nodes for register allocation ; CHECK-NEXT: Eliminate PHI nodes for register allocation
; CHECK-NEXT: Two-Address instruction pass ; CHECK-NEXT: Two-Address instruction pass
; CHECK-NEXT: Fast Register Allocator ; CHECK-NEXT: Fast Register Allocator
; CHECK-NEXT: Fast Register Allocator
; CHECK-NEXT: Fast Tile Register Configure ; CHECK-NEXT: Fast Tile Register Configure
; CHECK-NEXT: Fast Register Allocator
; CHECK-NEXT: X86 Lower Tile Copy ; CHECK-NEXT: X86 Lower Tile Copy
; CHECK-NEXT: Bundle Machine CFG Edges ; CHECK-NEXT: Bundle Machine CFG Edges
; CHECK-NEXT: X86 FP Stackifier ; CHECK-NEXT: X86 FP Stackifier
; CHECK-NEXT: Remove Redundant DEBUG_VALUE analysis ; CHECK-NEXT: Remove Redundant DEBUG_VALUE analysis
; CHECK-NEXT: Fixup Statepoint Caller Saved ; CHECK-NEXT: Fixup Statepoint Caller Saved
; CHECK-NEXT: Lazy Machine Block Frequency Analysis ; CHECK-NEXT: Lazy Machine Block Frequency Analysis
; CHECK-NEXT: Machine Optimization Remark Emitter ; CHECK-NEXT: Machine Optimization Remark Emitter
; CHECK-NEXT: Prologue/Epilogue Insertion & Frame Finalization ; CHECK-NEXT: Prologue/Epilogue Insertion & Frame Finalization
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