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Differential D127946

[RISCV][NFC][test] Correct a wrong test in vreductions-fp-vp.ll
ClosedPublic

Authored by Jimerlife on Jun 16 2022, 1:14 AM.

Details

Reviewers
craig.topper
victor-eds
frasercrmck
benshi001
Commits
rG5e16a781bada: [RISCV][NFC][test] Correct a wrong test in vreductions-fp-vp.ll
Summary

This D117467 patch add a wrong test to test reduce.fadd widen.

Diff Detail

Event Timeline

Jimerlife created this revision.Jun 16 2022, 1:14 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 16 2022, 1:14 AM
Herald added subscribers: sunshaoce, VincentWu, luke957 and 28 others. · View Herald Transcript
Jimerlife requested review of this revision.Jun 16 2022, 1:14 AM
Herald added subscribers: llvm-commits, • pcwang-thead, eopXD and 2 others. · View Herald TranscriptJun 16 2022, 1:14 AM
frasercrmck accepted this revision.Jun 16 2022, 1:46 AM

Good catch, thanks.

This revision is now accepted and ready to land.Jun 16 2022, 1:46 AM
victor-eds accepted this revision.Jun 16 2022, 1:50 AM

LGTM. Totally missed that. Thanks.

Harbormaster completed remote builds in B170205: Diff 437465.Jun 16 2022, 2:03 AM
This revision was landed with ongoing or failed builds.Jun 16 2022, 7:24 PM
Closed by commit rG5e16a781bada: [RISCV][NFC][test] Correct a wrong test in vreductions-fp-vp.ll (authored by Jimerlife). · Explain Why
This revision was automatically updated to reflect the committed changes.
Jimerlife added a commit: rG5e16a781bada: [RISCV][NFC][test] Correct a wrong test in vreductions-fp-vp.ll.

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
rvv/
5 lines

Diff 437465

llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll

Show First 20 Lines • Show All 309 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: vfredusum.vs v12, v8, v12, v0.t ; CHECK-NEXT: vfredusum.vs v12, v8, v12, v0.t
; CHECK-NEXT: vfmv.f.s fa0, v12 ; CHECK-NEXT: vfmv.f.s fa0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call reassoc double @llvm.vp.reduce.fadd.nxv3f64(double %s, <vscale x 3 x double> %v, <vscale x 3 x i1> %m, i32 %evl) %r = call reassoc double @llvm.vp.reduce.fadd.nxv3f64(double %s, <vscale x 3 x double> %v, <vscale x 3 x i1> %m, i32 %evl)
ret double %r ret double %r
} }
define double @vpreduce_ord_fadd_nxv3f64(double %s, <vscale x 4 x double> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) { define double @vpreduce_ord_fadd_nxv3f64(double %s, <vscale x 3 x double> %v, <vscale x 3 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_ord_fadd_nxv3f64: ; CHECK-LABEL: vpreduce_ord_fadd_nxv3f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v12, fa0 ; CHECK-NEXT: vfmv.s.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: vfredosum.vs v12, v8, v12, v0.t ; CHECK-NEXT: vfredosum.vs v12, v8, v12, v0.t
; CHECK-NEXT: vfmv.f.s fa0, v12 ; CHECK-NEXT: vfmv.f.s fa0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call double @llvm.vp.reduce.fadd.nxv4f64(double %s, <vscale x 4 x double> %v, <vscale x 4 x i1> %m, i32 %evl) %r = call double @llvm.vp.reduce.fadd.nxv3f64(double %s, <vscale x 3 x double> %v, <vscale x 3 x i1> %m, i32 %evl)
ret double %r ret double %r
} }
declare double @llvm.vp.reduce.fadd.nxv4f64(double, <vscale x 4 x double>, <vscale x 4 x i1>, i32) declare double @llvm.vp.reduce.fadd.nxv4f64(double, <vscale x 4 x double>, <vscale x 4 x i1>, i32)
define double @vpreduce_fadd_nxv4f64(double %s, <vscale x 4 x double> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) { define double @vpreduce_fadd_nxv4f64(double %s, <vscale x 4 x double> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_fadd_nxv4f64: ; CHECK-LABEL: vpreduce_fadd_nxv4f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v12, fa0 ; CHECK-NEXT: vfmv.s.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
Show All 19 Lines