[LegalizeTypes][RISCV][NFC] Modify assert in PromoteIntRes_STEP_VECTOR and add some tests for RISCV

[Jimerlife]

Summary

1. Modify assert in PromoteIntRes_STEP_VECTOR.
2. Add promote step_vector test for RISCV.

[craig.topper]

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

5280

Why this change? llvm.stepvector intrinsic works for fixed vectors.

llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll

318

The rest of this patch involve stepvector, but this doesn't. Unless I'm missing something this should be a different patch.

[Jimerlife]

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

5280

Yes, llvm.stepvector intrinsic works for fixed vectors, but ISD::STEP_VECTOR is only work for scalable vector. I'm not sure my understanding is right?

[Jimerlife]

llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll

318

Removed this change.

[david-arm]

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

5280

I agree with @craig.topper. I don't understand why we're changing the assert here. This should work for fixed vectors too so we should be asserting that the result is a vector, i.e. either fixed-width or scalable.

[Jimerlife]

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

5280

If call <vscale x 4 x i15> @llvm.experimental.stepvector.nxv4i15(), it generated nxv4i15 = step_vector node.
But if call <4 x i15> @llvm.experimental.stepvector.v4i15(), it generated v4i15 = build_vector node.

My understand is that fixed vectors cann't generate node like v4i15 = step_vector.
So, only scalable vector will go through PromoteIntRes_STEP_VECTOR if it need to promote.
This is right? @craig.topper @david-arm

[frasercrmck]

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

5280

That's my understanding, yes - we don't generate ISD::STEP_VECTOR for fixed-length vector types. Take a look at SelectionDAG::getStepVector's implementation. I assume that's done for canonicalization purposes.

[david-arm]

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

5280

My apologies @Jimerlife, you are absolutely right! I was thinking about the SelectionDAG::getStepVector interface, but this only returns STEP_VECTOR for scalable vectors. In fact, the ISD node states:

/// STEP_VECTOR(IMM) - Returns a scalable vector whose lanes are comprised
/// of a linear sequence of unsigned values starting from 0 with a step of
/// IMM, where IMM must be a TargetConstant with type equal to the vector
/// element type. The arithmetic is performed modulo the bitwidth of the
/// element.
///
/// The operation does not support returning fixed-width vectors or
/// non-constant operands.
STEP_VECTOR,

[david-arm]

LGTM!

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

SDValue DAGTypeLegalizer::PromoteIntRes_SPLAT_VECTOR(SDNode *N) {
 
   return DAG.getNode(ISD::SPLAT_VECTOR, dl, NOutVT, Op);
 }
 
 SDValue DAGTypeLegalizer::PromoteIntRes_STEP_VECTOR(SDNode *N) {
   SDLoc dl(N);
   EVT OutVT = N->getValueType(0);
   EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
-  assert(NOutVT.isVector() && "Type must be promoted to a vector type");
+  assert(NOutVT.isScalableVector() &&
+         "Type must be promoted to a scalable vector type");
   APInt StepVal = cast<ConstantSDNode>(N->getOperand(0))->getAPIntValue();
   return DAG.getStepVector(dl, NOutVT,
                            StepVal.sext(NOutVT.getScalarSizeInBits()));
 }
 
 SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(SDNode *N) {
   SDLoc dl(N);
 

llvm/test/CodeGen/RISCV/rvv/stepvector.ll

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
 ; CHECK-NEXT:    vid.v v8
 ; CHECK-NEXT:    ret
   %v = call <vscale x 2 x i16> @llvm.experimental.stepvector.nxv2i16()
   ret <vscale x 2 x i16> %v
 }
 
+declare <vscale x 2 x i15> @llvm.experimental.stepvector.nxv2i15()
+
+define <vscale x 2 x i15> @stepvector_nxv2i15() {
+; CHECK-LABEL: stepvector_nxv2i15:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
+; CHECK-NEXT:    vid.v v8
+; CHECK-NEXT:    ret
+  %v = call <vscale x 2 x i15> @llvm.experimental.stepvector.nxv2i15()
+  ret <vscale x 2 x i15> %v
+}
+
 declare <vscale x 3 x i16> @llvm.experimental.stepvector.nxv3i16()
 
 define <vscale x 3 x i16> @stepvector_nxv3i16() {
 ; CHECK-LABEL: stepvector_nxv3i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
 ; CHECK-NEXT:    vid.v v8
 ; CHECK-NEXT:    ret

 entry:
   %0 = insertelement <vscale x 8 x i64> poison, i64 33333333333, i32 0
   %1 = shufflevector <vscale x 8 x i64> %0, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
   %2 = call <vscale x 8 x i64> @llvm.experimental.stepvector.nxv8i64()
   %3 = mul <vscale x 8 x i64> %2, %1
   ret <vscale x 8 x i64> %3
 }
 
-
 define <vscale x 8 x i64> @shl_stepvector_nxv8i64() {
 ; CHECK-LABEL: shl_stepvector_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
 ; CHECK-NEXT:    vid.v v8
 ; CHECK-NEXT:    vsll.vi v8, v8, 2
 ; CHECK-NEXT:    ret
 entry:

llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll

 ; CHECK-NEXT:    vsetvli zero, a0, e64, m4, tu, mu
 ; CHECK-NEXT:    vfredusum.vs v12, v8, v12, v0.t
 ; CHECK-NEXT:    vfmv.f.s fa0, v12
 ; CHECK-NEXT:    ret
   %r = call reassoc double @llvm.vp.reduce.fadd.nxv3f64(double %s, <vscale x 3 x double> %v, <vscale x 3 x i1> %m, i32 %evl)
   ret double %r
 }
 
-define double @vpreduce_ord_fadd_nxv3f64(double %s, <vscale x 4 x double> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+define double @vpreduce_ord_fadd_nxv3f64(double %s, <vscale x 3 x double> %v, <vscale x 3 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: vpreduce_ord_fadd_nxv3f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
 ; CHECK-NEXT:    vfmv.s.f v12, fa0
 ; CHECK-NEXT:    vsetvli zero, a0, e64, m4, tu, mu
 ; CHECK-NEXT:    vfredosum.vs v12, v8, v12, v0.t
 ; CHECK-NEXT:    vfmv.f.s fa0, v12
 ; CHECK-NEXT:    ret
-  %r = call double @llvm.vp.reduce.fadd.nxv4f64(double %s, <vscale x 4 x double> %v, <vscale x 4 x i1> %m, i32 %evl)
+  %r = call double @llvm.vp.reduce.fadd.nxv3f64(double %s, <vscale x 3 x double> %v, <vscale x 3 x i1> %m, i32 %evl)
   ret double %r
 }
 
-
 declare double @llvm.vp.reduce.fadd.nxv4f64(double, <vscale x 4 x double>, <vscale x 4 x i1>, i32)
 
 define double @vpreduce_fadd_nxv4f64(double %s, <vscale x 4 x double> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: vpreduce_fadd_nxv4f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
 ; CHECK-NEXT:    vfmv.s.f v12, fa0
 ; CHECK-NEXT:    vsetvli zero, a0, e64, m4, tu, mu