[clang][AIX] Add option to control quadword lock free atomics ABI on AIX

[lkail]

Summary

We are supporting quadword lock free atomics on AIX. For the situation that users on AIX are using a libatomic that is lock-based for quadword types, we can't enable quadword lock free atomics by default on AIX in case user's new code and existing code accessing the same shared atomic quadword variable, we can't guarentee atomicity. So we need an option to enable quadword lock free atomics on AIX, thus we can build a quadword lock-free libatomic(also for advanced users considering atomic performance critical) for users to make the transition smooth.

[lkail]

Gentle ping.

[amyk]

This patch makes sense. I had some questions regarding it.

clang/include/clang/Driver/Options.td

3642

Would it be better if we called this maix64-quadword-atomics instead?

clang/test/Driver/ppc-unsupported.c

12

Should we have a big endian Linux check, too?

[amyk]

clang/test/Driver/ppc-unsupported.c

12

Oh, sorry. I noticed there wasn't powerpc64-unknown-linux but I realized I think powerpc64-unknown-freebsd is supposed to be the big endian 64-bit Linux check, right?

[lkail]

clang/test/Driver/ppc-unsupported.c

12

Added OS check is following lines above. I'm ok to add powerpc64-unknown-linux too. Thanks for pointing it out.

[lkail]

Address comments.

[nemanjai]

I am ok with this change overall, I just have a couple of questions about naming of the option.

1. Is there any precedent for options that start with -maix or -m<OS> for any other OS?
2. Is quadword the best word to use? There is no type information and this is restricted to integers. Would something like -maix-i128-atomics be a better name?
3. Since this is kind of an ABI-related decision, would it make sense (and would it be possible) to make this a further suboption to the -mabi option? Something like -mabi=vec-extabi,i128-atomics,ieeelongdouble

[lkail]

Is there any precedent for options that start with -maix or -m<OS> for any other OS?

There is -maix-struct-return.

Is quadword the best word to use? There is no type information and this is restricted to integers. Would something like -maix-i128-atomics be a better name?

'quadword' is used in ISA manual, so I follow it. Not merely i128, some struct types are also included, like

struct Q {
  char c[16];
};

Since this is kind of an ABI-related decision, would it make sense (and would it be possible) to make this a further suboption to the -mabi option?

This makes sense. I'll try this solution.

[lkail]

Option name changed to -mabi=quadword-atomics as nemanja suggested.

[lkail]

Ping.

[lkail]

Gentle ping.

[shchenz]

Can we use the feature bit FeatureQuadwordAtomic to decide whether QuadAtomic is supported or not on AIX? Like what we do for Linux.

The reason we need this option is: we may need to compile a lock free libatomic on a Power7 or below target? If so, do we have similar issue on Linux? Thanks.

clang/include/clang/Driver/Options.td

3642

Do we need to change the backend check below too?

bool PPCTargetLowering::shouldInlineQuadwordAtomics() const {
  // TODO: 16-byte atomic type support for AIX is in progress; we should be able
  // to inline 16-byte atomic ops on AIX too in the future.
  return Subtarget.isPPC64() &&
         (EnableQuadwordAtomics || !Subtarget.getTargetTriple().isOSAIX()) &&
         Subtarget.hasQuadwordAtomics();
}

clang/lib/Basic/Targets/PPC.cpp

854

Can we set MaxAtomicInlineWidth in PPC64TargetInfo::setMaxAtomicWidth()? There is a TODO there

[lkail]

Can we use the feature bit FeatureQuadwordAtomic to decide whether QuadAtomic is supported or not on AIX? Like what we do for Linux.

FeatureQuadwordAtomic is for cpu level control, while -mabi=quadword-atomics is for ABI level. AIX running on pwr8+ also features FeatureQuadwordAtomic, but in the case described in the patch summary, sometimes we can't enable quadword lock free atomics on AIX by default, so that clang generate libcalls into libatomic rather than inlining lock free operations. libatomic has the final decision to use lock-free version or not.

The reason we need this option is: we may need to compile a lock free libatomic on a Power7 or below target?

We need to compile a quadword lock free libatomic for CPUs above pwr8.

If so, do we have similar issue on Linux? Thanks.

On Linux, clang is linking against GNU's libatomic by default, that depends on GNU libatomic's behaviour.

[lkail]

clang/include/clang/Driver/Options.td

3642

We don't need to change this yet. When we are compiling a quadword lock free libatomic, we use options -mabi=quadword-atomics -mllvm -ppc-quadword-atomics to enforce generating quadword lock-free code on AIX.

clang/lib/Basic/Targets/PPC.cpp

854

The TODO marks our roadmap towards enabling quardword lock free atomics on AIX too. Putting adjustment here is implementation reason: we don't context of LanguageOptions in PPC64TargetInfo::PPC64TargetInfo.

[shchenz]

Thanks for the explanation. I am more clear now about the background.

clang/include/clang/Driver/Options.td

3642

This makes me confuse. We need to two different options to control the frontend and backend behavior?

Is it the final usage? Or we will add a follow up patch to map the backend one to the FE one? IMO finally we only need the driver option -mabi=quadword-atomics to control the final code generation for 128 bit atomic operations, right?

clang/lib/Basic/Targets/PPC.cpp

854

OK, fair enough.

[lkail]

clang/include/clang/Driver/Options.td

3642

This makes me confuse. We need to two different options to control the frontend and backend behavior?

This is multi-lang support consideration. clang is not the only frontend we have using LLVM as backend on AIX. If other language frontend generates store atomic i128, ..., the backend is supposed to generate libcalls into libatomic currently.

Is it the final usage?

No. We finally want to achieve -mabi=quadword-atomics by default and generate inline atomic code for cpu above pwr7 by default(no need to take OS into consideration).

[shchenz]

clang/include/clang/Driver/Options.td

3642

I know what you mean. But I assume the driver option -mabi=quadword-atomics will impact the assembly instead of just impact the frontend, right? Using -mllvm option is not right as the final solution.

There are some driver options example, like -gstrict-dwarf, Frontend can control the backend behavior and the backend can also change this option by -strict-dwarf.

Could you please explain:
1: how the backend will handle -mabi=quadword-atomics in future?
2: on what condition, we can start to remove below TODOs:

bool PPCTargetLowering::shouldInlineQuadwordAtomics() const {
// TODO: 16-byte atomic type support for AIX is in progress;
}

PPC64TargetInfo::setMaxAtomicWidth() {
    // TODO: We should allow AIX to inline quadword atomics in the future.
}

[lkail]

clang/include/clang/Driver/Options.td

3642

1, 2 can be answered together. After we ship new libatomic to users(I assume that that isn't in near future, since this requires AIX OS upgrade), we can enable quadword lock free atomics in both clang and llvm backend by default. Backend isn't aware of -mabi=quadword-atomics. This option changes layout of quadword atomic types(align to 16 byte), and generate atomic LLVM IR rather than generating libcalls in LLVM IR.

[shchenz]

LGTM. Thanks.

clang/include/clang/Basic/LangOptions.def

VALUE_LANGOPT(PackStruct  , 32, 0,
               "default struct packing maximum alignment")
 VALUE_LANGOPT(MaxTypeAlign  , 32, 0,
               "default maximum alignment for types")
 VALUE_LANGOPT(AlignDouble            , 1, 0, "Controls if doubles should be aligned to 8 bytes (x86 only)")
 VALUE_LANGOPT(DoubleSize            , 32, 0, "width of double")
 VALUE_LANGOPT(LongDoubleSize        , 32, 0, "width of long double")
 LANGOPT(PPCIEEELongDouble            , 1, 0, "use IEEE 754 quadruple-precision for long double")
 LANGOPT(EnableAIXExtendedAltivecABI  , 1, 0, "__EXTABI__  predefined macro")
+LANGOPT(EnableAIXQuadwordAtomicsABI  , 1, 0, "Use 16-byte atomic lock free semantics")
 COMPATIBLE_VALUE_LANGOPT(PICLevel    , 2, 0, "__PIC__ level")
 COMPATIBLE_VALUE_LANGOPT(PIE         , 1, 0, "is pie")
 LANGOPT(ROPI                         , 1, 0, "Read-only position independence")
 LANGOPT(RWPI                         , 1, 0, "Read-write position independence")
 COMPATIBLE_LANGOPT(GNUInline         , 1, 0, "GNU inline semantics")
 COMPATIBLE_LANGOPT(NoInlineDefine    , 1, 0, "__NO_INLINE__ predefined macro")
 COMPATIBLE_LANGOPT(Deprecated        , 1, 0, "__DEPRECATED predefined macro")
 COMPATIBLE_LANGOPT(FastMath          , 1, 0, "fast FP math optimizations, and __FAST_MATH__ predefined macro")

clang/include/clang/Driver/Options.td

 def mspe : Flag<["-"], "mspe">, Group<m_ppc_Features_Group>;
 def mno_spe : Flag<["-"], "mno-spe">, Group<m_ppc_Features_Group>;
 def mefpu2 : Flag<["-"], "mefpu2">, Group<m_ppc_Features_Group>;
 def mabi_EQ_vec_extabi : Flag<["-"], "mabi=vec-extabi">, Group<m_Group>, Flags<[CC1Option]>,
   HelpText<"Enable the extended Altivec ABI on AIX (AIX only). Uses volatile and nonvolatile vector registers">,
   MarshallingInfoFlag<LangOpts<"EnableAIXExtendedAltivecABI">>;
 def mabi_EQ_vec_default : Flag<["-"], "mabi=vec-default">, Group<m_Group>, Flags<[CC1Option]>,
   HelpText<"Enable the default Altivec ABI on AIX (AIX only). Uses only volatile vector registers.">;
+def maix64_quadword_atomics : Flag<["-"], "maix64-quadword-atomics">,
+  Group<m_Group>, Flags<[CC1Option]>,
+  HelpText<"Enable quadword atomics ABI on AIX (PPC64 only). Use lqarx/stqcx. instructions.">,
+  MarshallingInfoFlag<LangOpts<"EnableAIXQuadwordAtomicsABI">>;
 def mvsx : Flag<["-"], "mvsx">, Group<m_ppc_Features_Group>;
 def mno_vsx : Flag<["-"], "mno-vsx">, Group<m_ppc_Features_Group>;
 def msecure_plt : Flag<["-"], "msecure-plt">, Group<m_ppc_Features_Group>;
 def mpower8_vector : Flag<["-"], "mpower8-vector">,
     Group<m_ppc_Features_Group>;
 def mno_power8_vector : Flag<["-"], "mno-power8-vector">,
     Group<m_ppc_Features_Group>;
 def mpower9_vector : Flag<["-"], "mpower9-vector">,

clang/lib/Basic/Targets/PPC.cpp

void PPCTargetInfo::adjust(DiagnosticsEngine &Diags, LangOptions &Opts) {
   if (HasAltivec)
     Opts.AltiVec = 1;
   TargetInfo::adjust(Diags, Opts);
   if (LongDoubleFormat != &llvm::APFloat::IEEEdouble())
     LongDoubleFormat = Opts.PPCIEEELongDouble
                            ? &llvm::APFloat::IEEEquad()
                            : &llvm::APFloat::PPCDoubleDouble();
   Opts.IEEE128 = 1;
+  if (getTriple().isOSAIX() && Opts.EnableAIXQuadwordAtomicsABI &&
+      HasQuadwordAtomics)
+    MaxAtomicInlineWidth = 128;
 }
 
 ArrayRef<Builtin::Info> PPCTargetInfo::getTargetBuiltins() const {
   return llvm::makeArrayRef(BuiltinInfo, clang::PPC::LastTSBuiltin -
                                              Builtin::FirstTSBuiltin);
 }

clang/lib/Driver/ToolChains/Clang.cpp

if (!Triple.isOSAIX())
       D.Diag(diag::err_drv_unsupported_opt_for_target)
           << A->getSpelling() << RawTriple.str();
     if (A->getOption().getID() == options::OPT_mabi_EQ_vec_extabi)
       CmdArgs.push_back("-mabi=vec-extabi");
     else
       CmdArgs.push_back("-mabi=vec-default");
   }
 
+  if (Arg *A = Args.getLastArg(options::OPT_maix64_quadword_atomics)) {
+    if (!Triple.isOSAIX() || Triple.isPPC32())
+      D.Diag(diag::err_drv_unsupported_opt_for_target)
+        << A->getSpelling() << RawTriple.str();
+    CmdArgs.push_back("-maix64-quadword-atomics");
+  }
+
   if (Arg *A = Args.getLastArg(options::OPT_mlong_double_128)) {
     // Emit the unsupported option error until the Clang's library integration
     // support for 128-bit long double is available for AIX.
     if (Triple.isOSAIX())
       D.Diag(diag::err_drv_unsupported_opt_for_target)
           << A->getSpelling() << RawTriple.str();
   }
 

clang/lib/Frontend/CompilerInvocation.cpp

if (Arg *A =
     if (!T.isOSAIX())
       Diags.Report(diag::err_drv_unsupported_opt_for_target)
           << A->getSpelling() << T.str();
 
     const Option &O = A->getOption();
     Opts.EnableAIXExtendedAltivecABI = O.matches(OPT_mabi_EQ_vec_extabi);
   }
 
+  if (Arg *A = Args.getLastArg(OPT_maix64_quadword_atomics)) {
+    if (!T.isOSAIX() || T.isPPC32())
+      Diags.Report(diag::err_drv_unsupported_opt_for_target)
+        << A->getSpelling() << T.str();
+  }
+
   bool NeedLocTracking = false;
 
   if (!Opts.OptRecordFile.empty())
     NeedLocTracking = true;
 
   if (Arg *A = Args.getLastArg(OPT_opt_record_passes)) {
     Opts.OptRecordPasses = A->getValue();
     NeedLocTracking = true;

clang/test/CodeGen/PowerPC/quadword-atomics.c

 // RUN: %clang_cc1 -no-opaque-pointers -Werror -Wno-atomic-alignment -triple powerpc64le-linux-gnu \
-// RUN:   -target-cpu pwr8 -emit-llvm -o - %s | FileCheck %s --check-prefix=PPC64-PWR8
+// RUN:   -target-cpu pwr8 -emit-llvm -o - %s | FileCheck %s --check-prefix=PPC64-QUADWORD-ATOMICS
 // RUN: %clang_cc1 -no-opaque-pointers -Werror -Wno-atomic-alignment -triple powerpc64le-linux-gnu \
 // RUN:   -emit-llvm -o - %s | FileCheck %s --check-prefix=PPC64
 // RUN: %clang_cc1 -no-opaque-pointers -Werror -Wno-atomic-alignment -triple powerpc64-unknown-aix \
 // RUN:   -target-cpu pwr7 -emit-llvm -o - %s | FileCheck %s --check-prefix=PPC64
+// RUN: %clang_cc1 -no-opaque-pointers -Werror -Wno-atomic-alignment -triple powerpc64-unknown-aix \
+// RUN:   -target-cpu pwr8 -emit-llvm -o - %s | FileCheck %s --check-prefix=PPC64
+// RUN: %clang_cc1 -no-opaque-pointers -Werror -Wno-atomic-alignment -triple powerpc64-unknown-aix \
+// RUN:   -maix64-quadword-atomics -target-cpu pwr8 -emit-llvm -o - %s | FileCheck %s \
+// RUN:   --check-prefix=PPC64-QUADWORD-ATOMICS
+
 
 typedef struct {
   char x[16];
 } Q;
 
 typedef _Atomic(Q) AtomicQ;
 
 typedef __int128_t int128_t;
 
-// PPC64-PWR8-LABEL: @test_load(
-// PPC64-PWR8:    [[TMP3:%.*]] = load atomic i128, i128* [[TMP1:%.*]] acquire, align 16
+// PPC64-QUADWORD-ATOMICS-LABEL: @test_load(
+// PPC64-QUADWORD-ATOMICS:    [[TMP3:%.*]] = load atomic i128, i128* [[TMP1:%.*]] acquire, align 16
 //
 // PPC64-LABEL: @test_load(
 // PPC64:    call void @__atomic_load(i64 noundef 16, i8* noundef [[TMP3:%.*]], i8* noundef [[TMP4:%.*]], i32 noundef signext 2)
 //
 Q test_load(AtomicQ *ptr) {
   // expected-no-diagnostics
   return __c11_atomic_load(ptr, __ATOMIC_ACQUIRE);
 }
 
-// PPC64-PWR8-LABEL: @test_store(
-// PPC64-PWR8:    store atomic i128 [[TMP6:%.*]], i128* [[TMP4:%.*]] release, align 16
+// PPC64-QUADWORD-ATOMICS-LABEL: @test_store(
+// PPC64-QUADWORD-ATOMICS:    store atomic i128 [[TMP6:%.*]], i128* [[TMP4:%.*]] release, align 16
 //
 // PPC64-LABEL: @test_store(
 // PPC64:    call void @__atomic_store(i64 noundef 16, i8* noundef [[TMP6:%.*]], i8* noundef [[TMP7:%.*]], i32 noundef signext 3)
 //
 void test_store(Q val, AtomicQ *ptr) {
   // expected-no-diagnostics
   __c11_atomic_store(ptr, val, __ATOMIC_RELEASE);
 }
 
-// PPC64-PWR8-LABEL: @test_add(
-// PPC64-PWR8:    [[TMP3:%.*]] = atomicrmw add i128* [[TMP0:%.*]], i128 [[TMP2:%.*]] monotonic, align 16
+// PPC64-QUADWORD-ATOMICS-LABEL: @test_add(
+// PPC64-QUADWORD-ATOMICS:    [[TMP3:%.*]] = atomicrmw add i128* [[TMP0:%.*]], i128 [[TMP2:%.*]] monotonic, align 16
 //
 // PPC64-LABEL: @test_add(
 // PPC64:    [[CALL:%.*]] = call i128 @__atomic_fetch_add_16(i8* noundef [[TMP2:%.*]], i128 noundef [[TMP3:%.*]], i32 noundef signext 0)
 //
 void test_add(_Atomic(int128_t) *ptr, int128_t x) {
   // expected-no-diagnostics
   __c11_atomic_fetch_add(ptr, x, __ATOMIC_RELAXED);
 }
 
-// PPC64-PWR8-LABEL: @test_xchg(
-// PPC64-PWR8:    [[TMP8:%.*]] = atomicrmw xchg i128* [[TMP4:%.*]], i128 [[TMP7:%.*]] seq_cst, align 16
+// PPC64-QUADWORD-ATOMICS-LABEL: @test_xchg(
+// PPC64-QUADWORD-ATOMICS:    [[TMP8:%.*]] = atomicrmw xchg i128* [[TMP4:%.*]], i128 [[TMP7:%.*]] seq_cst, align 16
 //
 // PPC64-LABEL: @test_xchg(
 // PPC64:    call void @__atomic_exchange(i64 noundef 16, i8* noundef [[TMP7:%.*]], i8* noundef [[TMP8:%.*]], i8* noundef [[TMP9:%.*]], i32 noundef signext 5)
 //
 Q test_xchg(AtomicQ *ptr, Q new) {
   // expected-no-diagnostics
   return __c11_atomic_exchange(ptr, new, __ATOMIC_SEQ_CST);
 }
 
-// PPC64-PWR8-LABEL: @test_cmpxchg(
-// PPC64-PWR8:    [[TMP10:%.*]] = cmpxchg i128* [[TMP5:%.*]], i128 [[TMP8:%.*]], i128 [[TMP9:%.*]] seq_cst monotonic, align 16
+// PPC64-QUADWORD-ATOMICS-LABEL: @test_cmpxchg(
+// PPC64-QUADWORD-ATOMICS:    [[TMP10:%.*]] = cmpxchg i128* [[TMP5:%.*]], i128 [[TMP8:%.*]], i128 [[TMP9:%.*]] seq_cst monotonic, align 16
 //
 // PPC64-LABEL: @test_cmpxchg(
 // PPC64:    [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 noundef 16, i8* noundef [[TMP8:%.*]], i8* noundef [[TMP9:%.*]], i8* noundef [[TMP10:%.*]], i32 noundef signext 5, i32 noundef signext 0)
 //
 int test_cmpxchg(AtomicQ *ptr, Q *cmp, Q new) {
   // expected-no-diagnostics
   return __c11_atomic_compare_exchange_strong(ptr, cmp, new, __ATOMIC_SEQ_CST, __ATOMIC_RELAXED);
 }
 
-// PPC64-PWR8-LABEL: @test_cmpxchg_weak(
-// PPC64-PWR8:    [[TMP10:%.*]] = cmpxchg weak i128* [[TMP5:%.*]], i128 [[TMP8:%.*]], i128 [[TMP9:%.*]] seq_cst monotonic, align 16
+// PPC64-QUADWORD-ATOMICS-LABEL: @test_cmpxchg_weak(
+// PPC64-QUADWORD-ATOMICS:    [[TMP10:%.*]] = cmpxchg weak i128* [[TMP5:%.*]], i128 [[TMP8:%.*]], i128 [[TMP9:%.*]] seq_cst monotonic, align 16
 //
 // PPC64-LABEL: @test_cmpxchg_weak(
 // PPC64:    [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 noundef 16, i8* noundef [[TMP8:%.*]], i8* noundef [[TMP9:%.*]], i8* noundef [[TMP10:%.*]], i32 noundef signext 5, i32 noundef signext 0)
 //
 int test_cmpxchg_weak(AtomicQ *ptr, Q *cmp, Q new) {
   // expected-no-diagnostics
   return __c11_atomic_compare_exchange_weak(ptr, cmp, new, __ATOMIC_SEQ_CST, __ATOMIC_RELAXED);
 }
 
-// PPC64-PWR8-LABEL: @is_lock_free(
-// PPC64-PWR8:    ret i32 1
+// PPC64-QUADWORD-ATOMICS-LABEL: @is_lock_free(
+// PPC64-QUADWORD-ATOMICS:    ret i32 1
 //
 // PPC64-LABEL: @is_lock_free(
 // PPC64:    [[CALL:%.*]] = call zeroext i1 @__atomic_is_lock_free(i64 noundef 16, i8* noundef null)
 //
 int is_lock_free() {
   AtomicQ q;
  // expected-no-diagnostics
   return __c11_atomic_is_lock_free(sizeof(q));
 }

clang/test/Driver/aix-quadword-atomics-abi.c

+// RUN:  %clang -### -target powerpc-unknown-aix -S %s 2>&1 | FileCheck %s
+// RUN:  %clang -### -target powerpc64-unknown-aix -S %s 2>&1 | FileCheck %s
+// RUN:  %clang -### -target powerpc-unknown-aix -maix64-quadword-atomics -S \
+// RUN:    %s 2>&1 | FileCheck --check-prefix=CHECK-UNSUPPORTED-TARGET %s
+// RUN:  %clang -### -target powerpc64-unknown-aix -maix64-quadword-atomics -S \
+// RUN:    %s 2>&1 | FileCheck %s --check-prefix=CHECK-QUADWORD-ATOMICS
+//
+// CHECK-UNSUPPORTED-TARGET: unsupported option '-maix64-quadword-atomics' for target 'powerpc-unknown-aix'
+// CHECK-NOT: "-maix64-quadword-atomics"
+// CHECK-QUADWORD-ATOMICS: "-cc1"
+// CHECK-QUADWORD-ATOMICS-SAME: "-maix64-quadword-atomics"

clang/test/Driver/ppc-unsupported.c

 // REQUIRES: powerpc-registered-target
 // RUN: not %clang -target powerpc64-unknown-freebsd -maix-struct-return \
 // RUN:   -c %s 2>&1 | FileCheck %s
 // RUN: not %clang -target powerpc64-unknown-freebsd -msvr4-struct-return \
 // RUN:   -c %s 2>&1 | FileCheck %s
 // RUN: not %clang -target powerpc64le-unknown-linux -maix-struct-return \
 // RUN:   -c %s 2>&1 | FileCheck %s
 // RUN: not %clang -target powerpc64le-unknown-linux -msvr4-struct-return \
 // RUN:   -c %s 2>&1 | FileCheck %s
+// RUN: not %clang -target powerpc64-unknown-freebsd -maix64-quadword-atomics \
+// RUN:   -c %s 2>&1 | FileCheck %s
+// RUN: not %clang -target powerpc64-unknown-linux -maix64-quadword-atomics \
+// RUN:   -c %s 2>&1 | FileCheck %s
+// RUN: not %clang -target powerpc64le-unknown-linux -maix64-quadword-atomics \
+// RUN:   -c %s 2>&1 | FileCheck %s
+// RUN: not %clang -target powerpc-unknown-unknown -maix64-quadword-atomics \
+// RUN:   -c %s 2>&1 | FileCheck %s
+// RUN: not %clang -target powerpc-unknown-aix -maix64-quadword-atomics \
+// RUN:   -c %s 2>&1 | FileCheck %s
 // CHECK: unsupported option

clang/test/Sema/atomic-ops.c

 // RUN: %clang_cc1 %s -verify=expected,fp80,noi128 -fgnuc-version=4.2.1 -ffreestanding \
 // RUN:   -fsyntax-only -triple=i686-linux-gnu -std=c11
 // RUN: %clang_cc1 %s -verify=expected,noi128 -fgnuc-version=4.2.1 -ffreestanding \
 // RUN:   -fsyntax-only -triple=i686-linux-android -std=c11
 // RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
 // RUN:   -fsyntax-only -triple=powerpc64-linux-gnu -std=c11
 // RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
 // RUN:   -fsyntax-only -triple=powerpc64-linux-gnu -std=c11 \
 // RUN:   -target-cpu pwr7
 // RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
 // RUN:   -fsyntax-only -triple=powerpc64le-linux-gnu -std=c11 \
 // RUN:   -target-cpu pwr8 -DPPC64_PWR8
+// RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
+// RUN:   -fsyntax-only -triple=powerpc64-unknown-aix -std=c11 \
+// RUN:   -target-cpu pwr8
+// RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
+// RUN:   -fsyntax-only -triple=powerpc64-unknown-aix -std=c11 \
+// RUN:   -maix64-quadword-atomics -target-cpu pwr8 -DPPC64_PWR8
 
 // Basic parsing/Sema tests for __c11_atomic_*
 
 #include <stdatomic.h>
 
 struct S { char c[3]; };
 
 _Static_assert(__GCC_ATOMIC_BOOL_LOCK_FREE == 2, "");