[RISCV] Change GPRPF64's hwmode and spill alignment

[StephenFan]

Summary

GPRPF64 is only available when zdinx enabled on RV32.
GPRPF64 is composed of two GPR register, therefore the
spill alignment value should be consistent with GPR,
which is 32 bits in RV32.

[sunshaoce]

LGTM

[asb]

I'm a little nervous something may subtly break here (e.g. due to an assumption that any spilled f64 value will always be stored properly aligned). I note AFGR64 on Mips and IntPair on Sparc for instance both have 64-bit alignment. That's just a gut feeling though - I don't have a particular broken test case in mind. Have you explored this kind of potential problem?

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

def X#Index#_PD : RISCVRegWithSubRegs<Index, Reg.AsmName,
                                           [!cast<Register>("X"#Index),
                                            !cast<Register>("X"#!add(Index, 1))],
                                            Reg.AltNames> {
       let SubRegIndices = [sub_32, sub_32_hi];
     }
   }
 }
 
-let RegInfos = RegInfoByHwMode<[RV64], [RegInfo<64, 64, 64>]> in
-def GPRPF64 : RegisterClass<"RISCV", [f64], 64, (add
+let RegInfos = RegInfoByHwMode<[RV32], [RegInfo<64, 64, 32>]> in
+def GPRPF64 : RegisterClass<"RISCV", [f64], 32, (add
     X10_PD, X12_PD, X14_PD, X16_PD,
     X6_PD,
     X28_PD, X30_PD,
     X8_PD,
     X18_PD, X20_PD, X22_PD, X24_PD, X26_PD,
     X0_PD, X2_PD, X4_PD
 )>;