[AArch64] Look through copy in MachineCombiner FMUL patterns.

[dmgreen]

Summary

This is a small addition to D99662, which added machine combiner patterns for FMUL(DUP(..)). Due to the way these are generated from ISel, they may also be FMUL(COPY(DUP(..))), which this patch now ignores.

[SjoerdMeijer]

LGTM

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

5173

Perhaps a comment that we ignore the copy in FMUL(COPY(DUP(..)))?

[asavonic]

LGTM, thanks!

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

static bool getFMULPatterns(MachineInstr &Root,
 
   auto Match = [&](unsigned Opcode, int Operand,
                    MachineCombinerPattern Pattern) -> bool {
     MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
     MachineOperand &MO = Root.getOperand(Operand);
     MachineInstr *MI = nullptr;
     if (MO.isReg() && Register::isVirtualRegister(MO.getReg()))
       MI = MRI.getUniqueVRegDef(MO.getReg());
+    if (MI && MI->getOpcode() == TargetOpcode::COPY &&
+        MI->getOperand(1).getReg().isVirtual())
+      MI = MRI.getUniqueVRegDef(MI->getOperand(1).getReg());
     if (MI && MI->getOpcode() == Opcode) {
       Patterns.push_back(Pattern);
       return true;
     }
     return false;
   };
 
   typedef MachineCombinerPattern MCP;
assert(((IdxDupOp == 1) || (IdxDupOp == 2)) &&
          "Invalid index of FMUL operand");
 
   MachineFunction &MF = *Root.getMF();
   const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
 
   MachineInstr *Dup =
       MF.getRegInfo().getUniqueVRegDef(Root.getOperand(IdxDupOp).getReg());
 
+  if (Dup->getOpcode() == TargetOpcode::COPY)
+    Dup = MRI.getUniqueVRegDef(Dup->getOperand(1).getReg());
+
   Register DupSrcReg = Dup->getOperand(1).getReg();
   MRI.clearKillFlags(DupSrcReg);
   MRI.constrainRegClass(DupSrcReg, RC);
 
   unsigned DupSrcLane = Dup->getOperand(2).getImm();
 
   unsigned IdxMulOp = IdxDupOp == 1 ? 2 : 1;
   MachineOperand &MulOp = Root.getOperand(IdxMulOp);

llvm/test/CodeGen/AArch64/machine-combiner-copy.ll

 ; CHECK-NEXT:  // %bb.2:
 ; CHECK-NEXT:    mov x9, xzr
 ; CHECK-NEXT:    b .LBB0_6
 ; CHECK-NEXT:  .LBB0_3: // %vector.ph
 ; CHECK-NEXT:    and x9, x8, #0xfffffff0
 ; CHECK-NEXT:    add x10, x1, #16
 ; CHECK-NEXT:    add x11, x0, #16
 ; CHECK-NEXT:    mov x12, x9
-; CHECK-NEXT:    dup v1.8h, v0.h[0]
 ; CHECK-NEXT:  .LBB0_4: // %vector.body
 ; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    ldp q2, q3, [x11, #-16]
+; CHECK-NEXT:    ldp q1, q2, [x11, #-16]
 ; CHECK-NEXT:    subs x12, x12, #16
 ; CHECK-NEXT:    add x11, x11, #32
-; CHECK-NEXT:    ldp q4, q5, [x10, #-16]
-; CHECK-NEXT:    fmla v4.8h, v2.8h, v1.8h
-; CHECK-NEXT:    fmla v5.8h, v3.8h, v0.h[0]
-; CHECK-NEXT:    stp q4, q5, [x10, #-16]
+; CHECK-NEXT:    ldp q3, q4, [x10, #-16]
+; CHECK-NEXT:    fmla v3.8h, v1.8h, v0.h[0]
+; CHECK-NEXT:    fmla v4.8h, v2.8h, v0.h[0]
+; CHECK-NEXT:    stp q3, q4, [x10, #-16]
 ; CHECK-NEXT:    add x10, x10, #32
 ; CHECK-NEXT:    b.ne .LBB0_4
 ; CHECK-NEXT:  // %bb.5: // %middle.block
 ; CHECK-NEXT:    cmp x9, x8
 ; CHECK-NEXT:    b.eq .LBB0_8
 ; CHECK-NEXT:  .LBB0_6: // %for.body.preheader1
 ; CHECK-NEXT:    lsl x10, x9, #1
 ; CHECK-NEXT:    sub x8, x8, x9

llvm/test/CodeGen/AArch64/machine-combiner-fmul-dup.mir

body:             |
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr64common = COPY $x0
   ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:fpr64 = COPY $d2
   ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:fpr64 = COPY $d1
   ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:fpr64 = COPY $d0
   ; CHECK-NEXT:   [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
   ; CHECK-NEXT:   [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY3]], %subreg.dsub
   ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:fpr64 = COPY [[COPY1]]
   ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:fpr64 = COPY [[COPY2]]
-  ; CHECK-NEXT:   [[DUPv2i32lane:%[0-9]+]]:fpr64 = DUPv2i32lane killed [[INSERT_SUBREG]], 0
+  ; CHECK-NEXT:   [[DUPv2i32lane:%[0-9]+]]:fpr64 = DUPv2i32lane [[INSERT_SUBREG]], 0
   ; CHECK-NEXT:   [[COPY6:%[0-9]+]]:fpr64 = COPY [[DUPv2i32lane]]
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
-  ; CHECK-NEXT:   [[FMULv2f32_:%[0-9]+]]:fpr64 = FMULv2f32 [[COPY5]], [[COPY6]]
-  ; CHECK-NEXT:   [[FADDv2f32_:%[0-9]+]]:fpr64 = FADDv2f32 killed [[FMULv2f32_]], [[COPY4]]
+  ; CHECK-NEXT:   [[FMULv2i32_indexed:%[0-9]+]]:fpr64 = FMULv2i32_indexed [[COPY5]], [[INSERT_SUBREG]], 0
+  ; CHECK-NEXT:   [[FADDv2f32_:%[0-9]+]]:fpr64 = FADDv2f32 killed [[FMULv2i32_indexed]], [[COPY4]]
   ; CHECK-NEXT:   STRDui killed [[FADDv2f32_]], [[COPY]], 0 :: (store (s64), align 16)
   ; CHECK-NEXT:   B %bb.1
   bb.0:
     liveins: $d0, $d1, $d2, $x0
 
     %4:gpr64common = COPY $x0
     %3:fpr64 = COPY $d2
     %2:fpr64 = COPY $d1