[RISCV] Fix vnsrl/vnsra isel patterns that are dropping VL.

[craig.topper]

Summary

We were incorrectly using VLMax instead of the passed VL.

[khchen]

LGTM!

[frasercrmck]

Great catch!

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

def : Pat<
       (vti.Vector
         (riscv_trunc_vector_vl
           (op (wti.Vector wti.RegClass:$rs2),
               (wti.Vector (extop (vti.Vector (SplatPat GPR:$rs1)),
                                  (vti.Mask true_mask), VLOpFrag)),
           (wti.Mask true_mask), VLOpFrag),
         (vti.Mask true_mask), VLOpFrag)),
       (!cast<Instruction>(instruction_name#"_WX_"#vti.LMul.MX)
-        wti.RegClass:$rs2, GPR:$rs1, vti.AVL, vti.Log2SEW)>;
+        wti.RegClass:$rs2, GPR:$rs1, GPR:$vl, vti.Log2SEW)>;
   }
 }
 
 multiclass VPatMultiplyAddVL_VV_VX<SDNode op, string instruction_name> {
   foreach vti = AllIntegerVectors in {
     defvar suffix = vti.LMul.MX;
     // NOTE: We choose VMADD because it has the most commuting freedom. So it
     // works best with how TwoAddressInstructionPass tries commuting.

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnsra-vnsrl.ll

; CHECK-NEXT:    ret
   %a = ashr <8 x i16> %x, %splat
   %b = trunc <8 x i16> %a to <8 x i8>
   ret <8 x i8> %b
 }
 
 define <8 x i8> @vnsra_v8i16_v8i8_scalar_sext(<8 x i16> %x, i8 %y) {
 ; CHECK-LABEL: vnsra_v8i16_v8i8_scalar_sext:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
+; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vnsra.wx v8, v8, a0
 ; CHECK-NEXT:    ret
   %insert = insertelement <8 x i8> poison, i8 %y, i8 0
   %splat = shufflevector <8 x i8> %insert, <8 x i8> poison, <8 x i32> zeroinitializer
   %sext = sext <8 x i8> %splat to <8 x i16>
   %a = ashr <8 x i16> %x, %sext
   %b = trunc <8 x i16> %a to <8 x i8>
   ret <8 x i8> %b
 }
 
 define <8 x i8> @vnsra_v8i16_v8i8_scalar_zext(<8 x i16> %x, i8 %y) {
 ; CHECK-LABEL: vnsra_v8i16_v8i8_scalar_zext:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
+; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vnsra.wx v8, v8, a0
 ; CHECK-NEXT:    ret
   %insert = insertelement <8 x i8> poison, i8 %y, i8 0
   %splat = shufflevector <8 x i8> %insert, <8 x i8> poison, <8 x i32> zeroinitializer
   %zext = zext <8 x i8> %splat to <8 x i16>
   %a = ashr <8 x i16> %x, %zext
   %b = trunc <8 x i16> %a to <8 x i8>
   ret <8 x i8> %b
; CHECK-NEXT:    ret
   %a = ashr <4 x i32> %x, %splat
   %b = trunc <4 x i32> %a to <4 x i16>
   ret <4 x i16> %b
 }
 
 define <4 x i16> @vnsra_v4i32_v4i16_scalar_sext(<4 x i32> %x, i16 %y) {
 ; CHECK-LABEL: vnsra_v4i32_v4i16_scalar_sext:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
+; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, mu
 ; CHECK-NEXT:    vnsra.wx v8, v8, a0
 ; CHECK-NEXT:    ret
   %insert = insertelement <4 x i16> poison, i16 %y, i16 0
   %splat = shufflevector <4 x i16> %insert, <4 x i16> poison, <4 x i32> zeroinitializer
   %sext = sext <4 x i16> %splat to <4 x i32>
   %a = ashr <4 x i32> %x, %sext
   %b = trunc <4 x i32> %a to <4 x i16>
   ret <4 x i16> %b
 }
 
 define <4 x i16> @vnsra_v4i32_v4i16_scalar_zext(<4 x i32> %x, i16 %y) {
 ; CHECK-LABEL: vnsra_v4i32_v4i16_scalar_zext:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
+; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, mu
 ; CHECK-NEXT:    vnsra.wx v8, v8, a0
 ; CHECK-NEXT:    ret
   %insert = insertelement <4 x i16> poison, i16 %y, i16 0
   %splat = shufflevector <4 x i16> %insert, <4 x i16> poison, <4 x i32> zeroinitializer
   %zext = zext <4 x i16> %splat to <4 x i32>
   %a = ashr <4 x i32> %x, %zext
   %b = trunc <4 x i32> %a to <4 x i16>
   ret <4 x i16> %b
; CHECK-NEXT:    ret
   %a = ashr <2 x i64> %x, %splat
   %b = trunc <2 x i64> %a to <2 x i32>
   ret <2 x i32> %b
 }
 
 define <2 x i32> @vnsra_v2i64_v2i32_scalar_sext(<2 x i64> %x, i32 %y) {
 ; CHECK-LABEL: vnsra_v2i64_v2i32_scalar_sext:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, mu
 ; CHECK-NEXT:    vnsra.wx v8, v8, a0
 ; CHECK-NEXT:    ret
   %insert = insertelement <2 x i32> poison, i32 %y, i32 0
   %splat = shufflevector <2 x i32> %insert, <2 x i32> poison, <2 x i32> zeroinitializer
   %sext = sext <2 x i32> %splat to <2 x i64>
   %a = ashr <2 x i64> %x, %sext
   %b = trunc <2 x i64> %a to <2 x i32>
   ret <2 x i32> %b
 }
 
 define <2 x i32> @vnsra_v2i64_v2i32_scalar_zext(<2 x i64> %x, i32 %y) {
 ; CHECK-LABEL: vnsra_v2i64_v2i32_scalar_zext:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, mu
 ; CHECK-NEXT:    vnsra.wx v8, v8, a0
 ; CHECK-NEXT:    ret
   %insert = insertelement <2 x i32> poison, i32 %y, i32 0
   %splat = shufflevector <2 x i32> %insert, <2 x i32> poison, <2 x i32> zeroinitializer
   %zext = zext <2 x i32> %splat to <2 x i64>
   %a = ashr <2 x i64> %x, %zext
   %b = trunc <2 x i64> %a to <2 x i32>
   ret <2 x i32> %b
; CHECK-NEXT:    ret
   %a = lshr <8 x i16> %x, %splat
   %b = trunc <8 x i16> %a to <8 x i8>
   ret <8 x i8> %b
 }
 
 define <8 x i8> @vnsrl_v8i16_v8i8_scalar_sext(<8 x i16> %x, i8 %y) {
 ; CHECK-LABEL: vnsrl_v8i16_v8i8_scalar_sext:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
+; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vnsrl.wx v8, v8, a0
 ; CHECK-NEXT:    ret
   %insert = insertelement <8 x i8> poison, i8 %y, i16 0
   %splat = shufflevector <8 x i8> %insert, <8 x i8> poison, <8 x i32> zeroinitializer
   %sext = sext <8 x i8> %splat to <8 x i16>
   %a = lshr <8 x i16> %x, %sext
   %b = trunc <8 x i16> %a to <8 x i8>
   ret <8 x i8> %b
 }
 
 define <8 x i8> @vnsrl_v8i16_v8i8_scalar_zext(<8 x i16> %x, i8 %y) {
 ; CHECK-LABEL: vnsrl_v8i16_v8i8_scalar_zext:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
+; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vnsrl.wx v8, v8, a0
 ; CHECK-NEXT:    ret
   %insert = insertelement <8 x i8> poison, i8 %y, i16 0
   %splat = shufflevector <8 x i8> %insert, <8 x i8> poison, <8 x i32> zeroinitializer
   %zext = zext <8 x i8> %splat to <8 x i16>
   %a = lshr <8 x i16> %x, %zext
   %b = trunc <8 x i16> %a to <8 x i8>
   ret <8 x i8> %b
; CHECK-NEXT:    ret
   %a = lshr <4 x i32> %x, %splat
   %b = trunc <4 x i32> %a to <4 x i16>
   ret <4 x i16> %b
 }
 
 define <4 x i16> @vnsrl_v4i32_v4i16_scalar_sext(<4 x i32> %x, i16 %y) {
 ; CHECK-LABEL: vnsrl_v4i32_v4i16_scalar_sext:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
+; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, mu
 ; CHECK-NEXT:    vnsrl.wx v8, v8, a0
 ; CHECK-NEXT:    ret
   %insert = insertelement <4 x i16> poison, i16 %y, i16 0
   %splat = shufflevector <4 x i16> %insert, <4 x i16> poison, <4 x i32> zeroinitializer
   %sext = sext <4 x i16> %splat to <4 x i32>
   %a = lshr <4 x i32> %x, %sext
   %b = trunc <4 x i32> %a to <4 x i16>
   ret <4 x i16> %b
 }
 
 define <4 x i16> @vnsrl_v4i32_v4i16_scalar_zext(<4 x i32> %x, i16 %y) {
 ; CHECK-LABEL: vnsrl_v4i32_v4i16_scalar_zext:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
+; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, mu
 ; CHECK-NEXT:    vnsrl.wx v8, v8, a0
 ; CHECK-NEXT:    ret
   %insert = insertelement <4 x i16> poison, i16 %y, i16 0
   %splat = shufflevector <4 x i16> %insert, <4 x i16> poison, <4 x i32> zeroinitializer
   %zext = zext <4 x i16> %splat to <4 x i32>
   %a = lshr <4 x i32> %x, %zext
   %b = trunc <4 x i32> %a to <4 x i16>
   ret <4 x i16> %b
; CHECK-NEXT:    ret
   %a = lshr <2 x i64> %x, %splat
   %b = trunc <2 x i64> %a to <2 x i32>
   ret <2 x i32> %b
 }
 
 define <2 x i32> @vnsrl_v2i64_v2i32_scalar_sext(<2 x i64> %x, i32 %y) {
 ; CHECK-LABEL: vnsrl_v2i64_v2i32_scalar_sext:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, mu
 ; CHECK-NEXT:    vnsrl.wx v8, v8, a0
 ; CHECK-NEXT:    ret
   %insert = insertelement <2 x i32> poison, i32 %y, i32 0
   %splat = shufflevector <2 x i32> %insert, <2 x i32> poison, <2 x i32> zeroinitializer
   %sext = sext <2 x i32> %splat to <2 x i64>
   %a = lshr <2 x i64> %x, %sext
   %b = trunc <2 x i64> %a to <2 x i32>
   ret <2 x i32> %b
 }
 
 define <2 x i32> @vnsrl_v2i64_v2i32_scalar_zext(<2 x i64> %x, i32 %y) {
 ; CHECK-LABEL: vnsrl_v2i64_v2i32_scalar_zext:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, mu
 ; CHECK-NEXT:    vnsrl.wx v8, v8, a0
 ; CHECK-NEXT:    ret
   %insert = insertelement <2 x i32> poison, i32 %y, i32 0
   %splat = shufflevector <2 x i32> %insert, <2 x i32> poison, <2 x i32> zeroinitializer
   %zext = zext <2 x i32> %splat to <2 x i64>
   %a = lshr <2 x i64> %x, %zext
   %b = trunc <2 x i64> %a to <2 x i32>
   ret <2 x i32> %b