[MIPS] Remove an incorrect microMIPS instruction alias

[sdardis]

Summary

The microMIPS instruction set is compatible with the MIPS instruction
set at the assembly level but not in terms of encodings. nop in
microMIPS is a special case as it has the same encoding as nop for
MIPS.

Fix this error by reducing the usage of NOP in the MIPS backend such
that only that ISA correct variants are produced.

[atanasyan]

LGTM. Thanks.

[sdardis]

Thanks for the review, I'll try to get this committed in the next few days.

llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp

static cl::opt<bool> RoundSectionSizes(
     "mips-round-section-sizes", cl::init(false),
     cl::desc("Round section sizes up to the section alignment"), cl::Hidden);
 } // end anonymous namespace
 
 static bool isMicroMips(const MCSubtargetInfo *STI) {
   return STI->getFeatureBits()[Mips::FeatureMicroMips];
 }
 
+static bool isMips32r6(const MCSubtargetInfo *STI) {
+  return STI->getFeatureBits()[Mips::FeatureMips32r6];
+}
+
 MipsTargetStreamer::MipsTargetStreamer(MCStreamer &S)
     : MCTargetStreamer(S), GPReg(Mips::GP), ModuleDirectiveAllowed(true) {
   GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
 }
 void MipsTargetStreamer::emitDirectiveSetMicroMips() {}
 void MipsTargetStreamer::emitDirectiveSetNoMicroMips() {}
 void MipsTargetStreamer::setUsesMicroMips() {}
 void MipsTargetStreamer::emitDirectiveSetMips16() {}
if (ShiftAmount >= 32) {
     return;
   }
 
   emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, STI);
 }
 
 void MipsTargetStreamer::emitEmptyDelaySlot(bool hasShortDelaySlot, SMLoc IDLoc,
                                             const MCSubtargetInfo *STI) {
-  if (hasShortDelaySlot)
-    emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, STI);
-  else
-    emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
+  // The default case of `nop` is `sll $zero, $zero, 0`.
+  unsigned Opc = Mips::SLL;
+  if (isMicroMips(STI) && hasShortDelaySlot) {
+    Opc = isMips32r6(STI) ? Mips::MOVE16_MMR6 : Mips::MOVE16_MM;
+    emitRR(Opc, Mips::ZERO, Mips::ZERO, IDLoc, STI);
+    return;
+  }
+
+  if (isMicroMips(STI))
+    Opc = isMips32r6(STI) ? Mips::SLL_MMR6 : Mips::SLL_MM;
+
+  emitRRI(Opc, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
 }
 
 void MipsTargetStreamer::emitNop(SMLoc IDLoc, const MCSubtargetInfo *STI) {
   if (isMicroMips(STI))
     emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, STI);
   else
     emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
 }

llvm/lib/Target/Mips/MicroMipsInstrInfo.td

 
 let EncodingPredicates = [InMicroMips] in {
   def SDIV_MM_Pseudo : MultDivPseudo<SDIV_MM, ACC64, GPR32Opnd, MipsDivRem,
                                      II_DIV, 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
   def UDIV_MM_Pseudo : MultDivPseudo<UDIV_MM, ACC64, GPR32Opnd, MipsDivRemU,
                                      II_DIVU, 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
 
   def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>, ISA_MICROMIPS;
-  def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>, ISA_MICROMIPS;
   def : MipsInstAlias<"nop", (SLL_MM ZERO, ZERO, 0), 1>, ISA_MICROMIPS;
   def : MipsInstAlias<"nop", (MOVE16_MM ZERO, ZERO), 1>, ISA_MICROMIPS;
   def : MipsInstAlias<"ei", (EI_MM ZERO), 1>, ISA_MICROMIPS;
   def : MipsInstAlias<"di", (DI_MM ZERO), 1>, ISA_MICROMIPS;
   def : MipsInstAlias<"neg $rt, $rs",
                       (SUB_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>,
         ISA_MICROMIPS32_NOT_MIPS32R6;
   def : MipsInstAlias<"neg $rt",

llvm/lib/Target/Mips/MipsBranchExpansion.cpp

if (!ABI.IsN64()) {
 
       if (STI->isTargetNaCl() || !hasDelaySlot) {
         BuildMI(*BalTgtMBB, std::prev(Pos), DL, TII->get(Mips::ADDiu), Mips::SP)
             .addReg(Mips::SP)
             .addImm(8);
       }
       if (hasDelaySlot) {
         if (STI->isTargetNaCl()) {
-          BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::NOP));
+          TII->insertNop(*BalTgtMBB, Pos, DL);
         } else {
           BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
               .addReg(Mips::SP)
               .addImm(8);
         }
         BalTgtMBB->rbegin()->bundleWithPred();
       }
     } else {
if (STI->hasMips32r6() && TII->isBranchOffsetInRange(Mips::BC, I.Offset)) {
           .addMBB(TgtMBB);
     } else if (SameSegmentJump) {
       // Pre R6:
       // $longbr:
       //  j $tgt
       //  nop
       // $fallthrough:
       //
-      MIBundleBuilder(*LongBrMBB, Pos)
-          .append(BuildMI(*MFp, DL, TII->get(Mips::J)).addMBB(TgtMBB))
-          .append(BuildMI(*MFp, DL, TII->get(Mips::NOP)));
+      BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::J)).addMBB(TgtMBB);
+      TII->insertNop(*LongBrMBB, Pos, DL)->bundleWithPred();
     } else {
       // At this point, offset where we need to branch does not fit into
       // immediate field of the branch instruction and is not in the same
       // segment as jump instruction. Therefore we will break it into couple
       // instructions, where we first load the offset into register, and then we
       // do branch register.
       if (ABI.IsN64()) {
         BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi2Op_64),
for (Iter I = FI->begin(); I != FI->end(); ++I) {
         IInSlot = Res.first;
       }
 
       if (LastInstInFunction || !SafeInSlot(*IInSlot, *I)) {
         MachineBasicBlock::instr_iterator Iit = I->getIterator();
         if (std::next(Iit) == FI->end() ||
             std::next(Iit)->getOpcode() != Mips::NOP) {
           Changed = true;
-          MIBundleBuilder(&*I).append(
-              BuildMI(*MFp, I->getDebugLoc(), TII->get(Mips::NOP)));
+          TII->insertNop(*(I->getParent()), std::next(I), I->getDebugLoc())
+              ->bundleWithPred();
           NumInsertedNops++;
         }
       }
     }
   }
 
   return Changed;
 }

llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp

if ((InMicroMipsMode ||
       I = replaceWithCompactBranch(MBB, I, I->getDebugLoc());
       Changed = true;
       continue;
     }
 
     // Bundle the NOP to the instruction with the delay slot.
     LLVM_DEBUG(dbgs() << DEBUG_TYPE << ": could not fill delay slot for ";
                I->dump());
-    BuildMI(MBB, std::next(I), I->getDebugLoc(), TII->get(Mips::NOP));
+    TII->insertNop(MBB, std::next(I), I->getDebugLoc());
     MIBundleBuilder(MBB, I, std::next(I, 2));
     ++FilledSlots;
     Changed = true;
   }
 
   return Changed;
 }
 

llvm/lib/Target/Mips/MipsInstrInfo.h

public:
 
   /// Predicate to determine if an instruction has a load delay slot.
   bool HasLoadDelaySlot(const MachineInstr &MI) const;
 
   /// Insert nop instruction when hazard condition is found
   void insertNoop(MachineBasicBlock &MBB,
                   MachineBasicBlock::iterator MI) const override;
 
+  /// Insert an ISA appropriate `nop`.
+  // FIXME: Add support for MIPS16e.
+  MachineInstrBuilder insertNop(MachineBasicBlock &MBB,
+                                MachineBasicBlock::iterator MI,
+                                DebugLoc DL) const;
+
   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
   /// such, whenever a client has an instance of instruction info, it should
   /// always be able to get register info as well (through this method).
   virtual const MipsRegisterInfo &getRegisterInfo() const = 0;
 
   virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0;
 
   virtual bool isBranchWithImm(unsigned Opc) const {

llvm/lib/Target/Mips/MipsInstrInfo.cpp

 /// instruction.
 void MipsInstrInfo::
 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
 {
   DebugLoc DL;
   BuildMI(MBB, MI, DL, get(Mips::NOP));
 }
 
+MachineInstrBuilder MipsInstrInfo::insertNop(MachineBasicBlock &MBB,
+                                             MachineBasicBlock::iterator MI,
+                                             DebugLoc DL) const {
+  assert(!Subtarget.inMips16Mode() &&
+         "insertNop does not support MIPS16e mode at this time");
+  const unsigned MMOpc =
+      Subtarget.hasMips32r6() ? Mips::SLL_MMR6 : Mips::SLL_MM;
+  const unsigned Opc = Subtarget.inMicroMipsMode() ? MMOpc : Mips::SLL;
+  return BuildMI(MBB, MI, DL, get(Opc), Mips::ZERO)
+      .addReg(Mips::ZERO)
+      .addImm(0);
+}
+
 MachineMemOperand *
 MipsInstrInfo::GetMemOperand(MachineBasicBlock &MBB, int FI,
                              MachineMemOperand::Flags Flags) const {
   MachineFunction &MF = *MBB.getParent();
   MachineFrameInfo &MFI = MF.getFrameInfo();
 
   return MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, FI),
                                  Flags, MFI.getObjectSize(FI),

llvm/test/CodeGen/Mips/delay-slot-filler-bundled-insts-def-use.mir

body:             |
   ; CHECK:   renamable $at = ANDi killed renamable $at, 1
   ; CHECK:   $v0_64 = DADDiu $zero_64, 1
   ; CHECK:   $v0_64 = DADDiu $v0_64, 1
   ; CHECK:   BUNDLE implicit-def $v0_64 {
   ; CHECK:     $v0_64 = DADDiu $zero_64, 1
   ; CHECK:     $v0_64 = DADDiu $v0_64, 1
   ; CHECK:   }
   ; CHECK:   BNE killed renamable $at, $zero, %bb.2, implicit-def $at {
-  ; CHECK:     NOP
+  ; CHECK:     $zero = SLL $zero, 0
   ; CHECK:   }
   ; CHECK: bb.1.return:
   ; CHECK:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
-  ; CHECK:     NOP
+  ; CHECK:     $zero = SLL $zero, 0
   ; CHECK:   }
   ; CHECK: bb.2.err:
   bb.0.entry:
     successors: %bb.1(0x00000001), %bb.2(0x7fffffff)
     liveins: $a0_64
 
     renamable $at = SLL renamable $a0, 0, implicit killed $a0_64
     renamable $at = ANDi killed renamable $at, 1

llvm/test/CodeGen/Mips/delay-slot-filler-bundled-insts.mir

body:             |
   ; CHECK:   CFI_INSTRUCTION def_cfa_offset 16
   ; CHECK:   SD killed $ra_64, $sp_64, 8 :: (store (s64) into %stack.0)
   ; CHECK:   CFI_INSTRUCTION offset $ra_64, -8
   ; CHECK:   BUNDLE {
   ; CHECK:     $sp_64 = DADDiu $sp_64, -16
   ; CHECK:     $sp_64 = DADDiu $sp_64, 16
   ; CHECK:   }
   ; CHECK:   BEQ64 renamable $a0_64, $zero_64, %bb.2, implicit-def $at {
-  ; CHECK:     NOP
+  ; CHECK:     $zero = SLL $zero, 0
   ; CHECK:   }
   ; CHECK: bb.1.if.then:
   ; CHECK:   successors: %bb.3(0x80000000)
   ; CHECK:   JAL @func_a, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit-def $sp, implicit-def $v0_64 {
-  ; CHECK:     NOP
+  ; CHECK:     $zero = SLL $zero, 0
   ; CHECK:   }
   ; CHECK:   J %bb.3, implicit-def dead $at {
-  ; CHECK:     NOP
+  ; CHECK:     $zero = SLL $zero, 0
   ; CHECK:   }
   ; CHECK: bb.2.if.else:
   ; CHECK:   successors: %bb.3(0x80000000)
   ; CHECK:   JAL @func_b, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit-def $sp, implicit-def $v0_64 {
   ; CHECK:     $a0_64 = DADDiu $zero_64, 0
   ; CHECK:   }
   ; CHECK: bb.3.return:
   ; CHECK:   $ra_64 = LD $sp_64, 8 :: (load (s64) from %stack.0)

llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir

 stack:
 constants:
 body:             |
   ; MM-LABEL: name: a
   ; MM: bb.0.entry:
   ; MM:   successors: %bb.2(0x50000000), %bb.1(0x30000000)
   ; MM:   FCMP_D32_MM killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
   ; MM:   BC1F_MM $fcc0, %bb.2, implicit-def $at {
-  ; MM:     NOP
+  ; MM:     $zero = SLL_MM $zero, 0
   ; MM:   }
   ; MM: bb.1.entry:
   ; MM:   successors: %bb.3(0x80000000)
   ; MM:   J %bb.3, implicit-def $at {
-  ; MM:     NOP
+  ; MM:     $zero = SLL_MM $zero, 0
   ; MM:   }
   ; MM: bb.2.if.then:
   ; MM:   INLINEASM &".space 310680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; MM:   $v0 = LI16_MM 0
   ; MM:   JRC16_MM undef $ra, implicit killed $v0
   ; MM: bb.3.return:
   ; MM:   $v0 = LI16_MM 1
   ; MM:   JRC16_MM undef $ra, implicit killed $v0
   ; PIC-LABEL: name: a
   ; PIC: bb.0.entry:
   ; PIC:   successors: %bb.3(0x50000000), %bb.1(0x30000000)
   ; PIC:   FCMP_D32_MM killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
   ; PIC:   BC1F_MM $fcc0, %bb.3, implicit-def $at {
-  ; PIC:     NOP
+  ; PIC:     $zero = SLL_MM $zero, 0
   ; PIC:   }
   ; PIC: bb.1.entry:
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
   ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   BAL_BR_MM %bb.2, implicit-def $ra {
   ; PIC:     $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2

 stack:
 constants:
 body:             |
   ; MM-LABEL: name: b
   ; MM: bb.0.entry:
   ; MM:   successors: %bb.2(0x30000000), %bb.1(0x50000000)
   ; MM:   FCMP_D32_MM killed renamable $d6, killed renamable $d7, 19, implicit-def $fcc0
   ; MM:   BC1F_MM killed $fcc0, %bb.1, implicit-def dead $at {
-  ; MM:     NOP
+  ; MM:     $zero = SLL_MM $zero, 0
   ; MM:   }
   ; MM: bb.1.return:
   ; MM:   $v0 = LI16_MM 1
   ; MM:   JRC16_MM undef $ra, implicit killed $v0
   ; MM: bb.2.if.then:
   ; MM:   INLINEASM &".space 310680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; MM:   $v0 = LI16_MM 0
   ; MM:   JRC16_MM undef $ra, implicit killed $v0
   ; PIC-LABEL: name: b
   ; PIC: bb.0.entry:
   ; PIC:   successors: %bb.2(0x30000000), %bb.1(0x50000000)
   ; PIC:   FCMP_D32_MM killed renamable $d6, killed renamable $d7, 19, implicit-def $fcc0
   ; PIC:   BC1F_MM killed $fcc0, %bb.1, implicit-def dead $at {
-  ; PIC:     NOP
+  ; PIC:     $zero = SLL_MM $zero, 0
   ; PIC:   }
   ; PIC: bb.1.return:
   ; PIC:   $v0 = LI16_MM 1
   ; PIC:   JRC16_MM undef $ra, implicit killed $v0
   ; PIC: bb.2.if.then:
   ; PIC:   INLINEASM &".space 310680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; PIC:   $v0 = LI16_MM 0
   ; PIC:   JRC16_MM undef $ra, implicit killed $v0

llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir

 stack:
 constants:
 body:             |
   ; MIPS-LABEL: name: a
   ; MIPS: bb.0.entry:
   ; MIPS:   successors: %bb.2(0x50000000), %bb.1(0x30000000)
   ; MIPS:   FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
   ; MIPS:   BC1F $fcc0, %bb.2, implicit-def $at {
-  ; MIPS:     NOP
+  ; MIPS:     $zero = SLL $zero, 0
   ; MIPS:   }
   ; MIPS: bb.1.entry:
   ; MIPS:   successors: %bb.3(0x80000000)
   ; MIPS:   J %bb.3, implicit-def $at {
-  ; MIPS:     NOP
+  ; MIPS:     $zero = SLL $zero, 0
   ; MIPS:   }
   ; MIPS: bb.2.if.then:
   ; MIPS:   INLINEASM &".space 310680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; MIPS:   PseudoReturn undef $ra, implicit killed $v0 {
   ; MIPS:     $v0 = ADDiu $zero, 0
   ; MIPS:   }
   ; MIPS: bb.3.return:
   ; MIPS:   PseudoReturn undef $ra, implicit killed $v0 {
   ; MIPS:     $v0 = ADDiu $zero, 1
   ; MIPS:   }
   ; PIC-LABEL: name: a
   ; PIC: bb.0.entry:
   ; PIC:   successors: %bb.3(0x50000000), %bb.1(0x30000000)
   ; PIC:   FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
   ; PIC:   BC1F $fcc0, %bb.3, implicit-def $at {
-  ; PIC:     NOP
+  ; PIC:     $zero = SLL $zero, 0
   ; PIC:   }
   ; PIC: bb.1.entry:
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
   ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   BAL_BR %bb.2, implicit-def $ra {
   ; PIC:     $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2

 stack:
 constants:
 body:             |
   ; MIPS-LABEL: name: b
   ; MIPS: bb.0.entry:
   ; MIPS:   successors: %bb.2(0x50000000), %bb.1(0x30000000)
   ; MIPS:   FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
   ; MIPS:   BC1T $fcc0, %bb.2, implicit-def $at {
-  ; MIPS:     NOP
+  ; MIPS:     $zero = SLL $zero, 0
   ; MIPS:   }
   ; MIPS: bb.1.entry:
   ; MIPS:   successors: %bb.3(0x80000000)
   ; MIPS:   J %bb.3, implicit-def $at {
-  ; MIPS:     NOP
+  ; MIPS:     $zero = SLL $zero, 0
   ; MIPS:   }
   ; MIPS: bb.2.if.then:
   ; MIPS:   INLINEASM &".space 310680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; MIPS:   PseudoReturn undef $ra, implicit killed $v0 {
   ; MIPS:     $v0 = ADDiu $zero, 0
   ; MIPS:   }
   ; MIPS: bb.3.return:
   ; MIPS:   PseudoReturn undef $ra, implicit killed $v0 {
   ; MIPS:     $v0 = ADDiu $zero, 1
   ; MIPS:   }
   ; PIC-LABEL: name: b
   ; PIC: bb.0.entry:
   ; PIC:   successors: %bb.3(0x50000000), %bb.1(0x30000000)
   ; PIC:   FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
   ; PIC:   BC1T $fcc0, %bb.3, implicit-def $at {
-  ; PIC:     NOP
+  ; PIC:     $zero = SLL $zero, 0
   ; PIC:   }
   ; PIC: bb.1.entry:
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
   ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   BAL_BR %bb.2, implicit-def $ra {
   ; PIC:     $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2

llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir

 stack:
 constants:
 body:             |
   ; R6-LABEL: name: a
   ; R6: bb.0.entry:
   ; R6:   successors: %bb.2(0x50000000), %bb.1(0x30000000)
   ; R6:   $f0 = CMP_EQ_D killed $d12_64, killed $d14_64
   ; R6:   BC1NEZ $d0_64, %bb.2 {
-  ; R6:     NOP
+  ; R6:     $zero = SLL $zero, 0
   ; R6:   }
   ; R6: bb.1.entry:
   ; R6:   successors: %bb.3(0x80000000)
   ; R6:   BC %bb.3
   ; R6: bb.2.if.then:
   ; R6:   INLINEASM &".space 310680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; R6:   PseudoReturn undef $ra, implicit killed $v0 {
   ; R6:     $v0 = ADDiu $zero, 0
   ; R6:   }
   ; R6: bb.3.return:
   ; R6:   PseudoReturn undef $ra, implicit killed $v0 {
   ; R6:     $v0 = ADDiu $zero, 1
   ; R6:   }
   ; PIC-LABEL: name: a
   ; PIC: bb.0.entry:
   ; PIC:   successors: %bb.3(0x50000000), %bb.1(0x30000000)
   ; PIC:   $f0 = CMP_EQ_D killed $d12_64, killed $d14_64
   ; PIC:   BC1NEZ $d0_64, %bb.3 {
-  ; PIC:     NOP
+  ; PIC:     $zero = SLL $zero, 0
   ; PIC:   }
   ; PIC: bb.1.entry:
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
   ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   BALC %bb.2, implicit-def $ra

 stack:
 constants:
 body:             |
   ; R6-LABEL: name: b
   ; R6: bb.0.entry:
   ; R6:   successors: %bb.2(0x50000000), %bb.1(0x30000000)
   ; R6:   $f0 = CMP_EQ_D killed $d12_64, killed $d14_64
   ; R6:   BC1EQZ $d0_64, %bb.2 {
-  ; R6:     NOP
+  ; R6:     $zero = SLL $zero, 0
   ; R6:   }
   ; R6: bb.1.entry:
   ; R6:   successors: %bb.3(0x80000000)
   ; R6:   BC %bb.3
   ; R6: bb.2.if.then:
   ; R6:   INLINEASM &".space 310680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; R6:   PseudoReturn undef $ra, implicit killed $v0 {
   ; R6:     $v0 = ADDiu $zero, 0
   ; R6:   }
   ; R6: bb.3.return:
   ; R6:   PseudoReturn undef $ra, implicit killed $v0 {
   ; R6:     $v0 = ADDiu $zero, 1
   ; R6:   }
   ; PIC-LABEL: name: b
   ; PIC: bb.0.entry:
   ; PIC:   successors: %bb.3(0x50000000), %bb.1(0x30000000)
   ; PIC:   $f0 = CMP_EQ_D killed $d12_64, killed $d14_64
   ; PIC:   BC1EQZ $d0_64, %bb.3 {
-  ; PIC:     NOP
+  ; PIC:     $zero = SLL $zero, 0
   ; PIC:   }
   ; PIC: bb.1.entry:
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
   ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   BALC %bb.2, implicit-def $ra

llvm/test/CodeGen/Mips/longbranch/branch-limits-int-microMIPS.mir

body:             |
   ; MM-LABEL: name: expand_BEQ_MM
   ; MM: bb.0 (%ir-block.0):
   ; MM:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MM:   renamable $at = ANDi killed renamable $a0, 1
   ; MM:   BNEZC_MM $at, %bb.2, implicit-def $at
   ; MM: bb.1 (%ir-block.0):
   ; MM:   successors: %bb.3(0x80000000)
   ; MM:   J %bb.3, implicit-def $at {
-  ; MM:     NOP
+  ; MM:     $zero = SLL_MM $zero, 0
   ; MM:   }
   ; MM: bb.2.iftrue:
   ; MM:   successors: %bb.3(0x80000000)
   ; MM:   INLINEASM &".space 131068", 1
   ; MM: bb.3.tail:
   ; MM:   JRC16_MM undef $ra
   ; PIC-LABEL: name: expand_BEQ_MM
   ; PIC: bb.0 (%ir-block.0):

 stack:
 constants:
 body:             |
   ; MM-LABEL: name: expand_BGEZ_MM
   ; MM: bb.0 (%ir-block.0):
   ; MM:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MM:   renamable $at = ANDi killed renamable $a0, 1
   ; MM:   BLTZ_MM $at, %bb.2, implicit-def $at {
-  ; MM:     NOP
+  ; MM:     $zero = SLL_MM $zero, 0
   ; MM:   }
   ; MM: bb.1 (%ir-block.0):
   ; MM:   successors: %bb.3(0x80000000)
   ; MM:   J %bb.3, implicit-def $at {
-  ; MM:     NOP
+  ; MM:     $zero = SLL_MM $zero, 0
   ; MM:   }
   ; MM: bb.2.iftrue:
   ; MM:   successors: %bb.3(0x80000000)
   ; MM:   INLINEASM &".space 131068", 1
   ; MM: bb.3.tail:
   ; MM:   JRC16_MM undef $ra
   ; PIC-LABEL: name: expand_BGEZ_MM
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BLTZ_MM $at, %bb.3, implicit-def $at {
-  ; PIC:     NOP
+  ; PIC:     $zero = SLL_MM $zero, 0
   ; PIC:   }
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
   ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   BAL_BR_MM %bb.2, implicit-def $ra {
   ; PIC:     $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2

 stack:
 constants:
 body:             |
   ; MM-LABEL: name: expand_BGTZ_MM
   ; MM: bb.0 (%ir-block.0):
   ; MM:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MM:   renamable $at = ANDi killed renamable $a0, 1
   ; MM:   BLEZ_MM $at, %bb.2, implicit-def $at {
-  ; MM:     NOP
+  ; MM:     $zero = SLL_MM $zero, 0
   ; MM:   }
   ; MM: bb.1 (%ir-block.0):
   ; MM:   successors: %bb.3(0x80000000)
   ; MM:   J %bb.3, implicit-def $at {
-  ; MM:     NOP
+  ; MM:     $zero = SLL_MM $zero, 0
   ; MM:   }
   ; MM: bb.2.iftrue:
   ; MM:   successors: %bb.3(0x80000000)
   ; MM:   INLINEASM &".space 131068", 1
   ; MM: bb.3.tail:
   ; MM:   JRC16_MM undef $ra
   ; PIC-LABEL: name: expand_BGTZ_MM
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BLEZ_MM $at, %bb.3, implicit-def $at {
-  ; PIC:     NOP
+  ; PIC:     $zero = SLL_MM $zero, 0
   ; PIC:   }
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
   ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   BAL_BR_MM %bb.2, implicit-def $ra {
   ; PIC:     $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2

 stack:
 constants:
 body:             |
   ; MM-LABEL: name: expand_BLEZ_MM
   ; MM: bb.0 (%ir-block.0):
   ; MM:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MM:   renamable $at = ANDi killed renamable $a0, 1
   ; MM:   BGTZ_MM $at, %bb.2, implicit-def $at {
-  ; MM:     NOP
+  ; MM:     $zero = SLL_MM $zero, 0
   ; MM:   }
   ; MM: bb.1 (%ir-block.0):
   ; MM:   successors: %bb.3(0x80000000)
   ; MM:   J %bb.3, implicit-def $at {
-  ; MM:     NOP
+  ; MM:     $zero = SLL_MM $zero, 0
   ; MM:   }
   ; MM: bb.2.iftrue:
   ; MM:   successors: %bb.3(0x80000000)
   ; MM:   INLINEASM &".space 131068", 1
   ; MM: bb.3.tail:
   ; MM:   JRC16_MM undef $ra
   ; PIC-LABEL: name: expand_BLEZ_MM
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BGTZ_MM $at, %bb.3, implicit-def $at {
-  ; PIC:     NOP
+  ; PIC:     $zero = SLL_MM $zero, 0
   ; PIC:   }
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
   ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   BAL_BR_MM %bb.2, implicit-def $ra {
   ; PIC:     $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2

 stack:
 constants:
 body:             |
   ; MM-LABEL: name: expand_BLTZ_MM
   ; MM: bb.0 (%ir-block.0):
   ; MM:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MM:   renamable $at = ANDi killed renamable $a0, 1
   ; MM:   BGEZ_MM $at, %bb.2, implicit-def $at {
-  ; MM:     NOP
+  ; MM:     $zero = SLL_MM $zero, 0
   ; MM:   }
   ; MM: bb.1 (%ir-block.0):
   ; MM:   successors: %bb.3(0x80000000)
   ; MM:   J %bb.3, implicit-def $at {
-  ; MM:     NOP
+  ; MM:     $zero = SLL_MM $zero, 0
   ; MM:   }
   ; MM: bb.2.iftrue:
   ; MM:   successors: %bb.3(0x80000000)
   ; MM:   INLINEASM &".space 131068", 1
   ; MM: bb.3.tail:
   ; MM:   JRC16_MM undef $ra
   ; PIC-LABEL: name: expand_BLTZ_MM
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BGEZ_MM $at, %bb.3, implicit-def $at {
-  ; PIC:     NOP
+  ; PIC:     $zero = SLL_MM $zero, 0
   ; PIC:   }
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
   ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   BAL_BR_MM %bb.2, implicit-def $ra {
   ; PIC:     $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
body:             |
   ; MM-LABEL: name: expand_BNE_MM
   ; MM: bb.0 (%ir-block.0):
   ; MM:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MM:   renamable $at = ANDi killed renamable $a0, 1
   ; MM:   BEQZC_MM $at, %bb.2, implicit-def $at
   ; MM: bb.1 (%ir-block.0):
   ; MM:   successors: %bb.3(0x80000000)
   ; MM:   J %bb.3, implicit-def $at {
-  ; MM:     NOP
+  ; MM:     $zero = SLL_MM $zero, 0
   ; MM:   }
   ; MM: bb.2.iftrue:
   ; MM:   successors: %bb.3(0x80000000)
   ; MM:   INLINEASM &".space 131068", 1
   ; MM: bb.3.tail:
   ; MM:   JRC16_MM undef $ra
   ; PIC-LABEL: name: expand_BNE_MM
   ; PIC: bb.0 (%ir-block.0):

 stack:
 constants:
 body:             |
   ; MM-LABEL: name: expand_BEQZ16_MM
   ; MM: bb.0 (%ir-block.0):
   ; MM:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MM:   renamable $v0 = ANDi killed renamable $a0, 1
   ; MM:   BNEZ16_MM $v0, %bb.2, implicit-def $at {
-  ; MM:     NOP
+  ; MM:     $zero = SLL_MM $zero, 0
   ; MM:   }
   ; MM: bb.1 (%ir-block.0):
   ; MM:   successors: %bb.3(0x80000000)
   ; MM:   J %bb.3, implicit-def $at {
-  ; MM:     NOP
+  ; MM:     $zero = SLL_MM $zero, 0
   ; MM:   }
   ; MM: bb.2.iftrue:
   ; MM:   successors: %bb.3(0x80000000)
   ; MM:   INLINEASM &".space 131068", 1
   ; MM: bb.3.tail:
   ; MM:   JRC16_MM undef $ra
   ; PIC-LABEL: name: expand_BEQZ16_MM
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $v0 = ANDi killed renamable $a0, 1
   ; PIC:   BNEZ16_MM $v0, %bb.3, implicit-def $at {
-  ; PIC:     NOP
+  ; PIC:     $zero = SLL_MM $zero, 0
   ; PIC:   }
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
   ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   BAL_BR_MM %bb.2, implicit-def $ra {
   ; PIC:     $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2

 stack:
 constants:
 body:             |
   ; MM-LABEL: name: expand_BNEZ16_MM
   ; MM: bb.0 (%ir-block.0):
   ; MM:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MM:   renamable $v0 = ANDi killed renamable $a0, 1
   ; MM:   BEQZ16_MM $v0, %bb.2, implicit-def $at {
-  ; MM:     NOP
+  ; MM:     $zero = SLL_MM $zero, 0
   ; MM:   }
   ; MM: bb.1 (%ir-block.0):
   ; MM:   successors: %bb.3(0x80000000)
   ; MM:   J %bb.3, implicit-def $at {
-  ; MM:     NOP
+  ; MM:     $zero = SLL_MM $zero, 0
   ; MM:   }
   ; MM: bb.2.iftrue:
   ; MM:   successors: %bb.3(0x80000000)
   ; MM:   INLINEASM &".space 131068", 1
   ; MM: bb.3.tail:
   ; MM:   JRC16_MM undef $ra
   ; PIC-LABEL: name: expand_BNEZ16_MM
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $v0 = ANDi killed renamable $a0, 1
   ; PIC:   BEQZ16_MM $v0, %bb.3, implicit-def $at {
-  ; PIC:     NOP
+  ; PIC:     $zero = SLL_MM $zero, 0
   ; PIC:   }
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
   ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   BAL_BR_MM %bb.2, implicit-def $ra {
   ; PIC:     $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2

llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64.mir

 fixedStack:
 stack:
 constants:
 body:             |
   ; MIPS64-LABEL: name: expand_BEQ64
   ; MIPS64: bb.0 (%ir-block.0):
   ; MIPS64:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MIPS64:   BNE64 $a0_64, $zero_64, %bb.2, implicit-def $at {
-  ; MIPS64:     NOP
+  ; MIPS64:     $zero = SLL $zero, 0
   ; MIPS64:   }
   ; MIPS64: bb.1 (%ir-block.0):
   ; MIPS64:   successors: %bb.3(0x80000000)
   ; MIPS64:   J %bb.3, implicit-def $at {
-  ; MIPS64:     NOP
+  ; MIPS64:     $zero = SLL $zero, 0
   ; MIPS64:   }
   ; MIPS64: bb.2.iftrue:
   ; MIPS64:   INLINEASM &".space 131068", 1
   ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
   ; MIPS64:     $v0_64 = DADDiu $zero_64, 1
   ; MIPS64:   }
   ; MIPS64: bb.3.tail:
   ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
   ; MIPS64:     $v0_64 = DADDiu $zero_64, 0
   ; MIPS64:   }
   ; PIC-LABEL: name: expand_BEQ64
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   BNE64 $a0_64, $zero_64, %bb.3, implicit-def $at {
-  ; PIC:     NOP
+  ; PIC:     $zero = SLL $zero, 0
   ; PIC:   }
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp_64 = DADDiu $sp_64, -16
   ; PIC:   SD $ra_64, $sp_64, 0
   ; PIC:   $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   $at_64 = DSLL $at_64, 16
   ; PIC:   BAL_BR %bb.2, implicit-def $ra {

 fixedStack:
 stack:
 constants:
 body:             |
   ; MIPS64-LABEL: name: expand_BNE64
   ; MIPS64: bb.0 (%ir-block.0):
   ; MIPS64:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MIPS64:   BEQ64 $a0_64, $zero_64, %bb.2, implicit-def $at {
-  ; MIPS64:     NOP
+  ; MIPS64:     $zero = SLL $zero, 0
   ; MIPS64:   }
   ; MIPS64: bb.1 (%ir-block.0):
   ; MIPS64:   successors: %bb.3(0x80000000)
   ; MIPS64:   J %bb.3, implicit-def $at {
-  ; MIPS64:     NOP
+  ; MIPS64:     $zero = SLL $zero, 0
   ; MIPS64:   }
   ; MIPS64: bb.2.iftrue:
   ; MIPS64:   INLINEASM &".space 131068", 1
   ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
   ; MIPS64:     $v0_64 = DADDiu $zero_64, 1
   ; MIPS64:   }
   ; MIPS64: bb.3.tail:
   ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
   ; MIPS64:     $v0_64 = DADDiu $zero_64, 0
   ; MIPS64:   }
   ; PIC-LABEL: name: expand_BNE64
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   BEQ64 $a0_64, $zero_64, %bb.3, implicit-def $at {
-  ; PIC:     NOP
+  ; PIC:     $zero = SLL $zero, 0
   ; PIC:   }
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp_64 = DADDiu $sp_64, -16
   ; PIC:   SD $ra_64, $sp_64, 0
   ; PIC:   $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   $at_64 = DSLL $at_64, 16
   ; PIC:   BAL_BR %bb.2, implicit-def $ra {

 fixedStack:
 stack:
 constants:
 body:             |
   ; MIPS64-LABEL: name: expand_BGEZ64
   ; MIPS64: bb.0 (%ir-block.0):
   ; MIPS64:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MIPS64:   BLTZ64 $a0_64, %bb.2, implicit-def $at {
-  ; MIPS64:     NOP
+  ; MIPS64:     $zero = SLL $zero, 0
   ; MIPS64:   }
   ; MIPS64: bb.1 (%ir-block.0):
   ; MIPS64:   successors: %bb.3(0x80000000)
   ; MIPS64:   J %bb.3, implicit-def $at {
-  ; MIPS64:     NOP
+  ; MIPS64:     $zero = SLL $zero, 0
   ; MIPS64:   }
   ; MIPS64: bb.2.iftrue:
   ; MIPS64:   INLINEASM &".space 131068", 1
   ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
   ; MIPS64:     $v0_64 = DADDiu $zero_64, 1
   ; MIPS64:   }
   ; MIPS64: bb.3.tail:
   ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
   ; MIPS64:     $v0_64 = DADDiu $zero_64, 0
   ; MIPS64:   }
   ; PIC-LABEL: name: expand_BGEZ64
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   BLTZ64 $a0_64, %bb.3, implicit-def $at {
-  ; PIC:     NOP
+  ; PIC:     $zero = SLL $zero, 0
   ; PIC:   }
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp_64 = DADDiu $sp_64, -16
   ; PIC:   SD $ra_64, $sp_64, 0
   ; PIC:   $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   $at_64 = DSLL $at_64, 16
   ; PIC:   BAL_BR %bb.2, implicit-def $ra {

 fixedStack:
 stack:
 constants:
 body:             |
   ; MIPS64-LABEL: name: expand_BGTZ64
   ; MIPS64: bb.0 (%ir-block.0):
   ; MIPS64:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MIPS64:   BLEZ64 $a0_64, %bb.2, implicit-def $at {
-  ; MIPS64:     NOP
+  ; MIPS64:     $zero = SLL $zero, 0
   ; MIPS64:   }
   ; MIPS64: bb.1 (%ir-block.0):
   ; MIPS64:   successors: %bb.3(0x80000000)
   ; MIPS64:   J %bb.3, implicit-def $at {
-  ; MIPS64:     NOP
+  ; MIPS64:     $zero = SLL $zero, 0
   ; MIPS64:   }
   ; MIPS64: bb.2.iftrue:
   ; MIPS64:   INLINEASM &".space 131068", 1
   ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
   ; MIPS64:     $v0_64 = DADDiu $zero_64, 1
   ; MIPS64:   }
   ; MIPS64: bb.3.tail:
   ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
   ; MIPS64:     $v0_64 = DADDiu $zero_64, 0
   ; MIPS64:   }
   ; PIC-LABEL: name: expand_BGTZ64
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   BLEZ64 $a0_64, %bb.3, implicit-def $at {
-  ; PIC:     NOP
+  ; PIC:     $zero = SLL $zero, 0
   ; PIC:   }
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp_64 = DADDiu $sp_64, -16
   ; PIC:   SD $ra_64, $sp_64, 0
   ; PIC:   $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   $at_64 = DSLL $at_64, 16
   ; PIC:   BAL_BR %bb.2, implicit-def $ra {

 fixedStack:
 stack:
 constants:
 body:             |
   ; MIPS64-LABEL: name: expand_BLEZ64
   ; MIPS64: bb.0 (%ir-block.0):
   ; MIPS64:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MIPS64:   BGTZ64 $a0_64, %bb.2, implicit-def $at {
-  ; MIPS64:     NOP
+  ; MIPS64:     $zero = SLL $zero, 0
   ; MIPS64:   }
   ; MIPS64: bb.1 (%ir-block.0):
   ; MIPS64:   successors: %bb.3(0x80000000)
   ; MIPS64:   J %bb.3, implicit-def $at {
-  ; MIPS64:     NOP
+  ; MIPS64:     $zero = SLL $zero, 0
   ; MIPS64:   }
   ; MIPS64: bb.2.iftrue:
   ; MIPS64:   INLINEASM &".space 131068", 1
   ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
   ; MIPS64:     $v0_64 = DADDiu $zero_64, 1
   ; MIPS64:   }
   ; MIPS64: bb.3.tail:
   ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
   ; MIPS64:     $v0_64 = DADDiu $zero_64, 0
   ; MIPS64:   }
   ; PIC-LABEL: name: expand_BLEZ64
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   BGTZ64 $a0_64, %bb.3, implicit-def $at {
-  ; PIC:     NOP
+  ; PIC:     $zero = SLL $zero, 0
   ; PIC:   }
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp_64 = DADDiu $sp_64, -16
   ; PIC:   SD $ra_64, $sp_64, 0
   ; PIC:   $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   $at_64 = DSLL $at_64, 16
   ; PIC:   BAL_BR %bb.2, implicit-def $ra {

 fixedStack:
 stack:
 constants:
 body:             |
   ; MIPS64-LABEL: name: expand_BLTZ64
   ; MIPS64: bb.0 (%ir-block.0):
   ; MIPS64:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MIPS64:   BGEZ64 $a0_64, %bb.2, implicit-def $at {
-  ; MIPS64:     NOP
+  ; MIPS64:     $zero = SLL $zero, 0
   ; MIPS64:   }
   ; MIPS64: bb.1 (%ir-block.0):
   ; MIPS64:   successors: %bb.3(0x80000000)
   ; MIPS64:   J %bb.3, implicit-def $at {
-  ; MIPS64:     NOP
+  ; MIPS64:     $zero = SLL $zero, 0
   ; MIPS64:   }
   ; MIPS64: bb.2.iftrue:
   ; MIPS64:   INLINEASM &".space 131068", 1
   ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
   ; MIPS64:     $v0_64 = DADDiu $zero_64, 1
   ; MIPS64:   }
   ; MIPS64: bb.3.tail:
   ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
   ; MIPS64:     $v0_64 = DADDiu $zero_64, 0
   ; MIPS64:   }
   ; PIC-LABEL: name: expand_BLTZ64
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   BGEZ64 $a0_64, %bb.3, implicit-def $at {
-  ; PIC:     NOP
+  ; PIC:     $zero = SLL $zero, 0
   ; PIC:   }
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp_64 = DADDiu $sp_64, -16
   ; PIC:   SD $ra_64, $sp_64, 0
   ; PIC:   $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   $at_64 = DSLL $at_64, 16
   ; PIC:   BAL_BR %bb.2, implicit-def $ra {

llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64r6.mir

 body:             |
   ; MIPS64-LABEL: name: expand_BNEC64
   ; MIPS64: bb.0 (%ir-block.0):
   ; MIPS64:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MIPS64:   BEQC64 $a0_64, $zero_64, %bb.2, implicit-def $at
   ; MIPS64: bb.1 (%ir-block.0):
   ; MIPS64:   successors: %bb.3(0x80000000)
   ; MIPS64:   J %bb.3, implicit-def $at {
-  ; MIPS64:     NOP
+  ; MIPS64:     $zero = SLL $zero, 0
   ; MIPS64:   }
   ; MIPS64: bb.2.iftrue:
   ; MIPS64:   INLINEASM &".space 831068", 1
   ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
   ; MIPS64:     $v0_64 = DADDiu $zero_64, 1
   ; MIPS64:   }
   ; MIPS64: bb.3.tail:
   ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {

 body:             |
   ; MIPS64-LABEL: name: expand_BEQC64
   ; MIPS64: bb.0 (%ir-block.0):
   ; MIPS64:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MIPS64:   BNEC64 $a0_64, $zero_64, %bb.2, implicit-def $at
   ; MIPS64: bb.1 (%ir-block.0):
   ; MIPS64:   successors: %bb.3(0x80000000)
   ; MIPS64:   J %bb.3, implicit-def $at {
-  ; MIPS64:     NOP
+  ; MIPS64:     $zero = SLL $zero, 0
   ; MIPS64:   }
   ; MIPS64: bb.2.iftrue:
   ; MIPS64:   INLINEASM &".space 831068", 1
   ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
   ; MIPS64:     $v0_64 = DADDiu $zero_64, 1
   ; MIPS64:   }
   ; MIPS64: bb.3.tail:
   ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {

 body:             |
   ; MIPS64-LABEL: name: expand_BLTC64
   ; MIPS64: bb.0 (%ir-block.0):
   ; MIPS64:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MIPS64:   BGEC64 $a0_64, $zero_64, %bb.2, implicit-def $at
   ; MIPS64: bb.1 (%ir-block.0):
   ; MIPS64:   successors: %bb.3(0x80000000)
   ; MIPS64:   J %bb.3, implicit-def $at {
-  ; MIPS64:     NOP
+  ; MIPS64:     $zero = SLL $zero, 0
   ; MIPS64:   }
   ; MIPS64: bb.2.iftrue:
   ; MIPS64:   INLINEASM &".space 831068", 1
   ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
   ; MIPS64:     $v0_64 = DADDiu $zero_64, 1
   ; MIPS64:   }
   ; MIPS64: bb.3.tail:
   ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {

 body:             |
   ; MIPS64-LABEL: name: expand_BLTUC64
   ; MIPS64: bb.0 (%ir-block.0):
   ; MIPS64:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MIPS64:   BGEUC64 $a0_64, $zero_64, %bb.2, implicit-def $at
   ; MIPS64: bb.1 (%ir-block.0):
   ; MIPS64:   successors: %bb.3(0x80000000)
   ; MIPS64:   J %bb.3, implicit-def $at {
-  ; MIPS64:     NOP
+  ; MIPS64:     $zero = SLL $zero, 0
   ; MIPS64:   }
   ; MIPS64: bb.2.iftrue:
   ; MIPS64:   INLINEASM &".space 831068", 1
   ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
   ; MIPS64:     $v0_64 = DADDiu $zero_64, 1
   ; MIPS64:   }
   ; MIPS64: bb.3.tail:
   ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {

 body:             |
   ; MIPS64-LABEL: name: expand_BGEC64
   ; MIPS64: bb.0 (%ir-block.0):
   ; MIPS64:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MIPS64:   BLTC64 $a0_64, $zero_64, %bb.2, implicit-def $at
   ; MIPS64: bb.1 (%ir-block.0):
   ; MIPS64:   successors: %bb.3(0x80000000)
   ; MIPS64:   J %bb.3, implicit-def $at {
-  ; MIPS64:     NOP
+  ; MIPS64:     $zero = SLL $zero, 0
   ; MIPS64:   }
   ; MIPS64: bb.2.iftrue:
   ; MIPS64:   INLINEASM &".space 831068", 1
   ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
   ; MIPS64:     $v0_64 = DADDiu $zero_64, 1
   ; MIPS64:   }
   ; MIPS64: bb.3.tail:
   ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {

 body:             |
   ; MIPS64-LABEL: name: expand_BGEUC64
   ; MIPS64: bb.0 (%ir-block.0):
   ; MIPS64:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MIPS64:   BLTUC64 $a0_64, $zero_64, %bb.2, implicit-def $at
   ; MIPS64: bb.1 (%ir-block.0):
   ; MIPS64:   successors: %bb.3(0x80000000)
   ; MIPS64:   J %bb.3, implicit-def $at {
-  ; MIPS64:     NOP
+  ; MIPS64:     $zero = SLL $zero, 0
   ; MIPS64:   }
   ; MIPS64: bb.2.iftrue:
   ; MIPS64:   INLINEASM &".space 831068", 1
   ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
   ; MIPS64:     $v0_64 = DADDiu $zero_64, 1
   ; MIPS64:   }
   ; MIPS64: bb.3.tail:
   ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {

 body:             |
   ; MIPS64-LABEL: name: expand_BLEZC64
   ; MIPS64: bb.0 (%ir-block.0):
   ; MIPS64:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MIPS64:   BGTZC64 $a0_64, %bb.2, implicit-def $at
   ; MIPS64: bb.1 (%ir-block.0):
   ; MIPS64:   successors: %bb.3(0x80000000)
   ; MIPS64:   J %bb.3, implicit-def $at {
-  ; MIPS64:     NOP
+  ; MIPS64:     $zero = SLL $zero, 0
   ; MIPS64:   }
   ; MIPS64: bb.2.iftrue:
   ; MIPS64:   INLINEASM &".space 831068", 1
   ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
   ; MIPS64:     $v0_64 = DADDiu $zero_64, 1
   ; MIPS64:   }
   ; MIPS64: bb.3.tail:
   ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {

 body:             |
   ; MIPS64-LABEL: name: expand_BLTZC64
   ; MIPS64: bb.0 (%ir-block.0):
   ; MIPS64:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MIPS64:   BGEZC64 $a0_64, %bb.2, implicit-def $at
   ; MIPS64: bb.1 (%ir-block.0):
   ; MIPS64:   successors: %bb.3(0x80000000)
   ; MIPS64:   J %bb.3, implicit-def $at {
-  ; MIPS64:     NOP
+  ; MIPS64:     $zero = SLL $zero, 0
   ; MIPS64:   }
   ; MIPS64: bb.2.iftrue:
   ; MIPS64:   INLINEASM &".space 831068", 1
   ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
   ; MIPS64:     $v0_64 = DADDiu $zero_64, 1
   ; MIPS64:   }
   ; MIPS64: bb.3.tail:
   ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {

 body:             |
   ; MIPS64-LABEL: name: expand_BGEZC64
   ; MIPS64: bb.0 (%ir-block.0):
   ; MIPS64:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MIPS64:   BLTZC64 $a0_64, %bb.2, implicit-def $at
   ; MIPS64: bb.1 (%ir-block.0):
   ; MIPS64:   successors: %bb.3(0x80000000)
   ; MIPS64:   J %bb.3, implicit-def $at {
-  ; MIPS64:     NOP
+  ; MIPS64:     $zero = SLL $zero, 0
   ; MIPS64:   }
   ; MIPS64: bb.2.iftrue:
   ; MIPS64:   INLINEASM &".space 831068", 1
   ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
   ; MIPS64:     $v0_64 = DADDiu $zero_64, 1
   ; MIPS64:   }
   ; MIPS64: bb.3.tail:
   ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {

 body:             |
   ; MIPS64-LABEL: name: expand_BGTZC64
   ; MIPS64: bb.0 (%ir-block.0):
   ; MIPS64:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MIPS64:   BLEZC64 $a0_64, %bb.2, implicit-def $at
   ; MIPS64: bb.1 (%ir-block.0):
   ; MIPS64:   successors: %bb.3(0x80000000)
   ; MIPS64:   J %bb.3, implicit-def $at {
-  ; MIPS64:     NOP
+  ; MIPS64:     $zero = SLL $zero, 0
   ; MIPS64:   }
   ; MIPS64: bb.2.iftrue:
   ; MIPS64:   INLINEASM &".space 831068", 1
   ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
   ; MIPS64:     $v0_64 = DADDiu $zero_64, 1
   ; MIPS64:   }
   ; MIPS64: bb.3.tail:
   ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {

llvm/test/CodeGen/Mips/longbranch/branch-limits-int.mir

 stack:
 constants:
 body:             |
   ; MIPS-LABEL: name: expand_BEQ
   ; MIPS: bb.0 (%ir-block.0):
   ; MIPS:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MIPS:   renamable $at = ANDi killed renamable $a0, 1
   ; MIPS:   BNE $at, $zero, %bb.2, implicit-def $at {
-  ; MIPS:     NOP
+  ; MIPS:     $zero = SLL $zero, 0
   ; MIPS:   }
   ; MIPS: bb.1 (%ir-block.0):
   ; MIPS:   successors: %bb.3(0x80000000)
   ; MIPS:   J %bb.3, implicit-def $at {
-  ; MIPS:     NOP
+  ; MIPS:     $zero = SLL $zero, 0
   ; MIPS:   }
   ; MIPS: bb.2.iftrue:
   ; MIPS:   successors: %bb.3(0x80000000)
   ; MIPS:   INLINEASM &".space 131068", 1
   ; MIPS: bb.3.tail:
   ; MIPS:   PseudoReturn undef $ra {
-  ; MIPS:     NOP
+  ; MIPS:     $zero = SLL $zero, 0
   ; MIPS:   }
   ; PIC-LABEL: name: expand_BEQ
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BNE $at, $zero, %bb.3, implicit-def $at {
-  ; PIC:     NOP
+  ; PIC:     $zero = SLL $zero, 0
   ; PIC:   }
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
   ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   BAL_BR %bb.2, implicit-def $ra {
   ; PIC:     $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   }
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   JR $at {
   ; PIC:     $sp = ADDiu $sp, 8
   ; PIC:   }
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 131068", 1
   ; PIC: bb.4.tail:
   ; PIC:   PseudoReturn undef $ra {
-  ; PIC:     NOP
+  ; PIC:     $zero = SLL $zero, 0
   ; PIC:   }
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $at = ANDi killed renamable $a0, 1
     BEQ killed renamable $at, $zero, %bb.2, implicit-def $at
 

 stack:
 constants:
 body:             |
   ; MIPS-LABEL: name: expand_BGEZ
   ; MIPS: bb.0 (%ir-block.0):
   ; MIPS:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MIPS:   renamable $at = ANDi killed renamable $a0, 1
   ; MIPS:   BLTZ $at, %bb.2, implicit-def $at {
-  ; MIPS:     NOP
+  ; MIPS:     $zero = SLL $zero, 0
   ; MIPS:   }
   ; MIPS: bb.1 (%ir-block.0):
   ; MIPS:   successors: %bb.3(0x80000000)
   ; MIPS:   J %bb.3, implicit-def $at {
-  ; MIPS:     NOP
+  ; MIPS:     $zero = SLL $zero, 0
   ; MIPS:   }
   ; MIPS: bb.2.iftrue:
   ; MIPS:   successors: %bb.3(0x80000000)
   ; MIPS:   INLINEASM &".space 131068", 1
   ; MIPS: bb.3.tail:
   ; MIPS:   PseudoReturn undef $ra {
-  ; MIPS:     NOP
+  ; MIPS:     $zero = SLL $zero, 0
   ; MIPS:   }
   ; PIC-LABEL: name: expand_BGEZ
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BLTZ $at, %bb.3, implicit-def $at {
-  ; PIC:     NOP
+  ; PIC:     $zero = SLL $zero, 0
   ; PIC:   }
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
   ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   BAL_BR %bb.2, implicit-def $ra {
   ; PIC:     $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   }
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   JR $at {
   ; PIC:     $sp = ADDiu $sp, 8
   ; PIC:   }
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 131068", 1
   ; PIC: bb.4.tail:
   ; PIC:   PseudoReturn undef $ra {
-  ; PIC:     NOP
+  ; PIC:     $zero = SLL $zero, 0
   ; PIC:   }
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $at = ANDi killed renamable $a0, 1
     BGEZ killed renamable $at, %bb.2, implicit-def $at
 

 stack:
 constants:
 body:             |
   ; MIPS-LABEL: name: expand_BGTZ
   ; MIPS: bb.0 (%ir-block.0):
   ; MIPS:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MIPS:   renamable $at = ANDi killed renamable $a0, 1
   ; MIPS:   BLEZ $at, %bb.2, implicit-def $at {
-  ; MIPS:     NOP
+  ; MIPS:     $zero = SLL $zero, 0
   ; MIPS:   }
   ; MIPS: bb.1 (%ir-block.0):
   ; MIPS:   successors: %bb.3(0x80000000)
   ; MIPS:   J %bb.3, implicit-def $at {
-  ; MIPS:     NOP
+  ; MIPS:     $zero = SLL $zero, 0
   ; MIPS:   }
   ; MIPS: bb.2.iftrue:
   ; MIPS:   successors: %bb.3(0x80000000)
   ; MIPS:   INLINEASM &".space 131068", 1
   ; MIPS: bb.3.tail:
   ; MIPS:   PseudoReturn undef $ra {
-  ; MIPS:     NOP
+  ; MIPS:     $zero = SLL $zero, 0
   ; MIPS:   }
   ; PIC-LABEL: name: expand_BGTZ
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BLEZ $at, %bb.3, implicit-def $at {
-  ; PIC:     NOP
+  ; PIC:     $zero = SLL $zero, 0
   ; PIC:   }
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
   ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   BAL_BR %bb.2, implicit-def $ra {
   ; PIC:     $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   }
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   JR $at {
   ; PIC:     $sp = ADDiu $sp, 8
   ; PIC:   }
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 131068", 1
   ; PIC: bb.4.tail:
   ; PIC:   PseudoReturn undef $ra {
-  ; PIC:     NOP
+  ; PIC:     $zero = SLL $zero, 0
   ; PIC:   }
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $at = ANDi killed renamable $a0, 1
     BGTZ killed renamable $at, %bb.2, implicit-def $at
 

 stack:
 constants:
 body:             |
   ; MIPS-LABEL: name: expand_BLEZ
   ; MIPS: bb.0 (%ir-block.0):
   ; MIPS:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MIPS:   renamable $at = ANDi killed renamable $a0, 1
   ; MIPS:   BGTZ $at, %bb.2, implicit-def $at {
-  ; MIPS:     NOP
+  ; MIPS:     $zero = SLL $zero, 0
   ; MIPS:   }
   ; MIPS: bb.1 (%ir-block.0):
   ; MIPS:   successors: %bb.3(0x80000000)
   ; MIPS:   J %bb.3, implicit-def $at {
-  ; MIPS:     NOP
+  ; MIPS:     $zero = SLL $zero, 0
   ; MIPS:   }
   ; MIPS: bb.2.iftrue:
   ; MIPS:   successors: %bb.3(0x80000000)
   ; MIPS:   INLINEASM &".space 131068", 1
   ; MIPS: bb.3.tail:
   ; MIPS:   PseudoReturn undef $ra {
-  ; MIPS:     NOP
+  ; MIPS:     $zero = SLL $zero, 0
   ; MIPS:   }
   ; PIC-LABEL: name: expand_BLEZ
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BGTZ $at, %bb.3, implicit-def $at {
-  ; PIC:     NOP
+  ; PIC:     $zero = SLL $zero, 0
   ; PIC:   }
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
   ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   BAL_BR %bb.2, implicit-def $ra {
   ; PIC:     $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   }
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   JR $at {
   ; PIC:     $sp = ADDiu $sp, 8
   ; PIC:   }
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 131068", 1
   ; PIC: bb.4.tail:
   ; PIC:   PseudoReturn undef $ra {
-  ; PIC:     NOP
+  ; PIC:     $zero = SLL $zero, 0
   ; PIC:   }
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $at = ANDi killed renamable $a0, 1
     BLEZ killed renamable $at, %bb.2, implicit-def $at
 

 stack:
 constants:
 body:             |
   ; MIPS-LABEL: name: expand_BLTZ
   ; MIPS: bb.0 (%ir-block.0):
   ; MIPS:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MIPS:   renamable $at = ANDi killed renamable $a0, 1
   ; MIPS:   BGEZ $at, %bb.2, implicit-def $at {
-  ; MIPS:     NOP
+  ; MIPS:     $zero = SLL $zero, 0
   ; MIPS:   }
   ; MIPS: bb.1 (%ir-block.0):
   ; MIPS:   successors: %bb.3(0x80000000)
   ; MIPS:   J %bb.3, implicit-def $at {
-  ; MIPS:     NOP
+  ; MIPS:     $zero = SLL $zero, 0
   ; MIPS:   }
   ; MIPS: bb.2.iftrue:
   ; MIPS:   successors: %bb.3(0x80000000)
   ; MIPS:   INLINEASM &".space 131068", 1
   ; MIPS: bb.3.tail:
   ; MIPS:   PseudoReturn undef $ra {
-  ; MIPS:     NOP
+  ; MIPS:     $zero = SLL $zero, 0
   ; MIPS:   }
   ; PIC-LABEL: name: expand_BLTZ
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BGEZ $at, %bb.3, implicit-def $at {
-  ; PIC:     NOP
+  ; PIC:     $zero = SLL $zero, 0
   ; PIC:   }
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
   ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   BAL_BR %bb.2, implicit-def $ra {
   ; PIC:     $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   }
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   JR $at {
   ; PIC:     $sp = ADDiu $sp, 8
   ; PIC:   }
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 131068", 1
   ; PIC: bb.4.tail:
   ; PIC:   PseudoReturn undef $ra {
-  ; PIC:     NOP
+  ; PIC:     $zero = SLL $zero, 0
   ; PIC:   }
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $at = ANDi killed renamable $a0, 1
     BLTZ killed renamable $at, %bb.2, implicit-def $at
 

 stack:
 constants:
 body:             |
   ; MIPS-LABEL: name: expand_BNE
   ; MIPS: bb.0 (%ir-block.0):
   ; MIPS:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MIPS:   renamable $at = ANDi killed renamable $a0, 1
   ; MIPS:   BEQ $at, $zero, %bb.2, implicit-def $at {
-  ; MIPS:     NOP
+  ; MIPS:     $zero = SLL $zero, 0
   ; MIPS:   }
   ; MIPS: bb.1 (%ir-block.0):
   ; MIPS:   successors: %bb.3(0x80000000)
   ; MIPS:   J %bb.3, implicit-def $at {
-  ; MIPS:     NOP
+  ; MIPS:     $zero = SLL $zero, 0
   ; MIPS:   }
   ; MIPS: bb.2.iftrue:
   ; MIPS:   successors: %bb.3(0x80000000)
   ; MIPS:   INLINEASM &".space 131068", 1
   ; MIPS: bb.3.tail:
   ; MIPS:   PseudoReturn undef $ra {
-  ; MIPS:     NOP
+  ; MIPS:     $zero = SLL $zero, 0
   ; MIPS:   }
   ; PIC-LABEL: name: expand_BNE
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BEQ $at, $zero, %bb.3, implicit-def $at {
-  ; PIC:     NOP
+  ; PIC:     $zero = SLL $zero, 0
   ; PIC:   }
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
   ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   BAL_BR %bb.2, implicit-def $ra {
   ; PIC:     $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   }
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   JR $at {
   ; PIC:     $sp = ADDiu $sp, 8
   ; PIC:   }
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 131068", 1
   ; PIC: bb.4.tail:
   ; PIC:   PseudoReturn undef $ra {
-  ; PIC:     NOP
+  ; PIC:     $zero = SLL $zero, 0
   ; PIC:   }
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $at = ANDi killed renamable $a0, 1
     BNE killed renamable $at, $zero, %bb.2, implicit-def $at
 

llvm/test/CodeGen/Mips/longbranch/branch-limits-msa.mir

body:             |
   ; MSA: bb.0.entry:
   ; MSA:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MSA:   renamable $w0 = LDI_B 0
   ; MSA:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
   ; MSA:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
   ; MSA:   renamable $w0 = SHF_B killed renamable $w0, 27
   ; MSA:   renamable $w0 = SHF_W killed renamable $w0, 177
   ; MSA:   BNZ_B $w0, %bb.2, implicit-def $at {
-  ; MSA:     NOP
+  ; MSA:     $zero = SLL $zero, 0
   ; MSA:   }
   ; MSA: bb.1.entry:
   ; MSA:   successors: %bb.3(0x80000000)
   ; MSA:   J %bb.3, implicit-def $at {
-  ; MSA:     NOP
+  ; MSA:     $zero = SLL $zero, 0
   ; MSA:   }
   ; MSA: bb.2.if.then:
   ; MSA:   INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; MSA:     renamable $v0 = ADDiu $zero, 1
   ; MSA:   }
   ; MSA: bb.3:
   ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; MSA:     renamable $v0 = ADDiu $zero, 0
   ; MSA:   }
   ; PIC-LABEL: name: _Z4bz_8Dv16_a
   ; PIC: bb.0.entry:
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $w0 = LDI_B 0
   ; PIC:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
   ; PIC:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
   ; PIC:   renamable $w0 = SHF_B killed renamable $w0, 27
   ; PIC:   renamable $w0 = SHF_W killed renamable $w0, 177
   ; PIC:   BNZ_B $w0, %bb.3, implicit-def $at {
-  ; PIC:     NOP
+  ; PIC:     $zero = SLL $zero, 0
   ; PIC:   }
   ; PIC: bb.1.entry:
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp_64 = DADDiu $sp_64, -16
   ; PIC:   SD $ra_64, $sp_64, 0
   ; PIC:   $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   $at_64 = DSLL $at_64, 16
   ; PIC:   BAL_BR %bb.2, implicit-def $ra {
body:             |
   ; MSA-LABEL: name: _Z5bz_16Dv8_s
   ; MSA: bb.0.entry:
   ; MSA:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MSA:   renamable $w0 = LDI_B 0
   ; MSA:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
   ; MSA:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
   ; MSA:   renamable $w0 = SHF_H killed renamable $w0, 27
   ; MSA:   BNZ_H $w0, %bb.2, implicit-def $at {
-  ; MSA:     NOP
+  ; MSA:     $zero = SLL $zero, 0
   ; MSA:   }
   ; MSA: bb.1.entry:
   ; MSA:   successors: %bb.3(0x80000000)
   ; MSA:   J %bb.3, implicit-def $at {
-  ; MSA:     NOP
+  ; MSA:     $zero = SLL $zero, 0
   ; MSA:   }
   ; MSA: bb.2.if.then:
   ; MSA:   INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; MSA:     renamable $v0 = ADDiu $zero, 1
   ; MSA:   }
   ; MSA: bb.3:
   ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; MSA:     renamable $v0 = ADDiu $zero, 0
   ; MSA:   }
   ; PIC-LABEL: name: _Z5bz_16Dv8_s
   ; PIC: bb.0.entry:
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $w0 = LDI_B 0
   ; PIC:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
   ; PIC:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
   ; PIC:   renamable $w0 = SHF_H killed renamable $w0, 27
   ; PIC:   BNZ_H $w0, %bb.3, implicit-def $at {
-  ; PIC:     NOP
+  ; PIC:     $zero = SLL $zero, 0
   ; PIC:   }
   ; PIC: bb.1.entry:
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp_64 = DADDiu $sp_64, -16
   ; PIC:   SD $ra_64, $sp_64, 0
   ; PIC:   $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   $at_64 = DSLL $at_64, 16
   ; PIC:   BAL_BR %bb.2, implicit-def $ra {
body:             |
   ; MSA-LABEL: name: _Z5bz_32Dv4_i
   ; MSA: bb.0.entry:
   ; MSA:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MSA:   renamable $w0 = LDI_B 0
   ; MSA:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
   ; MSA:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
   ; MSA:   renamable $w0 = SHF_W killed renamable $w0, 177
   ; MSA:   BNZ_W $w0, %bb.2, implicit-def $at {
-  ; MSA:     NOP
+  ; MSA:     $zero = SLL $zero, 0
   ; MSA:   }
   ; MSA: bb.1.entry:
   ; MSA:   successors: %bb.3(0x80000000)
   ; MSA:   J %bb.3, implicit-def $at {
-  ; MSA:     NOP
+  ; MSA:     $zero = SLL $zero, 0
   ; MSA:   }
   ; MSA: bb.2.if.then:
   ; MSA:   INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; MSA:     renamable $v0 = ADDiu $zero, 1
   ; MSA:   }
   ; MSA: bb.3:
   ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; MSA:     renamable $v0 = ADDiu $zero, 0
   ; MSA:   }
   ; PIC-LABEL: name: _Z5bz_32Dv4_i
   ; PIC: bb.0.entry:
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $w0 = LDI_B 0
   ; PIC:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
   ; PIC:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
   ; PIC:   renamable $w0 = SHF_W killed renamable $w0, 177
   ; PIC:   BNZ_W $w0, %bb.3, implicit-def $at {
-  ; PIC:     NOP
+  ; PIC:     $zero = SLL $zero, 0
   ; PIC:   }
   ; PIC: bb.1.entry:
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp_64 = DADDiu $sp_64, -16
   ; PIC:   SD $ra_64, $sp_64, 0
   ; PIC:   $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   $at_64 = DSLL $at_64, 16
   ; PIC:   BAL_BR %bb.2, implicit-def $ra {

 body:             |
   ; MSA-LABEL: name: _Z5bz_64Dv2_x
   ; MSA: bb.0.entry:
   ; MSA:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MSA:   renamable $w0 = LDI_B 0
   ; MSA:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
   ; MSA:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
   ; MSA:   BNZ_D $w0, %bb.2, implicit-def $at {
-  ; MSA:     NOP
+  ; MSA:     $zero = SLL $zero, 0
   ; MSA:   }
   ; MSA: bb.1.entry:
   ; MSA:   successors: %bb.3(0x80000000)
   ; MSA:   J %bb.3, implicit-def $at {
-  ; MSA:     NOP
+  ; MSA:     $zero = SLL $zero, 0
   ; MSA:   }
   ; MSA: bb.2.if.then:
   ; MSA:   INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; MSA:     renamable $v0 = ADDiu $zero, 1
   ; MSA:   }
   ; MSA: bb.3:
   ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; MSA:     renamable $v0 = ADDiu $zero, 0
   ; MSA:   }
   ; PIC-LABEL: name: _Z5bz_64Dv2_x
   ; PIC: bb.0.entry:
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $w0 = LDI_B 0
   ; PIC:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
   ; PIC:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
   ; PIC:   BNZ_D $w0, %bb.3, implicit-def $at {
-  ; PIC:     NOP
+  ; PIC:     $zero = SLL $zero, 0
   ; PIC:   }
   ; PIC: bb.1.entry:
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp_64 = DADDiu $sp_64, -16
   ; PIC:   SD $ra_64, $sp_64, 0
   ; PIC:   $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   $at_64 = DSLL $at_64, 16
   ; PIC:   BAL_BR %bb.2, implicit-def $ra {

 body:             |
   ; MSA-LABEL: name: _Z5bz_64_vDv2_x
   ; MSA: bb.0.entry:
   ; MSA:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MSA:   renamable $w0 = LDI_B 0
   ; MSA:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
   ; MSA:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
   ; MSA:   BNZ_V $w0, %bb.2, implicit-def $at {
-  ; MSA:     NOP
+  ; MSA:     $zero = SLL $zero, 0
   ; MSA:   }
   ; MSA: bb.1.entry:
   ; MSA:   successors: %bb.3(0x80000000)
   ; MSA:   J %bb.3, implicit-def $at {
-  ; MSA:     NOP
+  ; MSA:     $zero = SLL $zero, 0
   ; MSA:   }
   ; MSA: bb.2.if.then:
   ; MSA:   INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; MSA:     renamable $v0 = ADDiu $zero, 1
   ; MSA:   }
   ; MSA: bb.3:
   ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; MSA:     renamable $v0 = ADDiu $zero, 0
   ; MSA:   }
   ; PIC-LABEL: name: _Z5bz_64_vDv2_x
   ; PIC: bb.0.entry:
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $w0 = LDI_B 0
   ; PIC:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
   ; PIC:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
   ; PIC:   BNZ_V $w0, %bb.3, implicit-def $at {
-  ; PIC:     NOP
+  ; PIC:     $zero = SLL $zero, 0
   ; PIC:   }
   ; PIC: bb.1.entry:
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp_64 = DADDiu $sp_64, -16
   ; PIC:   SD $ra_64, $sp_64, 0
   ; PIC:   $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   $at_64 = DSLL $at_64, 16
   ; PIC:   BAL_BR %bb.2, implicit-def $ra {
body:             |
   ; MSA: bb.0.entry:
   ; MSA:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MSA:   renamable $w0 = LDI_B 0
   ; MSA:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
   ; MSA:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
   ; MSA:   renamable $w0 = SHF_B killed renamable $w0, 27
   ; MSA:   renamable $w0 = SHF_W killed renamable $w0, 177
   ; MSA:   BZ_B $w0, %bb.2, implicit-def $at {
-  ; MSA:     NOP
+  ; MSA:     $zero = SLL $zero, 0
   ; MSA:   }
   ; MSA: bb.1.entry:
   ; MSA:   successors: %bb.3(0x80000000)
   ; MSA:   J %bb.3, implicit-def $at {
-  ; MSA:     NOP
+  ; MSA:     $zero = SLL $zero, 0
   ; MSA:   }
   ; MSA: bb.2.if.then:
   ; MSA:   INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; MSA:     renamable $v0 = ADDiu $zero, 1
   ; MSA:   }
   ; MSA: bb.3:
   ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; MSA:     renamable $v0 = ADDiu $zero, 0
   ; MSA:   }
   ; PIC-LABEL: name: _Z5bnz_8Dv16_a
   ; PIC: bb.0.entry:
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $w0 = LDI_B 0
   ; PIC:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
   ; PIC:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
   ; PIC:   renamable $w0 = SHF_B killed renamable $w0, 27
   ; PIC:   renamable $w0 = SHF_W killed renamable $w0, 177
   ; PIC:   BZ_B $w0, %bb.3, implicit-def $at {
-  ; PIC:     NOP
+  ; PIC:     $zero = SLL $zero, 0
   ; PIC:   }
   ; PIC: bb.1.entry:
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp_64 = DADDiu $sp_64, -16
   ; PIC:   SD $ra_64, $sp_64, 0
   ; PIC:   $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   $at_64 = DSLL $at_64, 16
   ; PIC:   BAL_BR %bb.2, implicit-def $ra {
body:             |
   ; MSA-LABEL: name: _Z6bnz_16Dv8_s
   ; MSA: bb.0.entry:
   ; MSA:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MSA:   renamable $w0 = LDI_B 0
   ; MSA:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
   ; MSA:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
   ; MSA:   renamable $w0 = SHF_H killed renamable $w0, 27
   ; MSA:   BZ_H $w0, %bb.2, implicit-def $at {
-  ; MSA:     NOP
+  ; MSA:     $zero = SLL $zero, 0
   ; MSA:   }
   ; MSA: bb.1.entry:
   ; MSA:   successors: %bb.3(0x80000000)
   ; MSA:   J %bb.3, implicit-def $at {
-  ; MSA:     NOP
+  ; MSA:     $zero = SLL $zero, 0
   ; MSA:   }
   ; MSA: bb.2.if.then:
   ; MSA:   INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; MSA:     renamable $v0 = ADDiu $zero, 1
   ; MSA:   }
   ; MSA: bb.3:
   ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; MSA:     renamable $v0 = ADDiu $zero, 0
   ; MSA:   }
   ; PIC-LABEL: name: _Z6bnz_16Dv8_s
   ; PIC: bb.0.entry:
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $w0 = LDI_B 0
   ; PIC:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
   ; PIC:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
   ; PIC:   renamable $w0 = SHF_H killed renamable $w0, 27
   ; PIC:   BZ_H $w0, %bb.3, implicit-def $at {
-  ; PIC:     NOP
+  ; PIC:     $zero = SLL $zero, 0
   ; PIC:   }
   ; PIC: bb.1.entry:
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp_64 = DADDiu $sp_64, -16
   ; PIC:   SD $ra_64, $sp_64, 0
   ; PIC:   $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   $at_64 = DSLL $at_64, 16
   ; PIC:   BAL_BR %bb.2, implicit-def $ra {
body:             |
   ; MSA-LABEL: name: _Z6bnz_32Dv4_i
   ; MSA: bb.0.entry:
   ; MSA:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MSA:   renamable $w0 = LDI_B 0
   ; MSA:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
   ; MSA:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
   ; MSA:   renamable $w0 = SHF_W killed renamable $w0, 177
   ; MSA:   BZ_W $w0, %bb.2, implicit-def $at {
-  ; MSA:     NOP
+  ; MSA:     $zero = SLL $zero, 0
   ; MSA:   }
   ; MSA: bb.1.entry:
   ; MSA:   successors: %bb.3(0x80000000)
   ; MSA:   J %bb.3, implicit-def $at {
-  ; MSA:     NOP
+  ; MSA:     $zero = SLL $zero, 0
   ; MSA:   }
   ; MSA: bb.2.if.then:
   ; MSA:   INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; MSA:     renamable $v0 = ADDiu $zero, 1
   ; MSA:   }
   ; MSA: bb.3:
   ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; MSA:     renamable $v0 = ADDiu $zero, 0
   ; MSA:   }
   ; PIC-LABEL: name: _Z6bnz_32Dv4_i
   ; PIC: bb.0.entry:
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $w0 = LDI_B 0
   ; PIC:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
   ; PIC:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
   ; PIC:   renamable $w0 = SHF_W killed renamable $w0, 177
   ; PIC:   BZ_W $w0, %bb.3, implicit-def $at {
-  ; PIC:     NOP
+  ; PIC:     $zero = SLL $zero, 0
   ; PIC:   }
   ; PIC: bb.1.entry:
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp_64 = DADDiu $sp_64, -16
   ; PIC:   SD $ra_64, $sp_64, 0
   ; PIC:   $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   $at_64 = DSLL $at_64, 16
   ; PIC:   BAL_BR %bb.2, implicit-def $ra {

 body:             |
   ; MSA-LABEL: name: _Z6bnz_64Dv2_x
   ; MSA: bb.0.entry:
   ; MSA:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MSA:   renamable $w0 = LDI_B 0
   ; MSA:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
   ; MSA:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
   ; MSA:   BZ_D $w0, %bb.2, implicit-def $at {
-  ; MSA:     NOP
+  ; MSA:     $zero = SLL $zero, 0
   ; MSA:   }
   ; MSA: bb.1.entry:
   ; MSA:   successors: %bb.3(0x80000000)
   ; MSA:   J %bb.3, implicit-def $at {
-  ; MSA:     NOP
+  ; MSA:     $zero = SLL $zero, 0
   ; MSA:   }
   ; MSA: bb.2.if.then:
   ; MSA:   INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; MSA:     renamable $v0 = ADDiu $zero, 1
   ; MSA:   }
   ; MSA: bb.3:
   ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; MSA:     renamable $v0 = ADDiu $zero, 0
   ; MSA:   }
   ; PIC-LABEL: name: _Z6bnz_64Dv2_x
   ; PIC: bb.0.entry:
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $w0 = LDI_B 0
   ; PIC:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
   ; PIC:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
   ; PIC:   BZ_D $w0, %bb.3, implicit-def $at {
-  ; PIC:     NOP
+  ; PIC:     $zero = SLL $zero, 0
   ; PIC:   }
   ; PIC: bb.1.entry:
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp_64 = DADDiu $sp_64, -16
   ; PIC:   SD $ra_64, $sp_64, 0
   ; PIC:   $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   $at_64 = DSLL $at_64, 16
   ; PIC:   BAL_BR %bb.2, implicit-def $ra {

 body:             |
   ; MSA-LABEL: name: _Z6bnz_64_vDv2_x
   ; MSA: bb.0.entry:
   ; MSA:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MSA:   renamable $w0 = LDI_B 0
   ; MSA:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
   ; MSA:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
   ; MSA:   BZ_V $w0, %bb.2, implicit-def $at {
-  ; MSA:     NOP
+  ; MSA:     $zero = SLL $zero, 0
   ; MSA:   }
   ; MSA: bb.1.entry:
   ; MSA:   successors: %bb.3(0x80000000)
   ; MSA:   J %bb.3, implicit-def $at {
-  ; MSA:     NOP
+  ; MSA:     $zero = SLL $zero, 0
   ; MSA:   }
   ; MSA: bb.2.if.then:
   ; MSA:   INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; MSA:     renamable $v0 = ADDiu $zero, 1
   ; MSA:   }
   ; MSA: bb.3:
   ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; MSA:     renamable $v0 = ADDiu $zero, 0
   ; MSA:   }
   ; PIC-LABEL: name: _Z6bnz_64_vDv2_x
   ; PIC: bb.0.entry:
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $w0 = LDI_B 0
   ; PIC:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
   ; PIC:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
   ; PIC:   BZ_V $w0, %bb.3, implicit-def $at {
-  ; PIC:     NOP
+  ; PIC:     $zero = SLL $zero, 0
   ; PIC:   }
   ; PIC: bb.1.entry:
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp_64 = DADDiu $sp_64, -16
   ; PIC:   SD $ra_64, $sp_64, 0
   ; PIC:   $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   $at_64 = DSLL $at_64, 16
   ; PIC:   BAL_BR %bb.2, implicit-def $ra {