[RISCV]Add CTZ Intrinsic for ZBB in Clang

[joker881]

Summary

Add Intrinsics and test for B extension (updating coming soon (:

[craig.topper]

The "B extension" terminology no longer exists.

clang/include/clang/Basic/BuiltinsRISCV.def

29

The only ones of these we need is ctz_32 and ctz_64 and they should be implemented the same as clz_32/clz_64.

I guess we might also need max_32/max_64/maxu_32/maxu_64/min_32/min_64/minu_32/minu_64 for -O0. For -O1 and above (x > y) ? x : y already works. They can use the existing llvm.smax/smin/umax/umin intrinsics.

andn can be represented directly in C with X & ~Y
orn is X | ~Y
cpop_32 is builtin_popcount
cpop_64 is builtin_popcountll
clzw_32 is __builtin_riscv_clz_32 sign extended to 64 bits. Similar for ctzw_64.

llvm/include/llvm/IR/IntrinsicsRISCV.td

90 ↗

(On Diff #424790)

We don't need any of these intrinsics.

Max already has llvm.smax and llvm.umax.
clzw is (signext (llvm.cltz))
cpop is llvm.ctpop
cpopw is (signext (llvm.ctpop))
andn is (and X, (not Y))
orn is (or X, (not Y))
ctz is llvm.ctlz

[joker881]

In D124348#3470612, @craig.topper wrote:

The "B extension" terminology no longer exists.

Thank you for your comments. I will consider them carefully. And I want to know that do you have any documents about intrinsic of bitmanip extension, like RISC-V Vector Extension Intrinsic Document.

[kito-cheng]

And I want to know that do you have any documents about intrinsic of bitmanip extension, like RISC-V Vector Extension Intrinsic Document.

No, we didn't have a formal document for that, I expect we will have one once this finalized https://github.com/riscv-non-isa/riscv-c-api-doc/pull/25 ...

[joker881]

In D124348#3470612, @craig.topper wrote:

The "B extension" terminology no longer exists.

And I decide to implement ctz_32 and ctz_64 like clz.

[joker881]

Implement intrinsic ctz for bitmanip extension

[craig.topper]

LGTM, but please fix the title to not use "B extension" since the "B extension" was never ratified. Only Zba, Zbb, Zbc, Zbs were ratified and there will never be a B.

[joker881]

update test

clang/include/clang/Basic/BuiltinsRISCV.def

 #   define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) BUILTIN(ID, TYPE, ATTRS)
 #endif
 
 // Zbb extension
 TARGET_BUILTIN(__builtin_riscv_orc_b_32, "ZiZi", "nc", "zbb")
 TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "zbb,64bit")
 TARGET_BUILTIN(__builtin_riscv_clz_32, "ZiZi", "nc", "zbb")
 TARGET_BUILTIN(__builtin_riscv_clz_64, "WiWi", "nc", "zbb,64bit")
+TARGET_BUILTIN(__builtin_riscv_ctz_32, "ZiZi", "nc", "zbb")
+TARGET_BUILTIN(__builtin_riscv_ctz_64, "WiWi", "nc", "zbb,64bit")
 
 // Zbc or Zbkc extension
 TARGET_BUILTIN(__builtin_riscv_clmul, "LiLiLi", "nc", "zbc|zbkc")
 TARGET_BUILTIN(__builtin_riscv_clmulh, "LiLiLi", "nc", "zbc|zbkc")
 TARGET_BUILTIN(__builtin_riscv_clmulr, "LiLiLi", "nc", "zbc")
 
 // Zbkx
 TARGET_BUILTIN(__builtin_riscv_xperm4, "LiLiLi", "nc", "zbkx")
 TARGET_BUILTIN(__builtin_riscv_xperm8, "LiLiLi", "nc", "zbkx")
 
 // Zbe extension
 TARGET_BUILTIN(__builtin_riscv_bcompress_32, "ZiZiZi", "nc", "experimental-zbe")
 TARGET_BUILTIN(__builtin_riscv_bcompress_64, "WiWiWi", "nc",

clang/lib/CodeGen/CGBuiltin.cpp

Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
   // Required for overloaded intrinsics.
   llvm::SmallVector<llvm::Type *, 2> IntrinsicTypes;
   switch (BuiltinID) {
   default: llvm_unreachable("unexpected builtin ID");
   case RISCV::BI__builtin_riscv_orc_b_32:
   case RISCV::BI__builtin_riscv_orc_b_64:
   case RISCV::BI__builtin_riscv_clz_32:
   case RISCV::BI__builtin_riscv_clz_64:
+  case RISCV::BI__builtin_riscv_ctz_32:
+  case RISCV::BI__builtin_riscv_ctz_64:
   case RISCV::BI__builtin_riscv_clmul:
   case RISCV::BI__builtin_riscv_clmulh:
   case RISCV::BI__builtin_riscv_clmulr:
   case RISCV::BI__builtin_riscv_bcompress_32:
   case RISCV::BI__builtin_riscv_bcompress_64:
   case RISCV::BI__builtin_riscv_bdecompress_32:
   case RISCV::BI__builtin_riscv_bdecompress_64:
   case RISCV::BI__builtin_riscv_bfp_32:
case RISCV::BI__builtin_riscv_unzip_32: {
     case RISCV::BI__builtin_riscv_orc_b_64:
       ID = Intrinsic::riscv_orc_b;
       break;
     case RISCV::BI__builtin_riscv_clz_32:
     case RISCV::BI__builtin_riscv_clz_64: {
       Function *F = CGM.getIntrinsic(Intrinsic::ctlz, Ops[0]->getType());
       return Builder.CreateCall(F, {Ops[0], Builder.getInt1(false)});
     }
+    case RISCV::BI__builtin_riscv_ctz_32:
+    case RISCV::BI__builtin_riscv_ctz_64: {
+      Function *F = CGM.getIntrinsic(Intrinsic::cttz, Ops[0]->getType());
+      return Builder.CreateCall(F, {Ops[0], Builder.getInt1(false)});
+    }
 
     // Zbc
     case RISCV::BI__builtin_riscv_clmul:
       ID = Intrinsic::riscv_clmul;
       break;
     case RISCV::BI__builtin_riscv_clmulh:
       ID = Intrinsic::riscv_clmulh;
       break;

clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c

 // RV32ZBB-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
 // RV32ZBB-NEXT:    store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
 // RV32ZBB-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
 // RV32ZBB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 false)
 // RV32ZBB-NEXT:    ret i32 [[TMP1]]
 //
 int clz_32(int a) {
   return __builtin_riscv_clz_32(a);
+}
+
+// RV32ZBB-LABEL: @ctz_32(
+// RV32ZBB-NEXT:  entry:
+// RV32ZBB-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBB-NEXT:    store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBB-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 false)
+// RV32ZBB-NEXT:    ret i32 [[TMP1]]
+//
+int ctz_32(int a) {
+  return __builtin_riscv_ctz_32(a);
 }
 No newline at end of file

clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c

 // RV64ZBB-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
 // RV64ZBB-NEXT:    store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
 // RV64ZBB-NEXT:    [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
 // RV64ZBB-NEXT:    [[TMP1:%.*]] = call i64 @llvm.ctlz.i64(i64 [[TMP0]], i1 false)
 // RV64ZBB-NEXT:    ret i64 [[TMP1]]
 //
 long clz_64(long a) {
   return __builtin_riscv_clz_64(a);
+}
+
+// RV64ZBB-LABEL: @ctz_64(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBB-NEXT:    store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBB-NEXT:    [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBB-NEXT:    [[TMP1:%.*]] = call i64 @llvm.cttz.i64(i64 [[TMP0]], i1 false)
+// RV64ZBB-NEXT:    ret i64 [[TMP1]]
+//
+long ctz_64(long a) {
+  return __builtin_riscv_ctz_64(a);
 }
 No newline at end of file