This is an archive of the discontinued LLVM Phabricator instance.

Differential D123839

[RISCV][NFC] Use defvar to simplify pattern definations.
ClosedPublic

Authored by Pretty-box on Apr 15 2022, 12:36 AM.

Details

Reviewers
benshi001
craig.topper
frasercrmck
jacquesguan
Commits
rG7493d9ffb63d: [RISCV][NFC] Use defvar to simplify pattern definations.

Diff Detail

Event Timeline

Pretty-box created this revision.Apr 15 2022, 12:36 AM
Herald added subscribers: sunshaoce, VincentWu, luke957 and 28 others. · View Herald TranscriptApr 15 2022, 12:36 AM
Pretty-box requested review of this revision.Apr 15 2022, 12:36 AM
Herald added subscribers: llvm-commits, • pcwang-thead, eopXD, MaskRay. · View Herald TranscriptApr 15 2022, 12:36 AM
Pretty-box added a reviewer: jacquesguan.Apr 15 2022, 12:50 AM
jacquesguan added inline comments.Apr 15 2022, 1:01 AM
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
707

Can these two lines be merged into one line if is less than 80 cols?

829

Should adjust the align here.

Harbormaster completed remote builds in B159786: Diff 423027.Apr 15 2022, 1:21 AM
Pretty-box updated this revision to Diff 423049.Apr 15 2022, 1:49 AM
Pretty-box marked 2 inline comments as done.
jacquesguan accepted this revision.Apr 15 2022, 2:17 AM

LGTM

This revision is now accepted and ready to land.Apr 15 2022, 2:17 AM
Pretty-box added a comment.Apr 15 2022, 2:29 AM

Address comment

Harbormaster completed remote builds in B159801: Diff 423049.Apr 15 2022, 3:05 AM
frasercrmck accepted this revision.Apr 18 2022, 12:19 AM

LGTM too

This revision was landed with ongoing or failed builds.Apr 21 2022, 7:45 PM
Closed by commit rG7493d9ffb63d: [RISCV][NFC] Use defvar to simplify pattern definations. (authored by Pretty-box, committed by benshi001). · Explain Why
This revision was automatically updated to reflect the committed changes.
benshi001 added a commit: rG7493d9ffb63d: [RISCV][NFC] Use defvar to simplify pattern definations..

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
66 lines

Diff 423027

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

Show First 20 Lines • Show All 677 Lines • ▼ Show 20 Lines def: Pat<(vti_m1.Vector (vop (vti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), VR:$rs2,
(vti_m1.Vector VR:$merge), (vti_m1.Vector VR:$merge),
(vti.Vector vti.RegClass:$rs1), (vti.Vector vti.RegClass:$rs1),
(vti_m1.Vector VR:$rs2), (vti_m1.Vector VR:$rs2),
(vti.Mask V0), GPR:$vl, vti.Log2SEW)>; (vti.Mask V0), GPR:$vl, vti.Log2SEW)>;
} }
} }
multiclass VPatBinarySDNodeExt_V_WV_WX<SDNode op, PatFrags extop, string instruction_name> { multiclass VPatBinarySDNodeExt_V_WV_WX<SDNode op, PatFrags extop, string instruction_name> {
foreach vti = AllWidenableIntVectors in { foreach vtiToWti = AllWidenableIntVectors in {
defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti;
def : Pat< def : Pat<
(vti.Vti.Vector (vti.Vector
(riscv_trunc_vector_vl (riscv_trunc_vector_vl
(op (vti.Wti.Vector vti.Wti.RegClass:$rs2), (op (wti.Vector wti.RegClass:$rs2),
(vti.Wti.Vector (extop (vti.Vti.Vector vti.Vti.RegClass:$rs1)))), (wti.Vector (extop (vti.Vector vti.RegClass:$rs1)))),
(riscv_vmset_vl VLOpFrag), (riscv_vmset_vl VLOpFrag),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>(instruction_name#"_WV_"#vti.Vti.LMul.MX) (!cast<Instruction>(instruction_name#"_WV_"#vti.LMul.MX)
vti.Wti.RegClass:$rs2, vti.Vti.RegClass:$rs1, wti.RegClass:$rs2, vti.RegClass:$rs1,
vti.Vti.AVL, vti.Vti.Log2SEW)>; vti.AVL, vti.Log2SEW)>;
def : Pat< def : Pat<
(vti.Vti.Vector (vti.Vector
(riscv_trunc_vector_vl (riscv_trunc_vector_vl
(op (vti.Wti.Vector vti.Wti.RegClass:$rs2), (op (wti.Vector wti.RegClass:$rs2),
(vti.Wti.Vector (extop (vti.Vti.Vector (SplatPat GPR:$rs1))))), (wti.Vector (extop (vti.Vector (SplatPat GPR:$rs1))))),
(riscv_vmset_vl VLOpFrag), (riscv_vmset_vl VLOpFrag),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>(instruction_name#"_WX_"#vti.Vti.LMul.MX) (!cast<Instruction>(instruction_name#"_WX_"#vti.LMul.MX)
vti.Wti.RegClass:$rs2, GPR:$rs1, wti.RegClass:$rs2, GPR:$rs1,
jacquesguanUnsubmitted
Done
ReplyInline Actions

Can these two lines be merged into one line if is less than 80 cols?

jacquesguan: Can these two lines be merged into one line if is less than 80 cols?
vti.Vti.AVL, vti.Vti.Log2SEW)>; vti.AVL, vti.Log2SEW)>;
} }
} }
multiclass VPatBinarySDNode_V_WV_WX_WI<SDNode op, string instruction_name> { multiclass VPatBinarySDNode_V_WV_WX_WI<SDNode op, string instruction_name> {
defm : VPatBinarySDNodeExt_V_WV_WX<op, sext_oneuse, instruction_name>; defm : VPatBinarySDNodeExt_V_WV_WX<op, sext_oneuse, instruction_name>;
defm : VPatBinarySDNodeExt_V_WV_WX<op, zext_oneuse, instruction_name>; defm : VPatBinarySDNodeExt_V_WV_WX<op, zext_oneuse, instruction_name>;
foreach vti = AllWidenableIntVectors in { foreach vtiToWti = AllWidenableIntVectors in {
defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti;
def : Pat< def : Pat<
(vti.Vti.Vector (vti.Vector
(riscv_trunc_vector_vl (riscv_trunc_vector_vl
(op (vti.Wti.Vector vti.Wti.RegClass:$rs2), (op (wti.Vector wti.RegClass:$rs2),
(vti.Wti.Vector (SplatPat_uimm5 uimm5:$rs1))), (wti.Vector (SplatPat_uimm5 uimm5:$rs1))),
(riscv_vmset_vl VLOpFrag), (riscv_vmset_vl VLOpFrag),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>(instruction_name#"_WI_"#vti.Vti.LMul.MX) (!cast<Instruction>(instruction_name#"_WI_"#vti.LMul.MX)
vti.Wti.RegClass:$rs2, uimm5:$rs1, wti.RegClass:$rs2, uimm5:$rs1,
vti.Vti.AVL, vti.Vti.Log2SEW)>; vti.AVL, vti.Log2SEW)>;
} }
} }
multiclass VPatWidenReductionVL<SDNode vop, PatFrags extop, string instruction_name, bit is_float> { multiclass VPatWidenReductionVL<SDNode vop, PatFrags extop, string instruction_name, bit is_float> {
foreach vtiToWti = !if(is_float, AllWidenableFloatVectors, AllWidenableIntVectors) in { foreach vtiToWti = !if(is_float, AllWidenableFloatVectors, AllWidenableIntVectors) in {
defvar vti = vtiToWti.Vti; defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti; defvar wti = vtiToWti.Wti;
defvar wti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # wti.SEW # "M1"); defvar wti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # wti.SEW # "M1");
▲ Show 20 Lines • Show All 77 Lines • ▼ Show 20 Lines
} }
multiclass VPatWidenBinaryFPVL_VV_VF_WV_WF<SDNode op, string instruction_name> { multiclass VPatWidenBinaryFPVL_VV_VF_WV_WF<SDNode op, string instruction_name> {
defm : VPatWidenBinaryFPVL_VV_VF<op, riscv_fpextend_vl_oneuse, instruction_name>; defm : VPatWidenBinaryFPVL_VV_VF<op, riscv_fpextend_vl_oneuse, instruction_name>;
defm : VPatWidenBinaryFPVL_WV_WF<op, riscv_fpextend_vl_oneuse, instruction_name>; defm : VPatWidenBinaryFPVL_WV_WF<op, riscv_fpextend_vl_oneuse, instruction_name>;
} }
multiclass VPatNarrowShiftSplatExt_WX<SDNode op, PatFrags extop, string instruction_name> { multiclass VPatNarrowShiftSplatExt_WX<SDNode op, PatFrags extop, string instruction_name> {
foreach vti = AllWidenableIntVectors in { foreach vtiToWti = AllWidenableIntVectors in {
defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti;
def : Pat< def : Pat<
(vti.Vti.Vector (vti.Vector
(riscv_trunc_vector_vl (riscv_trunc_vector_vl
(op (vti.Wti.Vector vti.Wti.RegClass:$rs2), (op (wti.Vector wti.RegClass:$rs2),
(vti.Wti.Vector (extop (vti.Vti.Vector (SplatPat GPR:$rs1)), (wti.Vector (extop (vti.Vector (SplatPat GPR:$rs1)),
(vti.Vti.Mask true_mask), VLOpFrag)), (vti.Mask true_mask), VLOpFrag)),
jacquesguanUnsubmitted
Done
ReplyInline Actions

Should adjust the align here.

jacquesguan: Should adjust the align here.
(vti.Wti.Mask true_mask), VLOpFrag), (wti.Mask true_mask), VLOpFrag),
(vti.Vti.Mask true_mask), VLOpFrag)), (vti.Mask true_mask), VLOpFrag)),
(!cast<Instruction>(instruction_name#"_WX_"#vti.Vti.LMul.MX) (!cast<Instruction>(instruction_name#"_WX_"#vti.LMul.MX)
vti.Wti.RegClass:$rs2, GPR:$rs1, wti.RegClass:$rs2, GPR:$rs1,
vti.Vti.AVL, vti.Vti.Log2SEW)>; vti.AVL, vti.Log2SEW)>;
} }
} }
multiclass VPatMultiplyAddVL_VV_VX<SDNode op, string instruction_name> { multiclass VPatMultiplyAddVL_VV_VX<SDNode op, string instruction_name> {
foreach vti = AllIntegerVectors in { foreach vti = AllIntegerVectors in {
defvar suffix = vti.LMul.MX; defvar suffix = vti.LMul.MX;
// NOTE: We choose VMADD because it has the most commuting freedom. So it // NOTE: We choose VMADD because it has the most commuting freedom. So it
// works best with how TwoAddressInstructionPass tries commuting. // works best with how TwoAddressInstructionPass tries commuting.
▲ Show 20 Lines • Show All 1,101 Lines • Show Last 20 Lines