[PPC][CodeGen][NFC] Use ArrayRef in TargetLowering functions

[lkail]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

197

I doubt if it really eases developer to read the code. This API implies Cartesian product, but some might think it as one-to-one mapping at first glance due to the same length.
Also, if we have new operation but only applied to MVT::f64, we still need another statement to specify it.

[Miss_Grape]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

197

Do you mean to change only one semantic, operate Ops alone or operate VTs alones？？
Pleas see this ： https://reviews.llvm.org/D123467

[nemanjai]

While I certainly appreciate the work to refactor this behemoth of a function, I am about as lukewarm on how much of a readability improvement this is. If all the targets are being similarly refactored, I won't stand in the way of doing the same to PPC. So if you get the approval for the other targets, we'll go ahead with PPC as well.

[Miss_Grape]

In D123663#3450323, @nemanjai wrote:

While I certainly appreciate the work to refactor this behemoth of a function, I am about as lukewarm on how much of a readability improvement this is. If all the targets are being similarly refactored, I won't stand in the way of doing the same to PPC. So if you get the approval for the other targets, we'll go ahead with PPC as well.

RISCV/X86 get the approval.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

   }
 
   // Match BITREVERSE to customized fast code sequence in the td file.
-  setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
-  setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
+  setOperationAction(ISD::BITREVERSE, {MVT::i32, MVT::i64}, Legal);
 
   // Sub-word ATOMIC_CMP_SWAP need to ensure that the input is zero-extended.
   setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
 
   // Custom lower inline assembly to check for special registers.
-  setOperationAction(ISD::INLINEASM, MVT::Other, Custom);
-  setOperationAction(ISD::INLINEASM_BR, MVT::Other, Custom);
+  setOperationAction({ISD::INLINEASM, ISD::INLINEASM_BR}, MVT::Other, Custom);
 
   // PowerPC has an i16 but no i8 (or i1) SEXTLOAD.
   for (MVT VT : MVT::integer_valuetypes()) {

   } else {
     // No extending loads from f16 or HW conversions back and forth.
     setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
-    setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
-    setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
+    setOperationAction({ISD::FP16_TO_FP, ISD::FP_TO_FP16}, {MVT::f64, MVT::f32},
+                       Expand);
     setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
-    setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
-    setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
     setTruncStoreAction(MVT::f64, MVT::f16, Expand);
     setTruncStoreAction(MVT::f32, MVT::f16, Expand);
   }

   }
 
   // PowerPC uses ADDC/ADDE/SUBC/SUBE to propagate carry.
-  const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
-  for (MVT VT : ScalarIntVTs) {
-    setOperationAction(ISD::ADDC, VT, Legal);
-    setOperationAction(ISD::ADDE, VT, Legal);
-    setOperationAction(ISD::SUBC, VT, Legal);
-    setOperationAction(ISD::SUBE, VT, Legal);
-  }
+  setOperationAction({ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE},
+                     {MVT::i32, MVT::i64}, Legal);
 
   if (Subtarget.useCRBits()) {
     setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);

       setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote);
       AddPromotedToType(ISD::FP_TO_UINT, MVT::i1,
                         isPPC64 ? MVT::i64 : MVT::i32);
-    } else {
-      setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i1, Custom);
-      setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i1, Custom);
-      setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
-      setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
-    }
+    } else
+      setOperationAction({ISD::STRICT_SINT_TO_FP, ISD::STRICT_UINT_TO_FP,
+                          ISD::SINT_TO_FP, ISD::UINT_TO_FP},
+                         MVT::i1, Custom);
 
     // PowerPC does not support direct load/store of condition registers.
-    setOperationAction(ISD::LOAD, MVT::i1, Custom);
-    setOperationAction(ISD::STORE, MVT::i1, Custom);
+    setOperationAction({ISD::LOAD, ISD::STORE}, MVT::i1, Custom);
 
     // FIXME: Remove this once the ANDI glue bug is fixed:
     if (ANDIGlueBug)

 
   // Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on
   // PPC (the libcall is not available).
-  setOperationAction(ISD::FP_TO_SINT, MVT::ppcf128, Custom);
-  setOperationAction(ISD::FP_TO_UINT, MVT::ppcf128, Custom);
-  setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::ppcf128, Custom);
-  setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::ppcf128, Custom);
+  setOperationAction({ISD::FP_TO_SINT, ISD::FP_TO_UINT, ISD::STRICT_FP_TO_SINT,
+                      ISD::STRICT_FP_TO_UINT},
+                     MVT::ppcf128, Custom);
 
   // We do not currently implement these libm ops for PowerPC.
-  setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
-  setOperationAction(ISD::FCEIL,  MVT::ppcf128, Expand);
-  setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
-  setOperationAction(ISD::FRINT,  MVT::ppcf128, Expand);
-  setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
-  setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
+  setOperationAction({ISD::FFLOOR, ISD::FCEIL, ISD::FTRUNC, ISD::FRINT,
+                      ISD::FNEARBYINT, ISD::FREM},
+                     MVT::ppcf128, Expand);
 
   // PowerPC has no SREM/UREM instructions unless we are on P9
   // On P9 we may use a hardware instruction to compute the remainder.

   // rather than use the remainder instruction. The instructions are legalized
   // directly because the DivRemPairsPass performs the transformation at the IR
   // level.
-  if (Subtarget.isISA3_0()) {
-    setOperationAction(ISD::SREM, MVT::i32, Legal);
-    setOperationAction(ISD::UREM, MVT::i32, Legal);
-    setOperationAction(ISD::SREM, MVT::i64, Legal);
-    setOperationAction(ISD::UREM, MVT::i64, Legal);
-  } else {
-    setOperationAction(ISD::SREM, MVT::i32, Expand);
-    setOperationAction(ISD::UREM, MVT::i32, Expand);
-    setOperationAction(ISD::SREM, MVT::i64, Expand);
-    setOperationAction(ISD::UREM, MVT::i64, Expand);
-  }
+  if (Subtarget.isISA3_0())
+    setOperationAction({ISD::SREM, ISD::UREM}, {MVT::i32, MVT::i64}, Legal);
+  else
+    setOperationAction({ISD::SREM, ISD::UREM}, {MVT::i32, MVT::i64}, Expand);
 
   // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
-  setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
-  setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
-  setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
-  setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
-  setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
-  setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
-  setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
-  setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
+  setOperationAction(
+      {ISD::UMUL_LOHI, ISD::SMUL_LOHI, ISD::UDIVREM, ISD::SDIVREM},
+      {MVT::i32, MVT::i64}, Expand);
 
   // Handle constrained floating-point operations of scalar.
   // TODO: Handle SPE specific operation.
-  setOperationAction(ISD::STRICT_FADD, MVT::f32, Legal);
-  setOperationAction(ISD::STRICT_FSUB, MVT::f32, Legal);
-  setOperationAction(ISD::STRICT_FMUL, MVT::f32, Legal);
-  setOperationAction(ISD::STRICT_FDIV, MVT::f32, Legal);
+  setOperationAction(
+      {ISD::STRICT_FADD, ISD::STRICT_FSUB, ISD::STRICT_FMUL, ISD::STRICT_FDIV},
+      {MVT::f32, MVT::f64}, Legal);
   setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Legal);
 
-  setOperationAction(ISD::STRICT_FADD, MVT::f64, Legal);
-  setOperationAction(ISD::STRICT_FSUB, MVT::f64, Legal);
-  setOperationAction(ISD::STRICT_FMUL, MVT::f64, Legal);
-  setOperationAction(ISD::STRICT_FDIV, MVT::f64, Legal);
-
-  if (!Subtarget.hasSPE()) {
-    setOperationAction(ISD::STRICT_FMA, MVT::f32, Legal);
-    setOperationAction(ISD::STRICT_FMA, MVT::f64, Legal);
-  }
-
-  if (Subtarget.hasVSX()) {
-    setOperationAction(ISD::STRICT_FRINT, MVT::f32, Legal);
-    setOperationAction(ISD::STRICT_FRINT, MVT::f64, Legal);
-  }
+  if (!Subtarget.hasSPE())
+    setOperationAction(ISD::STRICT_FMA, {MVT::f32, MVT::f64}, Legal);
 
-  if (Subtarget.hasFSQRT()) {
-    setOperationAction(ISD::STRICT_FSQRT, MVT::f32, Legal);
-    setOperationAction(ISD::STRICT_FSQRT, MVT::f64, Legal);
-  }
+  if (Subtarget.hasVSX())
+    setOperationAction(ISD::STRICT_FRINT, {MVT::f32, MVT::f64}, Legal);
 
-  if (Subtarget.hasFPRND()) {
-    setOperationAction(ISD::STRICT_FFLOOR, MVT::f32, Legal);
-    setOperationAction(ISD::STRICT_FCEIL,  MVT::f32, Legal);
-    setOperationAction(ISD::STRICT_FTRUNC, MVT::f32, Legal);
-    setOperationAction(ISD::STRICT_FROUND, MVT::f32, Legal);
+  if (Subtarget.hasFSQRT())
+    setOperationAction(ISD::STRICT_FSQRT, {MVT::f32, MVT::f64}, Legal);
 
-    setOperationAction(ISD::STRICT_FFLOOR, MVT::f64, Legal);
-    setOperationAction(ISD::STRICT_FCEIL,  MVT::f64, Legal);
-    setOperationAction(ISD::STRICT_FTRUNC, MVT::f64, Legal);
-    setOperationAction(ISD::STRICT_FROUND, MVT::f64, Legal);
-  }
+  if (Subtarget.hasFPRND())
+    setOperationAction({ISD::STRICT_FFLOOR, ISD::STRICT_FCEIL,
+                        ISD::STRICT_FTRUNC, ISD::STRICT_FROUND},
+                       {MVT::f32, MVT::f64}, Legal);
 
   // We don't support sin/cos/sqrt/fmod/pow
-  setOperationAction(ISD::FSIN , MVT::f64, Expand);
-  setOperationAction(ISD::FCOS , MVT::f64, Expand);
-  setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
-  setOperationAction(ISD::FREM , MVT::f64, Expand);
-  setOperationAction(ISD::FPOW , MVT::f64, Expand);
-  setOperationAction(ISD::FSIN , MVT::f32, Expand);
-  setOperationAction(ISD::FCOS , MVT::f32, Expand);
-  setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
-  setOperationAction(ISD::FREM , MVT::f32, Expand);
-  setOperationAction(ISD::FPOW , MVT::f32, Expand);
+  setOperationAction({ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FREM, ISD::FPOW},
+                     {MVT::f64, MVT::f32}, Expand);
 
   // MASS transformation for LLVM intrinsics with replicating fast-math flag
   // to be consistent to PPCGenScalarMASSEntries pass
   if (TM.getOptLevel() == CodeGenOpt::Aggressive &&
-      TM.Options.PPCGenScalarMASSEntries) {
-    setOperationAction(ISD::FSIN , MVT::f64, Custom);
-    setOperationAction(ISD::FCOS , MVT::f64, Custom);
-    setOperationAction(ISD::FPOW , MVT::f64, Custom);
-    setOperationAction(ISD::FLOG, MVT::f64, Custom);
-    setOperationAction(ISD::FLOG10, MVT::f64, Custom);
-    setOperationAction(ISD::FEXP, MVT::f64, Custom);
-    setOperationAction(ISD::FSIN , MVT::f32, Custom);
-    setOperationAction(ISD::FCOS , MVT::f32, Custom);
-    setOperationAction(ISD::FPOW , MVT::f32, Custom);
-    setOperationAction(ISD::FLOG, MVT::f32, Custom);
-    setOperationAction(ISD::FLOG10, MVT::f32, Custom);
-    setOperationAction(ISD::FEXP, MVT::f32, Custom);
-  }
+      TM.Options.PPCGenScalarMASSEntries)
+    setOperationAction(
+        {ISD::FSIN, ISD::FCOS, ISD::FPOW, ISD::FLOG, ISD::FLOG10, ISD::FEXP},
+        {MVT::f64, MVT::f32}, Custom);
 
-  if (Subtarget.hasSPE()) {
-    setOperationAction(ISD::FMA  , MVT::f64, Expand);
-    setOperationAction(ISD::FMA  , MVT::f32, Expand);
-  } else {
-    setOperationAction(ISD::FMA  , MVT::f64, Legal);
-    setOperationAction(ISD::FMA  , MVT::f32, Legal);
-  }
+  if (Subtarget.hasSPE())
+    setOperationAction(ISD::FMA, {MVT::f64, MVT::f32}, Expand);
+  else
+    setOperationAction(ISD::FMA, {MVT::f64, MVT::f32}, Legal);
 
   if (Subtarget.hasSPE())
     setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);

         Subtarget.hasFRES()))
     setOperationAction(ISD::FSQRT, MVT::f32, Expand);
 
-  if (Subtarget.hasFCPSGN()) {
-    setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
-    setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
-  } else {
-    setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
-    setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
-  }
-
-  if (Subtarget.hasFPRND()) {
-    setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
-    setOperationAction(ISD::FCEIL,  MVT::f64, Legal);
-    setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
-    setOperationAction(ISD::FROUND, MVT::f64, Legal);
+  if (Subtarget.hasFCPSGN())
+    setOperationAction(ISD::FCOPYSIGN, {MVT::f64, MVT::f32}, Legal);
+  else
+    setOperationAction(ISD::FCOPYSIGN, {MVT::f64, MVT::f32}, Expand);
 
-    setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
-    setOperationAction(ISD::FCEIL,  MVT::f32, Legal);
-    setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
-    setOperationAction(ISD::FROUND, MVT::f32, Legal);
-  }
+  if (Subtarget.hasFPRND())
+    setOperationAction({ISD::FFLOOR, ISD::FCEIL, ISD::FTRUNC, ISD::FROUND},
+                       {MVT::f64, MVT::f32}, Legal);
 
-  // PowerPC does not have BSWAP, but we can use vector BSWAP instruction xxbrd
-  // to speed up scalar BSWAP64.
-  // CTPOP or CTTZ were introduced in P8/P9 respectively
-  setOperationAction(ISD::BSWAP, MVT::i32  , Expand);
+  // PowerPC does not have BSWAP, but we can use vector BSWAP instruction
+  // xxbrd to speed up scalar BSWAP64. CTPOP or CTTZ were introduced in P8/P9
+  // respectively
+  setOperationAction(ISD::BSWAP, MVT::i32, Expand);
   if (Subtarget.hasP9Vector() && Subtarget.isPPC64())
-    setOperationAction(ISD::BSWAP, MVT::i64  , Custom);
+    setOperationAction(ISD::BSWAP, MVT::i64, Custom);
   else
-    setOperationAction(ISD::BSWAP, MVT::i64  , Expand);
-  if (Subtarget.isISA3_0()) {
-    setOperationAction(ISD::CTTZ , MVT::i32  , Legal);
-    setOperationAction(ISD::CTTZ , MVT::i64  , Legal);
-  } else {
-    setOperationAction(ISD::CTTZ , MVT::i32  , Expand);
-    setOperationAction(ISD::CTTZ , MVT::i64  , Expand);
-  }
+    setOperationAction(ISD::BSWAP, MVT::i64, Expand);
 
-  if (Subtarget.hasPOPCNTD() == PPCSubtarget::POPCNTD_Fast) {
-    setOperationAction(ISD::CTPOP, MVT::i32  , Legal);
-    setOperationAction(ISD::CTPOP, MVT::i64  , Legal);
-  } else {
-    setOperationAction(ISD::CTPOP, MVT::i32  , Expand);
-    setOperationAction(ISD::CTPOP, MVT::i64  , Expand);
-  }
+  if (Subtarget.isISA3_0())
+    setOperationAction(ISD::CTTZ, {MVT::i32, MVT::i64}, Legal);
+  else
+    setOperationAction(ISD::CTTZ, {MVT::i32, MVT::i64}, Expand);
+
+  if (Subtarget.hasPOPCNTD() == PPCSubtarget::POPCNTD_Fast)
+    setOperationAction(ISD::CTPOP, {MVT::i32, MVT::i64}, Legal);
+  else
+    setOperationAction(ISD::CTPOP, {MVT::i32, MVT::i64}, Expand);
 
   // PowerPC does not have ROTR
-  setOperationAction(ISD::ROTR, MVT::i32   , Expand);
-  setOperationAction(ISD::ROTR, MVT::i64   , Expand);
+  setOperationAction(ISD::ROTR, {MVT::i32, MVT::i64}, Expand);
 
-  if (!Subtarget.useCRBits()) {
+  if (!Subtarget.useCRBits())
     // PowerPC does not have Select
-    setOperationAction(ISD::SELECT, MVT::i32, Expand);
-    setOperationAction(ISD::SELECT, MVT::i64, Expand);
-    setOperationAction(ISD::SELECT, MVT::f32, Expand);
-    setOperationAction(ISD::SELECT, MVT::f64, Expand);
-  }
+    setOperationAction(ISD::SELECT, {MVT::i32, MVT::i64, MVT::f32, MVT::f64},
+                       Expand);
 
   // PowerPC wants to turn select_cc of FP into fsel when possible.
-  setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
-  setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
+  setOperationAction(ISD::SELECT_CC, {MVT::f32, MVT::f64}, Custom);
 
   // PowerPC wants to optimize integer setcc a bit
   if (!Subtarget.useCRBits())
     setOperationAction(ISD::SETCC, MVT::i32, Custom);
 
   if (Subtarget.hasFPU()) {
-    setOperationAction(ISD::STRICT_FSETCC, MVT::f32, Legal);
-    setOperationAction(ISD::STRICT_FSETCC, MVT::f64, Legal);
-    setOperationAction(ISD::STRICT_FSETCC, MVT::f128, Legal);
+    setOperationAction(ISD::STRICT_FSETCC, {MVT::f32, MVT::f64, MVT::f128},
+                       Legal);
 
-    setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Legal);
-    setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Legal);
-    setOperationAction(ISD::STRICT_FSETCCS, MVT::f128, Legal);
+    setOperationAction(ISD::STRICT_FSETCCS, {MVT::f32, MVT::f64, MVT::f128},
+                       Legal);
   }
 
   // PowerPC does not have BRCOND which requires SetCC

 
   if (Subtarget.hasSPE()) {
     // SPE has built-in conversions
-    setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Legal);
-    setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Legal);
-    setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i32, Legal);
-    setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
-    setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
-    setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
+    setOperationAction({ISD::STRICT_FP_TO_SINT, ISD::STRICT_SINT_TO_FP,
+                        ISD::STRICT_UINT_TO_FP, ISD::FP_TO_SINT,
+                        ISD::SINT_TO_FP, ISD::UINT_TO_FP},
+                       MVT::i32, Legal);
 
     // SPE supports signaling compare of f32/f64.
-    setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Legal);
-    setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Legal);
+    setOperationAction(ISD::STRICT_FSETCCS, {MVT::f32, MVT::f64}, Legal);
   } else {
     // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
-    setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
-    setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
+    setOperationAction({ISD::STRICT_FP_TO_SINT, ISD::FP_TO_SINT}, MVT::i32,
+                       Custom);
 
     // PowerPC does not have [U|S]INT_TO_FP
-    setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Expand);
-    setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i32, Expand);
-    setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
-    setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
+    setOperationAction({ISD::STRICT_SINT_TO_FP, ISD::STRICT_UINT_TO_FP,
+                        ISD::SINT_TO_FP, ISD::UINT_TO_FP},
+                       MVT::i32, Expand);
   }
 
   if (Subtarget.hasDirectMove() && isPPC64) {
-    setOperationAction(ISD::BITCAST, MVT::f32, Legal);
-    setOperationAction(ISD::BITCAST, MVT::i32, Legal);
-    setOperationAction(ISD::BITCAST, MVT::i64, Legal);
-    setOperationAction(ISD::BITCAST, MVT::f64, Legal);
-    if (TM.Options.UnsafeFPMath) {
-      setOperationAction(ISD::LRINT, MVT::f64, Legal);
-      setOperationAction(ISD::LRINT, MVT::f32, Legal);
-      setOperationAction(ISD::LLRINT, MVT::f64, Legal);
-      setOperationAction(ISD::LLRINT, MVT::f32, Legal);
-      setOperationAction(ISD::LROUND, MVT::f64, Legal);
-      setOperationAction(ISD::LROUND, MVT::f32, Legal);
-      setOperationAction(ISD::LLROUND, MVT::f64, Legal);
-      setOperationAction(ISD::LLROUND, MVT::f32, Legal);
-    }
-  } else {
-    setOperationAction(ISD::BITCAST, MVT::f32, Expand);
-    setOperationAction(ISD::BITCAST, MVT::i32, Expand);
-    setOperationAction(ISD::BITCAST, MVT::i64, Expand);
-    setOperationAction(ISD::BITCAST, MVT::f64, Expand);
-  }
+    setOperationAction(ISD::BITCAST, {MVT::f32, MVT::i32, MVT::i64, MVT::f64},
+                       Legal);
+    if (TM.Options.UnsafeFPMath)
+      setOperationAction({ISD::LRINT, ISD::LLRINT, ISD::LROUND, ISD::LLROUND},
+                         {MVT::f64, MVT::f32}, Legal);
+  } else
+    setOperationAction(ISD::BITCAST, {MVT::f32, MVT::i32, MVT::i64, MVT::f64},
+                       Expand);
 
   // We cannot sextinreg(i1).  Expand to shifts.
   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);

 
   // We want to legalize GlobalAddress and ConstantPool nodes into the
   // appropriate instructions to materialize the address.
-  setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
-  setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
-  setOperationAction(ISD::BlockAddress,  MVT::i32, Custom);
-  setOperationAction(ISD::ConstantPool,  MVT::i32, Custom);
-  setOperationAction(ISD::JumpTable,     MVT::i32, Custom);
-  setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
-  setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
-  setOperationAction(ISD::BlockAddress,  MVT::i64, Custom);
-  setOperationAction(ISD::ConstantPool,  MVT::i64, Custom);
-  setOperationAction(ISD::JumpTable,     MVT::i64, Custom);
+  setOperationAction({ISD::GlobalAddress, ISD::GlobalTLSAddress,
+                      ISD::BlockAddress, ISD::ConstantPool, ISD::JumpTable},
+                     {MVT::i32, MVT::i64}, Custom);
 
   // TRAP is legal.
   setOperationAction(ISD::TRAP, MVT::Other, Legal);
 
   // TRAMPOLINE is custom lowered.
-  setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
-  setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
+  setOperationAction({ISD::INIT_TRAMPOLINE, ISD::ADJUST_TRAMPOLINE}, MVT::Other,
+                     Custom);
 
   // VASTART needs to be custom lowered to use the VarArgsFrameIndex
   setOperationAction(ISD::VASTART           , MVT::Other, Custom);

     setOperationAction(ISD::VAARG, MVT::i32, Promote);
     AddPromotedToType(ISD::VAARG, MVT::i32, MVT::i64);
     setOperationAction(ISD::VAARG, MVT::Other, Expand);
-  } else if (Subtarget.is32BitELFABI()) {
+  } else if (Subtarget.is32BitELFABI())
     // VAARG is custom lowered with the 32-bit SVR4 ABI.
-    setOperationAction(ISD::VAARG, MVT::Other, Custom);
-    setOperationAction(ISD::VAARG, MVT::i64, Custom);
-  } else
+    setOperationAction(ISD::VAARG, {MVT::Other, MVT::i64}, Custom);
+  else
     setOperationAction(ISD::VAARG, MVT::Other, Expand);
 
   // VACOPY is custom lowered with the 32-bit SVR4 ABI.

     setOperationAction(ISD::VACOPY            , MVT::Other, Expand);
 
   // Use the default implementation.
-  setOperationAction(ISD::VAEND             , MVT::Other, Expand);
-  setOperationAction(ISD::STACKSAVE         , MVT::Other, Expand);
+  setOperationAction({ISD::VAEND, ISD::STACKSAVE}, MVT::Other, Expand);
   setOperationAction(ISD::STACKRESTORE      , MVT::Other, Custom);
-  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32  , Custom);
-  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64  , Custom);
-  setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, MVT::i32, Custom);
-  setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, MVT::i64, Custom);
-  setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom);
-  setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom);
+  setOperationAction({ISD::DYNAMIC_STACKALLOC, ISD::GET_DYNAMIC_AREA_OFFSET,
+                      ISD::EH_DWARF_CFA},
+                     {MVT::i32, MVT::i64}, Custom);
 
   // We want to custom lower some of our intrinsics.
-  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
-  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f64, Custom);
-  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::ppcf128, Custom);
-  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v4f32, Custom);
-  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v2f64, Custom);
+  setOperationAction(
+      ISD::INTRINSIC_WO_CHAIN,
+      {MVT::Other, MVT::f64, MVT::ppcf128, MVT::v4f32, MVT::v2f64}, Custom);
 
   // To handle counter-based loop conditions.
   setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
 
-  setOperationAction(ISD::INTRINSIC_VOID, MVT::i8, Custom);
-  setOperationAction(ISD::INTRINSIC_VOID, MVT::i16, Custom);
-  setOperationAction(ISD::INTRINSIC_VOID, MVT::i32, Custom);
-  setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
+  setOperationAction(ISD::INTRINSIC_VOID,
+                     {MVT::i8, MVT::i16, MVT::i32, MVT::Other}, Custom);
 
   // Comparisons that require checking two conditions.
-  if (Subtarget.hasSPE()) {
-    setCondCodeAction(ISD::SETO, MVT::f32, Expand);
-    setCondCodeAction(ISD::SETO, MVT::f64, Expand);
-    setCondCodeAction(ISD::SETUO, MVT::f32, Expand);
-    setCondCodeAction(ISD::SETUO, MVT::f64, Expand);
-  }
-  setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
-  setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
-  setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
-  setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
-  setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
-  setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
-  setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
-  setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
-  setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
-  setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
-  setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
-  setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
-
-  setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f32, Legal);
-  setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f64, Legal);
+  if (Subtarget.hasSPE())
+    setCondCodeAction({ISD::SETO, ISD::SETUO}, {MVT::f32, MVT::f64}, Expand);
+  setCondCodeAction({ISD::SETULT, ISD::SETUGT, ISD::SETUEQ, ISD::SETOGE,
+                     ISD::SETOLE, ISD::SETONE},
+                    {MVT::f32, MVT::f64}, Expand);
+
+  setOperationAction(ISD::STRICT_FP_EXTEND, {MVT::f32, MVT::f64}, Legal);
 
   if (Subtarget.has64BitSupport()) {
     // They also have instructions for converting between i64 and fp.
-    setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i64, Custom);
-    setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i64, Expand);
-    setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i64, Custom);
-    setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i64, Expand);
-    setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
-    setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
-    setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
-    setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
+    setOperationAction({ISD::STRICT_FP_TO_SINT, ISD::STRICT_SINT_TO_FP,
+                        ISD::FP_TO_SINT, ISD::SINT_TO_FP},
+                       MVT::i64, Custom);
+    setOperationAction({ISD::STRICT_FP_TO_UINT, ISD::STRICT_UINT_TO_FP,
+                        ISD::FP_TO_UINT, ISD::UINT_TO_FP},
+                       MVT::i64, Expand);
     // This is just the low 32 bits of a (signed) fp->i64 conversion.
     // We cannot do this with Promote because i64 is not a legal type.
-    setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
-    setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
+    setOperationAction({ISD::STRICT_FP_TO_UINT, ISD::FP_TO_UINT}, MVT::i32,
+                       Custom);
 
-    if (Subtarget.hasLFIWAX() || Subtarget.isPPC64()) {
-      setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
-      setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Custom);
-    }
+    if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
+      setOperationAction({ISD::SINT_TO_FP, ISD::STRICT_SINT_TO_FP}, MVT::i32,
+                         Custom);
   } else {
     // PowerPC does not have FP_TO_UINT on 32-bit implementations.
-    if (Subtarget.hasSPE()) {
-      setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Legal);
-      setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
-    } else {
-      setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Expand);
-      setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
-    }
+    if (Subtarget.hasSPE())
+      setOperationAction({ISD::STRICT_FP_TO_UINT, ISD::FP_TO_UINT}, MVT::i32,
+                         Legal);
+    else
+      setOperationAction({ISD::STRICT_FP_TO_UINT, ISD::FP_TO_UINT}, MVT::i32,
+                         Expand);
   }
 
   // With the instructions enabled under FPCVT, we can do everything.
   if (Subtarget.hasFPCVT()) {
-    if (Subtarget.has64BitSupport()) {
-      setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i64, Custom);
-      setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i64, Custom);
-      setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i64, Custom);
-      setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i64, Custom);
-      setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
-      setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
-      setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
-      setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
-    }
+    if (Subtarget.has64BitSupport())
+      setOperationAction({ISD::STRICT_FP_TO_SINT, ISD::STRICT_FP_TO_UINT,
+                          ISD::STRICT_SINT_TO_FP, ISD::STRICT_UINT_TO_FP,
+                          ISD::FP_TO_SINT, ISD::FP_TO_UINT, ISD::SINT_TO_FP,
+                          ISD::UINT_TO_FP},
+                         MVT::i64, Custom);
 
-    setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
-    setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
-    setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Custom);
-    setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i32, Custom);
-    setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
-    setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
-    setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
-    setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
+    setOperationAction({ISD::STRICT_FP_TO_SINT, ISD::STRICT_FP_TO_UINT,
+                        ISD::STRICT_SINT_TO_FP, ISD::STRICT_UINT_TO_FP,
+                        ISD::FP_TO_SINT, ISD::FP_TO_UINT, ISD::SINT_TO_FP,
+                        ISD::UINT_TO_FP},
+                       MVT::i32, Custom);
   }
 
   if (Subtarget.use64BitRegs()) {

     // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
     setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
     // 64-bit PowerPC wants to expand i128 shifts itself.
-    setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
-    setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
-    setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
-  } else {
+    setOperationAction({ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS},
+                       MVT::i64, Custom);
+  } else
     // 32-bit PowerPC wants to expand i64 shifts itself.
-    setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
-    setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
-    setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
-  }
+    setOperationAction({ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS},
+                       MVT::i32, Custom);
 
   // PowerPC has better expansions for funnel shifts than the generic
   // TargetLowering::expandFunnelShift.
-  if (Subtarget.has64BitSupport()) {
-    setOperationAction(ISD::FSHL, MVT::i64, Custom);
-    setOperationAction(ISD::FSHR, MVT::i64, Custom);
-  }
-  setOperationAction(ISD::FSHL, MVT::i32, Custom);
-  setOperationAction(ISD::FSHR, MVT::i32, Custom);
+  if (Subtarget.has64BitSupport())
+    setOperationAction({ISD::FSHL, ISD::FSHR}, MVT::i64, Custom);
+  setOperationAction({ISD::FSHL, ISD::FSHR}, MVT::i32, Custom);
 
-  if (Subtarget.hasVSX()) {
-    setOperationAction(ISD::FMAXNUM_IEEE, MVT::f64, Legal);
-    setOperationAction(ISD::FMAXNUM_IEEE, MVT::f32, Legal);
-    setOperationAction(ISD::FMINNUM_IEEE, MVT::f64, Legal);
-    setOperationAction(ISD::FMINNUM_IEEE, MVT::f32, Legal);
-  }
+  if (Subtarget.hasVSX())
+    setOperationAction({ISD::FMAXNUM_IEEE, ISD::FMINNUM_IEEE},
+                       {MVT::f64, MVT::f32}, Legal);
 
   if (Subtarget.hasAltivec()) {
-    for (MVT VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
-      setOperationAction(ISD::SADDSAT, VT, Legal);
-      setOperationAction(ISD::SSUBSAT, VT, Legal);
-      setOperationAction(ISD::UADDSAT, VT, Legal);
-      setOperationAction(ISD::USUBSAT, VT, Legal);
-    }
+    setOperationAction({ISD::SADDSAT, ISD::SSUBSAT, ISD::UADDSAT, ISD::USUBSAT},
+                       {MVT::v16i8, MVT::v8i16, MVT::v4i32}, Legal);
     // First set operation action for all vector types to expand. Then we
     // will selectively turn on ones that can be effectively codegen'd.
     for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
       // add/sub are legal for all supported vector VT's.
-      setOperationAction(ISD::ADD, VT, Legal);
-      setOperationAction(ISD::SUB, VT, Legal);
+      setOperationAction({ISD::ADD, ISD::SUB}, VT, Legal);
 
       // For v2i64, these are only valid with P8Vector. This is corrected after
       // the loop.
-      if (VT.getSizeInBits() <= 128 && VT.getScalarSizeInBits() <= 64) {
-        setOperationAction(ISD::SMAX, VT, Legal);
-        setOperationAction(ISD::SMIN, VT, Legal);
-        setOperationAction(ISD::UMAX, VT, Legal);
-        setOperationAction(ISD::UMIN, VT, Legal);
-      }
-      else {
-        setOperationAction(ISD::SMAX, VT, Expand);
-        setOperationAction(ISD::SMIN, VT, Expand);
-        setOperationAction(ISD::UMAX, VT, Expand);
-        setOperationAction(ISD::UMIN, VT, Expand);
-      }
+      if (VT.getSizeInBits() <= 128 && VT.getScalarSizeInBits() <= 64)
+        setOperationAction({ISD::SMAX, ISD::SMIN, ISD::UMAX, ISD::UMIN}, VT,
+                           Legal);
+      else
+        setOperationAction({ISD::SMAX, ISD::SMIN, ISD::UMAX, ISD::UMIN}, VT,
+                           Expand);
 
-      if (Subtarget.hasVSX()) {
-        setOperationAction(ISD::FMAXNUM, VT, Legal);
-        setOperationAction(ISD::FMINNUM, VT, Legal);
-      }
+      if (Subtarget.hasVSX())
+        setOperationAction({ISD::FMAXNUM, ISD::FMINNUM}, VT, Legal);
 
       // Vector instructions introduced in P8
-      if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) {
-        setOperationAction(ISD::CTPOP, VT, Legal);
-        setOperationAction(ISD::CTLZ, VT, Legal);
-      }
-      else {
-        setOperationAction(ISD::CTPOP, VT, Expand);
-        setOperationAction(ISD::CTLZ, VT, Expand);
-      }
+      if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128))
+        setOperationAction({ISD::CTPOP, ISD::CTLZ}, VT, Legal);
+      else
+        setOperationAction({ISD::CTPOP, ISD::CTLZ}, VT, Expand);
 
       // Vector instructions introduced in P9
       if (Subtarget.hasP9Altivec() && (VT.SimpleTy != MVT::v1i128))

       AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
 
       // No other operations are legal.
-      setOperationAction(ISD::MUL , VT, Expand);
-      setOperationAction(ISD::SDIV, VT, Expand);
-      setOperationAction(ISD::SREM, VT, Expand);
-      setOperationAction(ISD::UDIV, VT, Expand);
-      setOperationAction(ISD::UREM, VT, Expand);
-      setOperationAction(ISD::FDIV, VT, Expand);
-      setOperationAction(ISD::FREM, VT, Expand);
-      setOperationAction(ISD::FNEG, VT, Expand);
-      setOperationAction(ISD::FSQRT, VT, Expand);
-      setOperationAction(ISD::FLOG, VT, Expand);
-      setOperationAction(ISD::FLOG10, VT, Expand);
-      setOperationAction(ISD::FLOG2, VT, Expand);
-      setOperationAction(ISD::FEXP, VT, Expand);
-      setOperationAction(ISD::FEXP2, VT, Expand);
-      setOperationAction(ISD::FSIN, VT, Expand);
-      setOperationAction(ISD::FCOS, VT, Expand);
-      setOperationAction(ISD::FABS, VT, Expand);
-      setOperationAction(ISD::FFLOOR, VT, Expand);
-      setOperationAction(ISD::FCEIL,  VT, Expand);
-      setOperationAction(ISD::FTRUNC, VT, Expand);
-      setOperationAction(ISD::FRINT,  VT, Expand);
-      setOperationAction(ISD::FNEARBYINT, VT, Expand);
-      setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
-      setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
-      setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
-      setOperationAction(ISD::MULHU, VT, Expand);
-      setOperationAction(ISD::MULHS, VT, Expand);
-      setOperationAction(ISD::UMUL_LOHI, VT, Expand);
-      setOperationAction(ISD::SMUL_LOHI, VT, Expand);
-      setOperationAction(ISD::UDIVREM, VT, Expand);
-      setOperationAction(ISD::SDIVREM, VT, Expand);
-      setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
-      setOperationAction(ISD::FPOW, VT, Expand);
-      setOperationAction(ISD::BSWAP, VT, Expand);
-      setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
-      setOperationAction(ISD::ROTL, VT, Expand);
-      setOperationAction(ISD::ROTR, VT, Expand);
+      setOperationAction({ISD::MUL,
+                          ISD::SDIV,
+                          ISD::SREM,
+                          ISD::UDIV,
+                          ISD::UREM,
+                          ISD::FDIV,
+                          ISD::FREM,
+                          ISD::FNEG,
+                          ISD::FSQRT,
+                          ISD::FLOG,
+                          ISD::FLOG10,
+                          ISD::FLOG2,
+                          ISD::FEXP,
+                          ISD::FEXP2,
+                          ISD::FSIN,
+                          ISD::FCOS,
+                          ISD::FABS,
+                          ISD::FFLOOR,
+                          ISD::FCEIL,
+                          ISD::FTRUNC,
+                          ISD::FRINT,
+                          ISD::FNEARBYINT,
+                          ISD::EXTRACT_VECTOR_ELT,
+                          ISD::INSERT_VECTOR_ELT,
+                          ISD::BUILD_VECTOR,
+                          ISD::MULHU,
+                          ISD::MULHS,
+                          ISD::UMUL_LOHI,
+                          ISD::SMUL_LOHI,
+                          ISD::UDIVREM,
+                          ISD::SDIVREM,
+                          ISD::SCALAR_TO_VECTOR,
+                          ISD::FPOW,
+                          ISD::BSWAP,
+                          ISD::SIGN_EXTEND_INREG,
+                          ISD::ROTL,
+                          ISD::ROTR},
+                         VT, Expand);
 
       for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) {
         setTruncStoreAction(VT, InnerVT, Expand);
-        setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
-        setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
-        setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
+        setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, VT,
+                         InnerVT, Expand);
       }
     }
     setOperationAction(ISD::SELECT_CC, MVT::v4i32, Expand);
-    if (!Subtarget.hasP8Vector()) {
-      setOperationAction(ISD::SMAX, MVT::v2i64, Expand);
-      setOperationAction(ISD::SMIN, MVT::v2i64, Expand);
-      setOperationAction(ISD::UMAX, MVT::v2i64, Expand);
-      setOperationAction(ISD::UMIN, MVT::v2i64, Expand);
-    }
+    if (!Subtarget.hasP8Vector())
+      setOperationAction({ISD::SMAX, ISD::SMIN, ISD::UMAX, ISD::UMIN},
+                         MVT::v2i64, Expand);
 
     // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
     // with merges, splats, etc.

 
     // Vector truncates to sub-word integer that fit in an Altivec/VSX register
     // are cheap, so handle them before they get expanded to scalar.
-    setOperationAction(ISD::TRUNCATE, MVT::v8i8, Custom);
-    setOperationAction(ISD::TRUNCATE, MVT::v4i8, Custom);
-    setOperationAction(ISD::TRUNCATE, MVT::v2i8, Custom);
-    setOperationAction(ISD::TRUNCATE, MVT::v4i16, Custom);
-    setOperationAction(ISD::TRUNCATE, MVT::v2i16, Custom);
-
-    setOperationAction(ISD::AND   , MVT::v4i32, Legal);
-    setOperationAction(ISD::OR    , MVT::v4i32, Legal);
-    setOperationAction(ISD::XOR   , MVT::v4i32, Legal);
-    setOperationAction(ISD::LOAD  , MVT::v4i32, Legal);
+    setOperationAction(
+        ISD::TRUNCATE,
+        {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MVT::v2i16}, Custom);
+
+    setOperationAction({ISD::AND, ISD::OR, ISD::XOR, ISD::LOAD}, MVT::v4i32,
+                       Legal);
     setOperationAction(ISD::SELECT, MVT::v4i32,
                        Subtarget.useCRBits() ? Legal : Expand);
-    setOperationAction(ISD::STORE , MVT::v4i32, Legal);
-    setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v4i32, Legal);
-    setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v4i32, Legal);
-    setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i32, Legal);
-    setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i32, Legal);
-    setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
-    setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
-    setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
-    setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
-    setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
-    setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
-    setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
-    setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
+    setOperationAction({ISD::STORE, ISD::STRICT_FP_TO_SINT,
+                        ISD::STRICT_FP_TO_UINT, ISD::STRICT_SINT_TO_FP,
+                        ISD::STRICT_UINT_TO_FP, ISD::FP_TO_SINT,
+                        ISD::FP_TO_UINT, ISD::SINT_TO_FP, ISD::UINT_TO_FP},
+                       MVT::v4i32, Legal);
+    setOperationAction({ISD::FFLOOR, ISD::FCEIL, ISD::FTRUNC, ISD::FNEARBYINT},
+                       MVT::v4f32, Legal);
 
     // Custom lowering ROTL v1i128 to VECTOR_SHUFFLE v16i8.
     setOperationAction(ISD::ROTL, MVT::v1i128, Custom);
     // With hasAltivec set, we can lower ISD::ROTL to vrl(b|h|w).
     if (Subtarget.hasAltivec())
-      for (auto VT : {MVT::v4i32, MVT::v8i16, MVT::v16i8})
-        setOperationAction(ISD::ROTL, VT, Legal);
+      setOperationAction(ISD::ROTL, {MVT::v4i32, MVT::v8i16, MVT::v16i8},
+                         Legal);
     // With hasP8Altivec set, we can lower ISD::ROTL to vrld.
     if (Subtarget.hasP8Altivec())
       setOperationAction(ISD::ROTL, MVT::v2i64, Legal);

     addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
     addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
 
-    setOperationAction(ISD::MUL, MVT::v4f32, Legal);
-    setOperationAction(ISD::FMA, MVT::v4f32, Legal);
+    setOperationAction({ISD::MUL, ISD::FMA}, MVT::v4f32, Legal);
 
     if (Subtarget.hasVSX()) {
-      setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
-      setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
+      setOperationAction({ISD::FDIV, ISD::FSQRT}, MVT::v4f32, Legal);
       setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
     }
 

 
     if (Subtarget.isISA3_1()) {
       setOperationAction(ISD::MUL, MVT::v2i64, Legal);
-      setOperationAction(ISD::MULHS, MVT::v2i64, Legal);
-      setOperationAction(ISD::MULHU, MVT::v2i64, Legal);
-      setOperationAction(ISD::MULHS, MVT::v4i32, Legal);
-      setOperationAction(ISD::MULHU, MVT::v4i32, Legal);
-      setOperationAction(ISD::UDIV, MVT::v2i64, Legal);
-      setOperationAction(ISD::SDIV, MVT::v2i64, Legal);
-      setOperationAction(ISD::UDIV, MVT::v4i32, Legal);
-      setOperationAction(ISD::SDIV, MVT::v4i32, Legal);
-      setOperationAction(ISD::UREM, MVT::v2i64, Legal);
-      setOperationAction(ISD::SREM, MVT::v2i64, Legal);
-      setOperationAction(ISD::UREM, MVT::v4i32, Legal);
-      setOperationAction(ISD::SREM, MVT::v4i32, Legal);
-      setOperationAction(ISD::UREM, MVT::v1i128, Legal);
-      setOperationAction(ISD::SREM, MVT::v1i128, Legal);
-      setOperationAction(ISD::UDIV, MVT::v1i128, Legal);
-      setOperationAction(ISD::SDIV, MVT::v1i128, Legal);
+      setOperationAction({ISD::MULHS, ISD::MULHU}, {MVT::v2i64, MVT::v4i32},
+                         Legal);
+      setOperationAction({ISD::UREM, ISD::SREM, ISD::UDIV, ISD::SDIV},
+                         {MVT::v2i64, MVT::v4i32, MVT::v1i128}, Legal);
       setOperationAction(ISD::ROTL, MVT::v1i128, Legal);
     }
 
     setOperationAction(ISD::MUL, MVT::v8i16, Legal);
     setOperationAction(ISD::MUL, MVT::v16i8, Custom);
 
-    setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
-    setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
+    setOperationAction(ISD::SCALAR_TO_VECTOR, {MVT::v4f32, MVT::v4i32}, Custom);
 
-    setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
-    setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
-    setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
-    setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
+    setOperationAction(ISD::BUILD_VECTOR,
+                       {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32},
+                       Custom);
 
     // Altivec does not contain unordered floating-point compare instructions
-    setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
-    setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
-    setCondCodeAction(ISD::SETO,   MVT::v4f32, Expand);
-    setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
+    setCondCodeAction({ISD::SETUO, ISD::SETUEQ, ISD::SETO, ISD::SETONE},
+                      MVT::v4f32, Expand);
 
     if (Subtarget.hasVSX()) {
-      setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
-      setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
-      if (Subtarget.hasP8Vector()) {
-        setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
-        setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Legal);
-      }
-      if (Subtarget.hasDirectMove() && isPPC64) {
-        setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal);
-        setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal);
-        setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Legal);
-        setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Legal);
-        setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Legal);
-        setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Legal);
-        setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal);
-        setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
-      }
+      setOperationAction({ISD::SCALAR_TO_VECTOR, ISD::EXTRACT_VECTOR_ELT},
+                         MVT::v2f64, Legal);
+      if (Subtarget.hasP8Vector())
+        setOperationAction({ISD::SCALAR_TO_VECTOR, ISD::EXTRACT_VECTOR_ELT},
+                           MVT::v4f32, Legal);
+      if (Subtarget.hasDirectMove() && isPPC64)
+        setOperationAction({ISD::SCALAR_TO_VECTOR, ISD::EXTRACT_VECTOR_ELT},
+                           {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64},
+                           Legal);
       setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
 
       // The nearbyint variants are not allowed to raise the inexact exception
       // so we can only code-gen them with unsafe math.
-      if (TM.Options.UnsafeFPMath) {
-        setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
-        setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
-      }
+      if (TM.Options.UnsafeFPMath)
+        setOperationAction(ISD::FNEARBYINT, {MVT::f64, MVT::f32}, Legal);
 
-      setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
-      setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
-      setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
-      setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
-      setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
-      setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
-      setOperationAction(ISD::FROUND, MVT::f64, Legal);
-      setOperationAction(ISD::FRINT, MVT::f64, Legal);
+      setOperationAction({ISD::FFLOOR, ISD::FCEIL, ISD::FTRUNC, ISD::FNEARBYINT,
+                          ISD::FRINT, ISD::FROUND},
+                         MVT::v2f64, Legal);
+      setOperationAction({ISD::FROUND, ISD::FRINT}, MVT::f64, Legal);
 
-      setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
-      setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
-      setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
-      setOperationAction(ISD::FROUND, MVT::f32, Legal);
-      setOperationAction(ISD::FRINT, MVT::f32, Legal);
+      setOperationAction({ISD::FNEARBYINT, ISD::FRINT, ISD::FROUND}, MVT::v4f32,
+                         Legal);
+      setOperationAction({ISD::FROUND, ISD::FRINT}, MVT::f32, Legal);
 
-      setOperationAction(ISD::MUL, MVT::v2f64, Legal);
-      setOperationAction(ISD::FMA, MVT::v2f64, Legal);
+      setOperationAction({ISD::MUL, ISD::FMA}, MVT::v2f64, Legal);
 
-      setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
-      setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
+      setOperationAction({ISD::FDIV, ISD::FSQRT}, MVT::v2f64, Legal);
 
       // Share the Altivec comparison restrictions.
-      setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
-      setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
-      setCondCodeAction(ISD::SETO,   MVT::v2f64, Expand);
-      setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
+      setCondCodeAction({ISD::SETUO, ISD::SETUEQ, ISD::SETO, ISD::SETONE},
+                        MVT::v2f64, Expand);
 
-      setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
-      setOperationAction(ISD::STORE, MVT::v2f64, Legal);
+      setOperationAction({ISD::LOAD, ISD::STORE}, MVT::v2f64, Legal);
 
       setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
 

       addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
 
       if (Subtarget.hasP8Altivec()) {
-        setOperationAction(ISD::SHL, MVT::v2i64, Legal);
-        setOperationAction(ISD::SRA, MVT::v2i64, Legal);
-        setOperationAction(ISD::SRL, MVT::v2i64, Legal);
+        setOperationAction({ISD::SHL, ISD::SRA, ISD::SRL}, MVT::v2i64, Legal);
 
         // 128 bit shifts can be accomplished via 3 instructions for SHL and
         // SRL, but not for SRA because of the instructions available:
         // VS{RL} and VS{RL}O. However due to direct move costs, it's not worth
         // doing
-        setOperationAction(ISD::SHL, MVT::v1i128, Expand);
-        setOperationAction(ISD::SRL, MVT::v1i128, Expand);
-        setOperationAction(ISD::SRA, MVT::v1i128, Expand);
+        setOperationAction({ISD::SHL, ISD::SRL, ISD::SRA}, MVT::v1i128, Expand);
 
         setOperationAction(ISD::SETCC, MVT::v2i64, Legal);
       }
       else {
-        setOperationAction(ISD::SHL, MVT::v2i64, Expand);
-        setOperationAction(ISD::SRA, MVT::v2i64, Expand);
-        setOperationAction(ISD::SRL, MVT::v2i64, Expand);
+        setOperationAction({ISD::SHL, ISD::SRA, ISD::SRL}, MVT::v2i64, Expand);
 
         setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
 
         // VSX v2i64 only supports non-arithmetic operations.
-        setOperationAction(ISD::ADD, MVT::v2i64, Expand);
-        setOperationAction(ISD::SUB, MVT::v2i64, Expand);
+        setOperationAction({ISD::ADD, ISD::SUB}, MVT::v2i64, Expand);
       }
 
       if (Subtarget.isISA3_1())

 
       setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
 
-      setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i64, Legal);
-      setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i64, Legal);
-      setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v2i64, Legal);
-      setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v2i64, Legal);
-      setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
-      setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
-      setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
-      setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
+      setOperationAction({ISD::STRICT_SINT_TO_FP, ISD::STRICT_UINT_TO_FP,
+                          ISD::STRICT_FP_TO_SINT, ISD::STRICT_FP_TO_UINT,
+                          ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_TO_SINT,
+                          ISD::FP_TO_UINT},
+                         MVT::v2i64, Legal);
 
       // Custom handling for partial vectors of integers converted to
       // floating point. We already have optimal handling for v2i32 through
       // the DAG combine, so those aren't necessary.
-      setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i8, Custom);
-      setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i8, Custom);
-      setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i16, Custom);
-      setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i16, Custom);
-      setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i8, Custom);
-      setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i8, Custom);
-      setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i16, Custom);
-      setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i16, Custom);
-      setOperationAction(ISD::UINT_TO_FP, MVT::v2i8, Custom);
-      setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
-      setOperationAction(ISD::UINT_TO_FP, MVT::v2i16, Custom);
-      setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
-      setOperationAction(ISD::SINT_TO_FP, MVT::v2i8, Custom);
-      setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Custom);
-      setOperationAction(ISD::SINT_TO_FP, MVT::v2i16, Custom);
-      setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
-
-      setOperationAction(ISD::FNEG, MVT::v4f32, Legal);
-      setOperationAction(ISD::FNEG, MVT::v2f64, Legal);
-      setOperationAction(ISD::FABS, MVT::v4f32, Legal);
-      setOperationAction(ISD::FABS, MVT::v2f64, Legal);
-      setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Legal);
-      setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Legal);
-
-      setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
-      setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
+      setOperationAction({ISD::STRICT_UINT_TO_FP, ISD::STRICT_SINT_TO_FP,
+                          ISD::UINT_TO_FP, ISD::SINT_TO_FP},
+                         {MVT::v2i8, MVT::v4i8, MVT::v2i16, MVT::v4i16},
+                         Custom);
+
+      setOperationAction({ISD::FNEG, ISD::FABS, ISD::FCOPYSIGN},
+                         {MVT::v4f32, MVT::v2f64}, Legal);
+
+      setOperationAction(ISD::BUILD_VECTOR, {MVT::v2i64, MVT::v2f64}, Custom);
 
       // Handle constrained floating-point operations of vector.
       // The predictor is `hasVSX` because altivec instruction has
       // no exception but VSX vector instruction has.
-      setOperationAction(ISD::STRICT_FADD, MVT::v4f32, Legal);
-      setOperationAction(ISD::STRICT_FSUB, MVT::v4f32, Legal);
-      setOperationAction(ISD::STRICT_FMUL, MVT::v4f32, Legal);
-      setOperationAction(ISD::STRICT_FDIV, MVT::v4f32, Legal);
-      setOperationAction(ISD::STRICT_FMA, MVT::v4f32, Legal);
-      setOperationAction(ISD::STRICT_FSQRT, MVT::v4f32, Legal);
-      setOperationAction(ISD::STRICT_FMAXNUM, MVT::v4f32, Legal);
-      setOperationAction(ISD::STRICT_FMINNUM, MVT::v4f32, Legal);
-      setOperationAction(ISD::STRICT_FRINT, MVT::v4f32, Legal);
-      setOperationAction(ISD::STRICT_FFLOOR, MVT::v4f32, Legal);
-      setOperationAction(ISD::STRICT_FCEIL,  MVT::v4f32, Legal);
-      setOperationAction(ISD::STRICT_FTRUNC, MVT::v4f32, Legal);
-      setOperationAction(ISD::STRICT_FROUND, MVT::v4f32, Legal);
-
-      setOperationAction(ISD::STRICT_FADD, MVT::v2f64, Legal);
-      setOperationAction(ISD::STRICT_FSUB, MVT::v2f64, Legal);
-      setOperationAction(ISD::STRICT_FMUL, MVT::v2f64, Legal);
-      setOperationAction(ISD::STRICT_FDIV, MVT::v2f64, Legal);
-      setOperationAction(ISD::STRICT_FMA, MVT::v2f64, Legal);
-      setOperationAction(ISD::STRICT_FSQRT, MVT::v2f64, Legal);
-      setOperationAction(ISD::STRICT_FMAXNUM, MVT::v2f64, Legal);
-      setOperationAction(ISD::STRICT_FMINNUM, MVT::v2f64, Legal);
-      setOperationAction(ISD::STRICT_FRINT, MVT::v2f64, Legal);
-      setOperationAction(ISD::STRICT_FFLOOR, MVT::v2f64, Legal);
-      setOperationAction(ISD::STRICT_FCEIL,  MVT::v2f64, Legal);
-      setOperationAction(ISD::STRICT_FTRUNC, MVT::v2f64, Legal);
-      setOperationAction(ISD::STRICT_FROUND, MVT::v2f64, Legal);
+      setOperationAction({ISD::STRICT_FADD, ISD::STRICT_FSUB, ISD::STRICT_FMUL,
+                          ISD::STRICT_FDIV, ISD::STRICT_FMA, ISD::STRICT_FSQRT,
+                          ISD::STRICT_FMAXNUM, ISD::STRICT_FMINNUM,
+                          ISD::STRICT_FRINT, ISD::STRICT_FFLOOR,
+                          ISD::STRICT_FCEIL, ISD::STRICT_FTRUNC,
+                          ISD::STRICT_FROUND},
+                         {MVT::v4f32, MVT::v2f64}, Legal);
 
       addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
       addRegisterClass(MVT::f128, &PPC::VRRCRegClass);

       setTruncStoreAction(MVT::f128, MVT::f32, Expand);
 
       // No implementation for these ops for PowerPC.
-      setOperationAction(ISD::FSIN, MVT::f128, Expand);
-      setOperationAction(ISD::FCOS, MVT::f128, Expand);
-      setOperationAction(ISD::FPOW, MVT::f128, Expand);
-      setOperationAction(ISD::FPOWI, MVT::f128, Expand);
-      setOperationAction(ISD::FREM, MVT::f128, Expand);
+      setOperationAction(
+          {ISD::FSIN, ISD::FCOS, ISD::FPOW, ISD::FPOWI, ISD::FREM}, MVT::f128,
+          Expand);
     }
 
     if (Subtarget.hasP8Altivec()) {

     }
 
     if (Subtarget.hasP9Vector()) {
-      setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
-      setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
+      setOperationAction(ISD::INSERT_VECTOR_ELT, {MVT::v4i32, MVT::v4f32},
+                         Custom);
 
       // 128 bit shifts can be accomplished via 3 instructions for SHL and
       // SRL, but not for SRA because of the instructions available:
       // VS{RL} and VS{RL}O.
-      setOperationAction(ISD::SHL, MVT::v1i128, Legal);
-      setOperationAction(ISD::SRL, MVT::v1i128, Legal);
+      setOperationAction({ISD::SHL, ISD::SRL}, MVT::v1i128, Legal);
       setOperationAction(ISD::SRA, MVT::v1i128, Expand);
 
-      setOperationAction(ISD::FADD, MVT::f128, Legal);
-      setOperationAction(ISD::FSUB, MVT::f128, Legal);
-      setOperationAction(ISD::FDIV, MVT::f128, Legal);
-      setOperationAction(ISD::FMUL, MVT::f128, Legal);
-      setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal);
-
-      setOperationAction(ISD::FMA, MVT::f128, Legal);
-      setCondCodeAction(ISD::SETULT, MVT::f128, Expand);
-      setCondCodeAction(ISD::SETUGT, MVT::f128, Expand);
-      setCondCodeAction(ISD::SETUEQ, MVT::f128, Expand);
-      setCondCodeAction(ISD::SETOGE, MVT::f128, Expand);
-      setCondCodeAction(ISD::SETOLE, MVT::f128, Expand);
-      setCondCodeAction(ISD::SETONE, MVT::f128, Expand);
-
-      setOperationAction(ISD::FTRUNC, MVT::f128, Legal);
-      setOperationAction(ISD::FRINT, MVT::f128, Legal);
-      setOperationAction(ISD::FFLOOR, MVT::f128, Legal);
-      setOperationAction(ISD::FCEIL, MVT::f128, Legal);
-      setOperationAction(ISD::FNEARBYINT, MVT::f128, Legal);
-      setOperationAction(ISD::FROUND, MVT::f128, Legal);
-
-      setOperationAction(ISD::FP_ROUND, MVT::f64, Legal);
-      setOperationAction(ISD::FP_ROUND, MVT::f32, Legal);
+      setOperationAction({ISD::FADD, ISD::FSUB, ISD::FDIV, ISD::FMUL,
+                          ISD::FP_EXTEND, ISD::FMA},
+                         MVT::f128, Legal);
+
+      setCondCodeAction({ISD::SETULT, ISD::SETUGT, ISD::SETUEQ, ISD::SETOGE,
+                         ISD::SETOLE, ISD::SETONE},
+                        MVT::f128, Expand);
+
+      setOperationAction({ISD::FTRUNC, ISD::FRINT, ISD::FFLOOR, ISD::FCEIL,
+                          ISD::FNEARBYINT, ISD::FROUND},
+                         MVT::f128, Legal);
+
+      setOperationAction(ISD::FP_ROUND, {MVT::f64, MVT::f32}, Legal);
       setOperationAction(ISD::BITCAST, MVT::i128, Custom);
 
       // Handle constrained floating-point operations of fp128
-      setOperationAction(ISD::STRICT_FADD, MVT::f128, Legal);
-      setOperationAction(ISD::STRICT_FSUB, MVT::f128, Legal);
-      setOperationAction(ISD::STRICT_FMUL, MVT::f128, Legal);
-      setOperationAction(ISD::STRICT_FDIV, MVT::f128, Legal);
-      setOperationAction(ISD::STRICT_FMA, MVT::f128, Legal);
-      setOperationAction(ISD::STRICT_FSQRT, MVT::f128, Legal);
-      setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f128, Legal);
-      setOperationAction(ISD::STRICT_FP_ROUND, MVT::f64, Legal);
-      setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Legal);
-      setOperationAction(ISD::STRICT_FRINT, MVT::f128, Legal);
-      setOperationAction(ISD::STRICT_FNEARBYINT, MVT::f128, Legal);
-      setOperationAction(ISD::STRICT_FFLOOR, MVT::f128, Legal);
-      setOperationAction(ISD::STRICT_FCEIL, MVT::f128, Legal);
-      setOperationAction(ISD::STRICT_FTRUNC, MVT::f128, Legal);
-      setOperationAction(ISD::STRICT_FROUND, MVT::f128, Legal);
+      setOperationAction({ISD::STRICT_FADD, ISD::STRICT_FSUB, ISD::STRICT_FMUL,
+                          ISD::STRICT_FDIV, ISD::STRICT_FMA, ISD::STRICT_FSQRT,
+                          ISD::STRICT_FP_EXTEND, ISD::STRICT_FRINT,
+                          ISD::STRICT_FNEARBYINT, ISD::STRICT_FFLOOR,
+                          ISD::STRICT_FCEIL, ISD::STRICT_FTRUNC,
+                          ISD::STRICT_FROUND},
+                         MVT::f128, Legal);
+
+      setOperationAction(ISD::STRICT_FP_ROUND, {MVT::f64, MVT::f32}, Legal);
       setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
-      setOperationAction(ISD::BSWAP, MVT::v8i16, Legal);
-      setOperationAction(ISD::BSWAP, MVT::v4i32, Legal);
-      setOperationAction(ISD::BSWAP, MVT::v2i64, Legal);
-      setOperationAction(ISD::BSWAP, MVT::v1i128, Legal);
+      setOperationAction(
+          ISD::BSWAP, {MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v1i128}, Legal);
     } else if (Subtarget.hasVSX()) {
-      setOperationAction(ISD::LOAD, MVT::f128, Promote);
-      setOperationAction(ISD::STORE, MVT::f128, Promote);
+      setOperationAction({ISD::LOAD, ISD::STORE}, MVT::f128, Promote);
 
       AddPromotedToType(ISD::LOAD, MVT::f128, MVT::v4i32);
       AddPromotedToType(ISD::STORE, MVT::f128, MVT::v4i32);
 
       // Set FADD/FSUB as libcall to avoid the legalizer to expand the
       // fp_to_uint and int_to_fp.
-      setOperationAction(ISD::FADD, MVT::f128, LibCall);
-      setOperationAction(ISD::FSUB, MVT::f128, LibCall);
+      setOperationAction({ISD::FADD, ISD::FSUB}, MVT::f128, LibCall);
 
-      setOperationAction(ISD::FMUL, MVT::f128, Expand);
-      setOperationAction(ISD::FDIV, MVT::f128, Expand);
-      setOperationAction(ISD::FNEG, MVT::f128, Expand);
-      setOperationAction(ISD::FABS, MVT::f128, Expand);
-      setOperationAction(ISD::FSQRT, MVT::f128, Expand);
-      setOperationAction(ISD::FMA, MVT::f128, Expand);
-      setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
+      setOperationAction({ISD::FMUL, ISD::FDIV, ISD::FNEG, ISD::FABS,
+                          ISD::FSQRT, ISD::FMA, ISD::FCOPYSIGN},
+                         MVT::f128, Expand);
 
       // Expand the fp_extend if the target type is fp128.
-      setOperationAction(ISD::FP_EXTEND, MVT::f128, Expand);
-      setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f128, Expand);
+      setOperationAction({ISD::FP_EXTEND, ISD::STRICT_FP_EXTEND}, MVT::f128,
+                         Expand);
 
       // Expand the fp_round if the source type is fp128.
-      for (MVT VT : {MVT::f32, MVT::f64}) {
-        setOperationAction(ISD::FP_ROUND, VT, Custom);
-        setOperationAction(ISD::STRICT_FP_ROUND, VT, Custom);
-      }
+      setOperationAction({ISD::FP_ROUND, ISD::STRICT_FP_ROUND},
+                         {MVT::f32, MVT::f64}, Custom);
 
-      setOperationAction(ISD::SETCC, MVT::f128, Custom);
-      setOperationAction(ISD::STRICT_FSETCC, MVT::f128, Custom);
-      setOperationAction(ISD::STRICT_FSETCCS, MVT::f128, Custom);
+      setOperationAction({ISD::SETCC, ISD::STRICT_FSETCC, ISD::STRICT_FSETCCS},
+                         MVT::f128, Custom);
       setOperationAction(ISD::BR_CC, MVT::f128, Expand);
 
       // Lower following f128 select_cc pattern:
-      // select_cc x, y, tv, fv, cc -> select_cc (setcc x, y, cc), 0, tv, fv, NE
+      // select_cc x, y, tv, fv, cc -> select_cc (setcc x, y, cc), 0, tv, fv,
+      // NE
       setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
 
       // We need to handle f128 SELECT_CC with integer result type.

     }
 
     if (Subtarget.hasP9Altivec()) {
-      if (Subtarget.isISA3_1()) {
-        setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
-        setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Legal);
-        setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Legal);
-        setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Legal);
-      } else {
-        setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
-        setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
-      }
-      setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8,  Legal);
-      setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Legal);
-      setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Legal);
-      setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8,  Legal);
-      setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Legal);
-      setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
-      setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
+      if (Subtarget.isISA3_1())
+        setOperationAction(ISD::INSERT_VECTOR_ELT,
+                           {MVT::v2i64, MVT::v8i16, MVT::v16i8, MVT::v4i32},
+                           Legal);
+      else
+        setOperationAction(ISD::INSERT_VECTOR_ELT, {MVT::v8i16, MVT::v16i8},
+                           Custom);
+      setOperationAction(ISD::SIGN_EXTEND_INREG,
+                         {MVT::v4i8, MVT::v4i16, MVT::v4i32, MVT::v2i8,
+                          MVT::v2i16, MVT::v2i32, MVT::v2i64},
+                         Legal);
     }
 
     if (Subtarget.hasP10Vector()) {

 
   if (Subtarget.pairedVectorMemops()) {
     addRegisterClass(MVT::v256i1, &PPC::VSRpRCRegClass);
-    setOperationAction(ISD::LOAD, MVT::v256i1, Custom);
-    setOperationAction(ISD::STORE, MVT::v256i1, Custom);
+    setOperationAction({ISD::LOAD, ISD::STORE}, MVT::v256i1, Custom);
   }
   if (Subtarget.hasMMA()) {
     addRegisterClass(MVT::v512i1, &PPC::UACCRCRegClass);
-    setOperationAction(ISD::LOAD, MVT::v512i1, Custom);
-    setOperationAction(ISD::STORE, MVT::v512i1, Custom);
-    setOperationAction(ISD::BUILD_VECTOR, MVT::v512i1, Custom);
+    setOperationAction({ISD::LOAD, ISD::STORE, ISD::BUILD_VECTOR}, MVT::v512i1,
+                       Custom);
   }
 
   if (Subtarget.has64BitSupport())

 
   setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
 
-  if (!isPPC64) {
-    setOperationAction(ISD::ATOMIC_LOAD,  MVT::i64, Expand);
-    setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
-  }
+  if (!isPPC64)
+    setOperationAction({ISD::ATOMIC_LOAD, ISD::ATOMIC_STORE}, MVT::i64, Expand);
 
-  if (shouldInlineQuadwordAtomics()) {
-    setOperationAction(ISD::ATOMIC_LOAD, MVT::i128, Custom);
-    setOperationAction(ISD::ATOMIC_STORE, MVT::i128, Custom);
-    setOperationAction(ISD::INTRINSIC_VOID, MVT::i128, Custom);
-  }
+  if (shouldInlineQuadwordAtomics())
+    setOperationAction(
+        {ISD::ATOMIC_LOAD, ISD::ATOMIC_STORE, ISD::INTRINSIC_VOID}, MVT::i128,
+        Custom);
 
   setBooleanContents(ZeroOrOneBooleanContent);
 

   }
 
   setLibcallName(RTLIB::MULO_I128, nullptr);
-  if (!isPPC64) {
+  if (!isPPC64)
     // These libcalls are not available in 32-bit.
-    setLibcallName(RTLIB::SHL_I128, nullptr);
-    setLibcallName(RTLIB::SRL_I128, nullptr);
-    setLibcallName(RTLIB::SRA_I128, nullptr);
-    setLibcallName(RTLIB::MUL_I128, nullptr);
-    setLibcallName(RTLIB::MULO_I64, nullptr);
-  }
+    setLibcallName({RTLIB::SHL_I128, RTLIB::SRL_I128, RTLIB::SRA_I128,
+                    RTLIB::MUL_I128, RTLIB::MULO_I64},
+                   nullptr);
 
   if (!isPPC64)
     setMaxAtomicSizeInBitsSupported(32);