[RISCV] Remove sext_inreg+riscv_grev/riscv_gorc isel patterns.

[Jimerlife]

Summary

Use binop_allwusers and doPeepholeSExtW to Remove sext_inreg+riscv_grev/riscv_gorc isel patterns.
There is special when Imm is 7, becase of existing two patterns:
Pat<(riscv_gorc GPR:$rs1, 7), (ORC_B GPR:$rs1)>,
Pat<(riscv_grev GPR:$rs1, 7), (BREV8 GPR:$rs1).
So I still keep sext_inreg+riscv_grev/riscv_gorc when imm is 7.

[craig.topper]

LGTM.

Though I wonder at what point we should delete all code for non-ratified bitmanip ISAs. The Bitmanip task group doesn't appear to be active anymore so these instructions may never become official and the opcodes may get claimed for something else.

[frasercrmck]

In D123565#3444561, @craig.topper wrote:

Though I wonder at what point we should delete all code for non-ratified bitmanip ISAs. The Bitmanip task group doesn't appear to be active anymore so these instructions may never become official and the opcodes may get claimed for something else.

Yeah I've been wondering about that too. Feels like nobody's sure. Only yesterday I noticed that spike supports these non-ratified ones as a custom Xbitmanip (XZbp etc) extension(s). Not that that's a reason to keep them, it's just an interesting data point.

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

 // before doing this, but that would be more complicated.
 // TODO: Does this need to look through AND/OR/XOR to their users to find more
 // opportunities.
 bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits) const {
   assert((Node->getOpcode() == ISD::ADD || Node->getOpcode() == ISD::SUB ||
           Node->getOpcode() == ISD::MUL || Node->getOpcode() == ISD::SHL ||
           Node->getOpcode() == ISD::SRL ||
           Node->getOpcode() == ISD::SIGN_EXTEND_INREG ||
+          Node->getOpcode() == RISCVISD::GREV ||
+          Node->getOpcode() == RISCVISD::GORC ||
           isa<ConstantSDNode>(Node)) &&
          "Unexpected opcode");
 
   for (auto UI = Node->use_begin(), UE = Node->use_end(); UI != UE; ++UI) {
     SDNode *User = *UI;
     // Users of this node should have already been instruction selected
     if (!User->isMachineOpcode())
       return false;
case RISCV::SLLI: {
     ReplaceUses(N, Result);
     return true;
   }
   case RISCV::ADDW:
   case RISCV::ADDIW:
   case RISCV::SUBW:
   case RISCV::MULW:
   case RISCV::SLLIW:
+  case RISCV::GREVIW:
+  case RISCV::GORCIW:
     // Result is already sign extended just remove the sext.w.
     // NOTE: We only handle the nodes that are selected with hasAllWUsers.
     ReplaceUses(N, N0.getNode());
     return true;
   }
 
   return false;
 }

llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

 } // Predicates = [HasStdExtZbp]
 
 let Predicates = [HasStdExtZbp, IsRV64] in {
 def : PatGprGpr<riscv_grevw, GREVW>;
 def : PatGprGpr<riscv_gorcw, GORCW>;
 
 // Select GREVIW/GORCIW when the immediate doesn't have bit 5 set and the result
 // is sign extended.
-// FIXME: Use binop_allwusers and doPeepholeSExtW instead?
-def : Pat<(i64 (sext_inreg (binop_oneuse<riscv_grev> GPR:$rs1, uimm5:$imm), i32)),
-          (GREVIW GPR:$rs1, uimm5:$imm)>;
-def : Pat<(i64 (sext_inreg (binop_oneuse<riscv_gorc> GPR:$rs1, uimm5:$imm), i32)),
-          (GORCIW GPR:$rs1, uimm5:$imm)>;
+// FIXME: Two special patterns keeped when Imm is 7.
+def : Pat<(i64 (sext_inreg (binop_oneuse<riscv_grev> GPR:$rs1, 7), i32)),
+          (GREVIW GPR:$rs1, 7)>;
+def : Pat<(i64 (sext_inreg (binop_oneuse<riscv_gorc> GPR:$rs1, 7), i32)),
+          (GORCIW GPR:$rs1, 7)>;
+def : PatGprImm<binop_allwusers<riscv_grev>, GREVIW, uimm5>;
+def : PatGprImm<binop_allwusers<riscv_gorc>, GORCIW, uimm5>;
 
 def : PatGprGpr<riscv_shflw, SHFLW>;
 def : PatGprGpr<riscv_unshflw, UNSHFLW>;
 } // Predicates = [HasStdExtZbp, IsRV64]
 
 let Predicates = [HasStdExtZbp, IsRV64] in
 def : PatGprGpr<int_riscv_xperm_w, XPERM_W>;
 

llvm/test/CodeGen/RISCV/rv64zbp.ll

 ; RV64I-NEXT:    slli a0, a0, 24
 ; RV64I-NEXT:    or a0, a0, a3
 ; RV64I-NEXT:    or a0, a0, a2
 ; RV64I-NEXT:    sw a0, 0(a1)
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBP-LABEL: bswap_i32_nosext:
 ; RV64ZBP:       # %bb.0:
-; RV64ZBP-NEXT:    rev8.w a0, a0
+; RV64ZBP-NEXT:    greviw a0, a0, 24
 ; RV64ZBP-NEXT:    sw a0, 0(a1)
 ; RV64ZBP-NEXT:    ret
   %1 = tail call i32 @llvm.bswap.i32(i32 %a)
   store i32 %1, i32* %x
   ret void
 }
 
 declare i64 @llvm.bswap.i64(i64)

 ; RV64I-NEXT:    and a0, a0, a3
 ; RV64I-NEXT:    slli a0, a0, 1
 ; RV64I-NEXT:    or a0, a2, a0
 ; RV64I-NEXT:    sw a0, 0(a1)
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBP-LABEL: bitreverse_i32_nosext:
 ; RV64ZBP:       # %bb.0:
-; RV64ZBP-NEXT:    rev.w a0, a0
+; RV64ZBP-NEXT:    greviw a0, a0, 31
 ; RV64ZBP-NEXT:    sw a0, 0(a1)
 ; RV64ZBP-NEXT:    ret
   %1 = tail call i32 @llvm.bitreverse.i32(i32 %a)
   store i32 %1, i32* %x
   ret void
 }
 
 declare i64 @llvm.bitreverse.i64(i64)