[UpdateLLCTestChecks] Pick the correct output block when generating isel debug output checks in update_llc_test_checks.py

[ningxinr]

Summary

This change is a follow-up change of D119368. This change picks up the right block
from the generated isel debug output, and make the generated tests runnable.

With this change, the checks generated will pass. A lit tests of Lanai is added to
demonstrate what a passing test would look like.

This patch concludes the support of instruction selection debug output check generation.

[Flakebi]

Just to check that I understand this correctly.
Is the intention behind the function prefix to make it configurable in the end, so that one can also check for Legalized selection DAG and others?

Or is it only to pick the right block, without making it configurable?
Then I think it would be easier to use check_label_format = '{} %s-LABEL: Selected selection DAG:{{.*}}%s%s:', which does not need any changes in common.py

llvm/utils/UpdateTestChecks/common.py

844–846 ↗

(On Diff #419441)

This might be easier to read?

func_prefix = func_dict[checkprefix][func_name].func_prefix
if func_prefix:
  output_lines.append(check_label_format % (checkprefix, func_prefix + '{{.*}}', func_name, args_and_sig))

[ningxinr]

In D122824#3421553, @Flakebi wrote:

Just to check that I understand this correctly.
Is the intention behind the function prefix to make it configurable in the end, so that one can also check for Legalized selection DAG and others?

Or is it only to pick the right block, without making it configurable?
Then I think it would be easier to use check_label_format = '{} %s-LABEL: Selected selection DAG:{{.*}}%s%s:', which does not need any changes in common.py

You were right, this is much easier for my purpose. For this use case the function prefix is an invariant of function name and FileCheck prefixes, so we can just add it to the check_label_format. I suppose we could always change this later when the need of making it configurable rises.

Thank you, Sebastian! :)

[ningxinr]

Update commit message to reflect the feedback

[Flakebi]

llvm/utils/UpdateTestChecks/isel.py

16

I guess this TODO is fixed with this patch?

18

For consistency with the checked string below, maybe use spaces here for Selected selection DAG: %bb.0?

[lebedev.ri]

This review may be stuck/dead, consider abandoning if no longer relevant.
Removing myself as reviewer in attempt to clean dashboard.

llvm/test/CodeGen/Lanai/isel_debug_single.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=lanai -stop-after=finalize-isel -debug-only=isel -o /dev/null %s 2>&1 | FileCheck %s
+
+; Test Selection DAG debug output generation
+
+target datalayout = "E-m:e-p:32:32-i64:64-a:0:32-n32-S64"
+target triple = "lanai"
+
+define i64 @i64_test(i64 %i) nounwind readnone {
+; CHECK-LABEL: Selected selection DAG:{{.*}}i64_test:
+; CHECK:       SelectionDAG has 22 nodes:
+; CHECK-NEXT:    t0: ch = EntryToken
+; CHECK-NEXT:    t5: i32,ch = LDW_RI<Mem:(load (s32) from %fixed-stack.0)> TargetFrameIndex:i32<-2>, TargetConstant:i32<0>, TargetConstant:i32<0>, t0
+; CHECK-NEXT:    t7: i32 = ADD_I_LO TargetFrameIndex:i32<0>, TargetConstant:i32<0>
+; CHECK-NEXT:    t29: i32 = OR_I_LO t7, TargetConstant:i32<4>
+; CHECK-NEXT:    t22: i32,ch = LDW_RI<Mem:(dereferenceable load (s32) from %ir.loc + 4, basealign 8)> t29, TargetConstant:i32<0>, TargetConstant:i32<0>, t0
+; CHECK-NEXT:    t24: i32 = ADD_R t5, t22, TargetConstant:i32<0>
+; CHECK-NEXT:    t3: i32,ch = LDW_RI<Mem:(load (s32) from %fixed-stack.1, align 8)> TargetFrameIndex:i32<-1>, TargetConstant:i32<0>, TargetConstant:i32<0>, t0
+; CHECK-NEXT:    t19: i32,ch = LDW_RI<Mem:(dereferenceable load (s32) from %ir.loc, align 8)> TargetFrameIndex:i32<0>, TargetConstant:i32<0>, TargetConstant:i32<0>, t0
+; CHECK-NEXT:    t25: i32 = ADD_R t3, t19, TargetConstant:i32<0>
+; CHECK-NEXT:    t30: i32,glue = SFSUB_F_RR t24, t5
+; CHECK-NEXT:    t31: i32 = SCC TargetConstant:i32<4>, t30:1
+; CHECK-NEXT:    t28: i32 = ADD_R t25, t31, TargetConstant:i32<0>
+; CHECK-NEXT:    t15: ch,glue = CopyToReg t0, Register:i32 $rv, t28
+; CHECK-NEXT:    t17: ch,glue = CopyToReg t15, Register:i32 $r9, t24, t15:1
+; CHECK-NEXT:    t18: ch = RET Register:i32 $rv, Register:i32 $r9, t17, t17:1
+; CHECK-EMPTY:
+  %loc = alloca i64
+  %j = load i64, i64 * %loc
+  %r = add i64 %i, %j
+  ret i64 %r
+}
+
+define i64 @i32_test(i32 %i) nounwind readnone {
+; CHECK-LABEL: Selected selection DAG:{{.*}}i32_test:
+; CHECK:       SelectionDAG has 14 nodes:
+; CHECK-NEXT:    t0: ch = EntryToken
+; CHECK-NEXT:    t21: i32,ch = CopyFromReg t0, Register:i32 $r0
+; CHECK-NEXT:    t13: ch,glue = CopyToReg t0, Register:i32 $rv, t21
+; CHECK-NEXT:    t3: i32,ch = LDW_RI<Mem:(load (s32) from %fixed-stack.0, align 8)> TargetFrameIndex:i32<-1>, TargetConstant:i32<0>, TargetConstant:i32<0>, t0
+; CHECK-NEXT:    t6: i32,ch = LDW_RI<Mem:(dereferenceable load (s32) from %ir.loc)> TargetFrameIndex:i32<0>, TargetConstant:i32<0>, TargetConstant:i32<0>, t0
+; CHECK-NEXT:    t7: i32 = ADD_R t3, t6, TargetConstant:i32<0>
+; CHECK-NEXT:    t15: ch,glue = CopyToReg t13, Register:i32 $r9, t7, t13:1
+; CHECK-NEXT:    t16: ch = RET Register:i32 $rv, Register:i32 $r9, t15, t15:1
+; CHECK-EMPTY:
+  %loc = alloca i32
+  %j = load i32, i32 * %loc
+  %r = add i32 %i, %j
+  %ext = zext i32 %r to i64
+  ret i64 %ext
+}
+
+define i64 @i16_test(i16 %i) nounwind readnone {
+; CHECK-LABEL: Selected selection DAG:{{.*}}i16_test:
+; CHECK:       SelectionDAG has 19 nodes:
+; CHECK-NEXT:    t0: ch = EntryToken
+; CHECK-NEXT:    t33: i32,ch = CopyFromReg t0, Register:i32 $r0
+; CHECK-NEXT:    t14: ch,glue = CopyToReg t0, Register:i32 $rv, t33
+; CHECK-NEXT:    t1: i32 = ADD_I_LO TargetFrameIndex:i32<-1>, TargetConstant:i32<0>
+; CHECK-NEXT:    t21: i32 = OR_I_LO t1, TargetConstant:i32<2>
+; CHECK-NEXT:    t23: i32,ch = LDHz_RI<Mem:(load (s16) from %fixed-stack.0 + 2)> t21, TargetConstant:i32<0>, TargetConstant:i32<0>, t0
+; CHECK-NEXT:    t22: i32,ch = LDHz_RI<Mem:(dereferenceable load (s16) from %ir.loc)> TargetFrameIndex:i32<0>, TargetConstant:i32<0>, TargetConstant:i32<0>, t0
+; CHECK-NEXT:    t24: i32 = ADD_R t23, t22, TargetConstant:i32<0>
+; CHECK-NEXT:    t27: i32 = AND_I_HI t24, TargetConstant:i32<0>
+; CHECK-NEXT:    t16: ch,glue = CopyToReg t14, Register:i32 $r9, t27, t14:1
+; CHECK-NEXT:    t28: i32 = TargetConstant<65535>
+; CHECK-NEXT:    t17: ch = RET Register:i32 $rv, Register:i32 $r9, t16, t16:1
+; CHECK-EMPTY:
+  %loc = alloca i16
+  %j = load i16, i16 * %loc
+  %r = add i16 %i, %j
+  %ext = zext i16 %r to i64
+  ret i64 %ext
+}
+
+define i64 @i8_test(i8 %i) nounwind readnone {
+; CHECK-LABEL: Selected selection DAG:{{.*}}i8_test:
+; CHECK:       SelectionDAG has 20 nodes:
+; CHECK-NEXT:    t0: ch = EntryToken
+; CHECK-NEXT:    t33: i32,ch = CopyFromReg t0, Register:i32 $r0
+; CHECK-NEXT:    t14: ch,glue = CopyToReg t0, Register:i32 $rv, t33
+; CHECK-NEXT:    t1: i32 = ADD_I_LO TargetFrameIndex:i32<-1>, TargetConstant:i32<0>
+; CHECK-NEXT:    t21: i32 = OR_I_LO t1, TargetConstant:i32<3>
+; CHECK-NEXT:    t23: i32,ch = LDBz_RI<Mem:(load (s8) from %fixed-stack.0 + 3)> t21, TargetConstant:i32<0>, TargetConstant:i32<0>, t0
+; CHECK-NEXT:    t22: i32,ch = LDBz_RI<Mem:(dereferenceable load (s8) from %ir.loc)> TargetFrameIndex:i32<0>, TargetConstant:i32<0>, TargetConstant:i32<0>, t0
+; CHECK-NEXT:    t24: i32 = ADD_R t23, t22, TargetConstant:i32<0>
+; CHECK-NEXT:    t26: i32 = SLI TargetConstant:i32<255>
+; CHECK-NEXT:    t27: i32 = AND_R t24, t26, TargetConstant:i32<0>
+; CHECK-NEXT:    t16: ch,glue = CopyToReg t14, Register:i32 $r9, t27, t14:1
+; CHECK-NEXT:    t17: ch = RET Register:i32 $rv, Register:i32 $r9, t16, t16:1
+; CHECK-EMPTY:
+  %loc = alloca i8
+  %j = load i8, i8 * %loc
+  %r = add i8 %i, %j
+  %ext = zext i8 %r to i64
+  ret i64 %ext
+}

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -stop-after=finalize-isel -debug-only=isel -o /dev/null %s 2>&1 | FileCheck %s
 
 define i64 @i64_test(i64 %i) nounwind readnone {
-; CHECK-LABEL: i64_test:
+; CHECK-LABEL: Selected selection DAG:{{.*}}i64_test:
 ; CHECK:       SelectionDAG has 9 nodes:
 ; CHECK-NEXT:    t0: ch = EntryToken
 ; CHECK-NEXT:    t11: ch,glue = CopyToReg t0, Register:i32 $vgpr0, IMPLICIT_DEF:i32
 ; CHECK-NEXT:    t17: i32 = V_MOV_B32_e32 TargetConstant:i32<0>
 ; CHECK-NEXT:    t13: ch,glue = CopyToReg t11, Register:i32 $vgpr1, t17, t11:1
 ; CHECK-NEXT:    t14: ch = SI_RETURN Register:i32 $vgpr0, Register:i32 $vgpr1, t13, t13:1
 ; CHECK-EMPTY:
   %loc = alloca i64
   %j = load i64, i64 * %loc
   %r = add i64 %i, %j
   ret i64 %r
 }
 
 define i64 @i32_test(i32 %i) nounwind readnone {
-; CHECK-LABEL: i32_test:
+; CHECK-LABEL: Selected selection DAG:{{.*}}i32_test:
 ; CHECK:       SelectionDAG has 8 nodes:
 ; CHECK-NEXT:    t5: i32 = V_MOV_B32_e32 TargetConstant:i32<0>
 ; CHECK-NEXT:    t0: ch = EntryToken
 ; CHECK-NEXT:    t7: ch,glue = CopyToReg t0, Register:i32 $vgpr0, t5
 ; CHECK-NEXT:    t9: ch,glue = CopyToReg t7, Register:i32 $vgpr1, t5, t7:1
 ; CHECK-NEXT:    t10: ch = SI_RETURN Register:i32 $vgpr0, Register:i32 $vgpr1, t9, t9:1
 ; CHECK-EMPTY:
   %loc = alloca i32
   %j = load i32, i32 * %loc
   %r = add i32 %i, %j
   %ext = zext i32 %r to i64
   ret i64 %ext
 }
 
 define i64 @i16_test(i16 %i) nounwind readnone {
-; CHECK-LABEL: i16_test:
+; CHECK-LABEL: Selected selection DAG:{{.*}}i16_test:
 ; CHECK:       SelectionDAG has 8 nodes:
 ; CHECK-NEXT:    t5: i32 = V_MOV_B32_e32 TargetConstant:i32<0>
 ; CHECK-NEXT:    t0: ch = EntryToken
 ; CHECK-NEXT:    t7: ch,glue = CopyToReg t0, Register:i32 $vgpr0, t5
 ; CHECK-NEXT:    t9: ch,glue = CopyToReg t7, Register:i32 $vgpr1, t5, t7:1
 ; CHECK-NEXT:    t10: ch = SI_RETURN Register:i32 $vgpr0, Register:i32 $vgpr1, t9, t9:1
 ; CHECK-EMPTY:
   %loc = alloca i16
   %j = load i16, i16 * %loc
   %r = add i16 %i, %j
   %ext = zext i16 %r to i64
   ret i64 %ext
 }
 
 define i64 @i8_test(i8 %i) nounwind readnone {
-; CHECK-LABEL: i8_test:
+; CHECK-LABEL: Selected selection DAG:{{.*}}i8_test:
 ; CHECK:       SelectionDAG has 8 nodes:
 ; CHECK-NEXT:    t5: i32 = V_MOV_B32_e32 TargetConstant:i32<0>
 ; CHECK-NEXT:    t0: ch = EntryToken
 ; CHECK-NEXT:    t7: ch,glue = CopyToReg t0, Register:i32 $vgpr0, t5
 ; CHECK-NEXT:    t9: ch,glue = CopyToReg t7, Register:i32 $vgpr1, t5, t7:1
 ; CHECK-NEXT:    t10: ch = SI_RETURN Register:i32 $vgpr0, Register:i32 $vgpr1, t9, t9:1
 ; CHECK-EMPTY:
   %loc = alloca i8
   %j = load i8, i8 * %loc
   %r = add i8 %i, %j
   %ext = zext i8 %r to i64
   ret i64 %ext
 }

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/lanai_isel.ll.expected

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=lanai -stop-after=finalize-isel -debug-only=isel -o /dev/null %s 2>&1 | FileCheck %s
 
 define i64 @i64_test(i64 %i) nounwind readnone {
-; CHECK-LABEL: i64_test:
+; CHECK-LABEL: Selected selection DAG:{{.*}}i64_test:
 ; CHECK:       SelectionDAG has 22 nodes:
 ; CHECK-NEXT:    t0: ch = EntryToken
 ; CHECK-NEXT:    t5: i32,ch = LDW_RI<Mem:(load (s32) from %fixed-stack.0)> TargetFrameIndex:i32<-2>, TargetConstant:i32<0>, TargetConstant:i32<0>, t0
 ; CHECK-NEXT:    t7: i32 = ADD_I_LO TargetFrameIndex:i32<0>, TargetConstant:i32<0>
 ; CHECK-NEXT:    t29: i32 = OR_I_LO t7, TargetConstant:i32<4>
 ; CHECK-NEXT:    t22: i32,ch = LDW_RI<Mem:(dereferenceable load (s32) from %ir.loc + 4, basealign 8)> t29, TargetConstant:i32<0>, TargetConstant:i32<0>, t0
 ; CHECK-NEXT:    t24: i32 = ADD_R t5, t22, TargetConstant:i32<0>
 ; CHECK-NEXT:    t3: i32,ch = LDW_RI<Mem:(load (s32) from %fixed-stack.1, align 8)> TargetFrameIndex:i32<-1>, TargetConstant:i32<0>, TargetConstant:i32<0>, t0
 ; CHECK-NEXT:    t19: i32,ch = LDW_RI<Mem:(dereferenceable load (s32) from %ir.loc, align 8)> TargetFrameIndex:i32<0>, TargetConstant:i32<0>, TargetConstant:i32<0>, t0
 ; CHECK-NEXT:    t25: i32 = ADD_R t3, t19, TargetConstant:i32<0>
 ; CHECK-NEXT:    t30: i32,glue = SFSUB_F_RR t24, t5
 ; CHECK-NEXT:    t31: i32 = SCC TargetConstant:i32<4>, t30:1
 ; CHECK-NEXT:    t28: i32 = ADD_R t25, t31, TargetConstant:i32<0>
 ; CHECK-NEXT:    t15: ch,glue = CopyToReg t0, Register:i32 $rv, t28
 ; CHECK-NEXT:    t17: ch,glue = CopyToReg t15, Register:i32 $r9, t24, t15:1
 ; CHECK-NEXT:    t18: ch = RET Register:i32 $rv, Register:i32 $r9, t17, t17:1
 ; CHECK-EMPTY:
   %loc = alloca i64
   %j = load i64, i64 * %loc
   %r = add i64 %i, %j
   ret i64 %r
 }
 
 define i64 @i32_test(i32 %i) nounwind readnone {
-; CHECK-LABEL: i32_test:
+; CHECK-LABEL: Selected selection DAG:{{.*}}i32_test:
 ; CHECK:       SelectionDAG has 14 nodes:
 ; CHECK-NEXT:    t0: ch = EntryToken
 ; CHECK-NEXT:    t21: i32,ch = CopyFromReg t0, Register:i32 $r0
 ; CHECK-NEXT:    t13: ch,glue = CopyToReg t0, Register:i32 $rv, t21
 ; CHECK-NEXT:    t3: i32,ch = LDW_RI<Mem:(load (s32) from %fixed-stack.0, align 8)> TargetFrameIndex:i32<-1>, TargetConstant:i32<0>, TargetConstant:i32<0>, t0
 ; CHECK-NEXT:    t6: i32,ch = LDW_RI<Mem:(dereferenceable load (s32) from %ir.loc)> TargetFrameIndex:i32<0>, TargetConstant:i32<0>, TargetConstant:i32<0>, t0
 ; CHECK-NEXT:    t7: i32 = ADD_R t3, t6, TargetConstant:i32<0>
 ; CHECK-NEXT:    t15: ch,glue = CopyToReg t13, Register:i32 $r9, t7, t13:1
 ; CHECK-NEXT:    t16: ch = RET Register:i32 $rv, Register:i32 $r9, t15, t15:1
 ; CHECK-EMPTY:
   %loc = alloca i32
   %j = load i32, i32 * %loc
   %r = add i32 %i, %j
   %ext = zext i32 %r to i64
   ret i64 %ext
 }
 
 define i64 @i16_test(i16 %i) nounwind readnone {
-; CHECK-LABEL: i16_test:
+; CHECK-LABEL: Selected selection DAG:{{.*}}i16_test:
 ; CHECK:       SelectionDAG has 19 nodes:
 ; CHECK-NEXT:    t0: ch = EntryToken
 ; CHECK-NEXT:    t33: i32,ch = CopyFromReg t0, Register:i32 $r0
 ; CHECK-NEXT:    t14: ch,glue = CopyToReg t0, Register:i32 $rv, t33
 ; CHECK-NEXT:    t1: i32 = ADD_I_LO TargetFrameIndex:i32<-1>, TargetConstant:i32<0>
 ; CHECK-NEXT:    t21: i32 = OR_I_LO t1, TargetConstant:i32<2>
 ; CHECK-NEXT:    t23: i32,ch = LDHz_RI<Mem:(load (s16) from %fixed-stack.0 + 2)> t21, TargetConstant:i32<0>, TargetConstant:i32<0>, t0
 ; CHECK-NEXT:    t22: i32,ch = LDHz_RI<Mem:(dereferenceable load (s16) from %ir.loc)> TargetFrameIndex:i32<0>, TargetConstant:i32<0>, TargetConstant:i32<0>, t0
 ; CHECK-NEXT:    t24: i32 = ADD_R t23, t22, TargetConstant:i32<0>
 ; CHECK-NEXT:    t27: i32 = AND_I_HI t24, TargetConstant:i32<0>
 ; CHECK-NEXT:    t16: ch,glue = CopyToReg t14, Register:i32 $r9, t27, t14:1
 ; CHECK-NEXT:    t28: i32 = TargetConstant<65535>
 ; CHECK-NEXT:    t17: ch = RET Register:i32 $rv, Register:i32 $r9, t16, t16:1
 ; CHECK-EMPTY:
   %loc = alloca i16
   %j = load i16, i16 * %loc
   %r = add i16 %i, %j
   %ext = zext i16 %r to i64
   ret i64 %ext
 }
 
 define i64 @i8_test(i8 %i) nounwind readnone {
-; CHECK-LABEL: i8_test:
+; CHECK-LABEL: Selected selection DAG:{{.*}}i8_test:
 ; CHECK:       SelectionDAG has 20 nodes:
 ; CHECK-NEXT:    t0: ch = EntryToken
 ; CHECK-NEXT:    t33: i32,ch = CopyFromReg t0, Register:i32 $r0
 ; CHECK-NEXT:    t14: ch,glue = CopyToReg t0, Register:i32 $rv, t33
 ; CHECK-NEXT:    t1: i32 = ADD_I_LO TargetFrameIndex:i32<-1>, TargetConstant:i32<0>
 ; CHECK-NEXT:    t21: i32 = OR_I_LO t1, TargetConstant:i32<3>
 ; CHECK-NEXT:    t23: i32,ch = LDBz_RI<Mem:(load (s8) from %fixed-stack.0 + 3)> t21, TargetConstant:i32<0>, TargetConstant:i32<0>, t0
 ; CHECK-NEXT:    t22: i32,ch = LDBz_RI<Mem:(dereferenceable load (s8) from %ir.loc)> TargetFrameIndex:i32<0>, TargetConstant:i32<0>, TargetConstant:i32<0>, t0

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_isel.ll.expected

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=x86_64 -stop-after=finalize-isel -debug-only=isel -o /dev/null %s 2>&1 | FileCheck %s --check-prefix=PIC
 ; RUN: llc -mtriple=x86_64-windows -stop-after=finalize-isel -debug-only=isel -o /dev/null %s 2>&1 | FileCheck %s --check-prefix=WIN
 
 define i64 @i64_test(i64 %i) nounwind readnone {
-; PIC-LABEL: i64_test:
+; PIC-LABEL: Selected selection DAG:{{.*}}i64_test:
 ; PIC:       SelectionDAG has 12 nodes:
 ; PIC-NEXT:    t0: ch = EntryToken
 ; PIC-NEXT:    t2: i64,ch = CopyFromReg t0, Register:i64 %0
 ; PIC-NEXT:    t7: i64,i32,ch = ADD64rm<Mem:(dereferenceable load (s64) from %ir.loc)> t2, TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, t0
 ; PIC-NEXT:    t10: ch,glue = CopyToReg t0, Register:i64 $rax, t7
 ; PIC-NEXT:    t11: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t10, t10:1
 ; PIC-EMPTY:
 ;
-; WIN-LABEL: i64_test:
+; WIN-LABEL: Selected selection DAG:{{.*}}i64_test:
 ; WIN:       SelectionDAG has 12 nodes:
 ; WIN-NEXT:    t0: ch = EntryToken
 ; WIN-NEXT:    t2: i64,ch = CopyFromReg t0, Register:i64 %0
 ; WIN-NEXT:    t7: i64,i32,ch = ADD64rm<Mem:(dereferenceable load (s64) from %ir.loc)> t2, TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, t0
 ; WIN-NEXT:    t10: ch,glue = CopyToReg t0, Register:i64 $rax, t7
 ; WIN-NEXT:    t11: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t10, t10:1
 ; WIN-EMPTY:
   %loc = alloca i64
   %j = load i64, i64 * %loc
   %r = add i64 %i, %j
   ret i64 %r
 }
 
 define i64 @i32_test(i32 %i) nounwind readnone {
-; PIC-LABEL: i32_test:
+; PIC-LABEL: Selected selection DAG:{{.*}}i32_test:
 ; PIC:       SelectionDAG has 15 nodes:
 ; PIC-NEXT:    t0: ch = EntryToken
 ; PIC-NEXT:    t2: i32,ch = CopyFromReg t0, Register:i32 %0
 ; PIC-NEXT:    t7: i32,i32,ch = ADD32rm<Mem:(dereferenceable load (s32) from %ir.loc)> t2, TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, t0
 ; PIC-NEXT:    t8: i64 = SUBREG_TO_REG TargetConstant:i64<0>, t7, TargetConstant:i32<6>
 ; PIC-NEXT:    t11: ch,glue = CopyToReg t0, Register:i64 $rax, t8
 ; PIC-NEXT:    t12: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t11, t11:1
 ; PIC-EMPTY:
 ;
-; WIN-LABEL: i32_test:
+; WIN-LABEL: Selected selection DAG:{{.*}}i32_test:
 ; WIN:       SelectionDAG has 15 nodes:
 ; WIN-NEXT:    t0: ch = EntryToken
 ; WIN-NEXT:    t2: i32,ch = CopyFromReg t0, Register:i32 %0
 ; WIN-NEXT:    t7: i32,i32,ch = ADD32rm<Mem:(dereferenceable load (s32) from %ir.loc)> t2, TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, t0
 ; WIN-NEXT:    t8: i64 = SUBREG_TO_REG TargetConstant:i64<0>, t7, TargetConstant:i32<6>
 ; WIN-NEXT:    t11: ch,glue = CopyToReg t0, Register:i64 $rax, t8
 ; WIN-NEXT:    t12: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t11, t11:1
 ; WIN-EMPTY:
   %loc = alloca i32
   %j = load i32, i32 * %loc
   %r = add i32 %i, %j
   %ext = zext i32 %r to i64
   ret i64 %ext
 }
 
 define i64 @i16_test(i16 %i) nounwind readnone {
-; PIC-LABEL: i16_test:
+; PIC-LABEL: Selected selection DAG:{{.*}}i16_test:
 ; PIC:       SelectionDAG has 18 nodes:
 ; PIC-NEXT:    t0: ch = EntryToken
 ; PIC-NEXT:    t2: i32,ch = CopyFromReg t0, Register:i32 %0
 ; PIC-NEXT:    t3: i16 = EXTRACT_SUBREG t2, TargetConstant:i32<4>
 ; PIC-NEXT:    t8: i16,i32,ch = ADD16rm<Mem:(dereferenceable load (s16) from %ir.loc)> t3, TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, t0
 ; PIC-NEXT:    t15: i32 = MOVZX32rr16 t8
 ; PIC-NEXT:    t9: i64 = SUBREG_TO_REG TargetConstant:i64<0>, t15, TargetConstant:i32<6>
 ; PIC-NEXT:    t12: ch,glue = CopyToReg t0, Register:i64 $rax, t9
 ; PIC-NEXT:    t13: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t12, t12:1
 ; PIC-EMPTY:
 ;
-; WIN-LABEL: i16_test:
+; WIN-LABEL: Selected selection DAG:{{.*}}i16_test:
 ; WIN:       SelectionDAG has 16 nodes:
 ; WIN-NEXT:    t0: ch = EntryToken
 ; WIN-NEXT:    t2: i16,ch = CopyFromReg t0, Register:i16 %0
 ; WIN-NEXT:    t7: i16,i32,ch = ADD16rm<Mem:(dereferenceable load (s16) from %ir.loc)> t2, TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, t0
 ; WIN-NEXT:    t14: i32 = MOVZX32rr16 t7
 ; WIN-NEXT:    t8: i64 = SUBREG_TO_REG TargetConstant:i64<0>, t14, TargetConstant:i32<6>
 ; WIN-NEXT:    t11: ch,glue = CopyToReg t0, Register:i64 $rax, t8
 ; WIN-NEXT:    t12: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t11, t11:1
 ; WIN-EMPTY:
   %loc = alloca i16
   %j = load i16, i16 * %loc
   %r = add i16 %i, %j
   %ext = zext i16 %r to i64
   ret i64 %ext
 }
 
 define i64 @i8_test(i8 %i) nounwind readnone {
-; PIC-LABEL: i8_test:
+; PIC-LABEL: Selected selection DAG:{{.*}}i8_test:
 ; PIC:       SelectionDAG has 18 nodes:
 ; PIC-NEXT:    t0: ch = EntryToken
 ; PIC-NEXT:    t2: i32,ch = CopyFromReg t0, Register:i32 %0
 ; PIC-NEXT:    t3: i8 = EXTRACT_SUBREG t2, TargetConstant:i32<1>
 ; PIC-NEXT:    t8: i8,i32,ch = ADD8rm<Mem:(dereferenceable load (s8) from %ir.loc)> t3, TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, t0
 ; PIC-NEXT:    t15: i32 = MOVZX32rr8 t8
 ; PIC-NEXT:    t9: i64 = SUBREG_TO_REG TargetConstant:i64<0>, t15, TargetConstant:i32<6>
 ; PIC-NEXT:    t12: ch,glue = CopyToReg t0, Register:i64 $rax, t9
 ; PIC-NEXT:    t13: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t12, t12:1
 ; PIC-EMPTY:
 ;
-; WIN-LABEL: i8_test:
+; WIN-LABEL: Selected selection DAG:{{.*}}i8_test:
 ; WIN:       SelectionDAG has 16 nodes:
 ; WIN-NEXT:    t0: ch = EntryToken
 ; WIN-NEXT:    t2: i8,ch = CopyFromReg t0, Register:i8 %0
 ; WIN-NEXT:    t7: i8,i32,ch = ADD8rm<Mem:(dereferenceable load (s8) from %ir.loc)> t2, TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, t0
 ; WIN-NEXT:    t14: i32 = MOVZX32rr8 t7
 ; WIN-NEXT:    t8: i64 = SUBREG_TO_REG TargetConstant:i64<0>, t14, TargetConstant:i32<6>
 ; WIN-NEXT:    t11: ch,glue = CopyToReg t0, Register:i64 $rax, t8
 ; WIN-NEXT:    t12: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t11, t11:1
 ; WIN-EMPTY:
   %loc = alloca i8
   %j = load i8, i8 * %loc
   %r = add i8 %i, %j
   %ext = zext i8 %r to i64
   ret i64 %ext
 }

llvm/utils/UpdateTestChecks/isel.py

 import re
 from . import common
 import sys
 
 if sys.version_info[0] > 2:
   class string:
     expandtabs = str.expandtabs
 else:
   import string
 
 # Support of isel debug checks
 # RegEx: this is where the magic happens.
 
 ##### iSel parser
 
 # TODO: add function prefix
 ISEL_FUNCTION_DEFAULT_RE = re.compile(
      r'Selected[\s]*selection[\s]*DAG:[\s]*%bb.0[\s]*\'(?P<func>.*?):[^\']*\'*\n'
      r'(?P<body>.*?)\n'
      r'Total[\s]*amount[\s]*of[\s]*phi[\s]*nodes[\s]*to[\s]*update:[\s]*[0-9]+',
      flags=(re.M | re.S))
 
 def scrub_isel_default(isel, args):
   # Scrub runs of whitespace out of the iSel debug output, but leave the leading
   # whitespace in place.
   isel = common.SCRUB_WHITESPACE_RE.sub(r' ', isel)
if handler is None:
     handler = (scrub_isel_default, ISEL_FUNCTION_DEFAULT_RE)
 
   return handler
 
 ##### Generator of iSel CHECK lines
 
 def add_checks(output_lines, comment_marker, prefix_list, func_dict, func_name, is_filtered):
   # Label format is based on iSel string.
-  check_label_format = '{} %s-LABEL: %s%s:'.format(comment_marker)
+  check_label_format = '{} %s-LABEL: Selected selection DAG:{{{{.*}}}}%s%s:'.format(comment_marker)
   global_vars_seen_dict = {}
   common.add_checks(output_lines, comment_marker, prefix_list, func_dict,
                     func_name, check_label_format, True, False,
                     global_vars_seen_dict, is_filtered = is_filtered)