[SDAG] avoid libcalls to fmin/fmax for soft-float targets

[spatel]

Summary

This is an extension of D70965 to avoid creating a mathlib call where it did not exist in the original source. Also see D70852 for discussion about an alternative proposal that was abandoned.

In the motivating bug report:
https://github.com/llvm/llvm-project/issues/54554
...we also have a more general issue about handling "no-builtin" options. I'm not sure how that works yet.

[efriedma]

LGTM. (As a followup, we could consider querying TargetLibraryInfo to see if fmax is available, instead of assuming it isn't.)

---

The general question could probably use some thought... currently, the compiler is very constrained in terms of helper routines. We're basically constrained to calling memcpy/memset/memmove, plus whatever routines are exposed by libgcc, plus whatever TargetLibraryInfo tells us is available. This is pretty limiting: we're currently forced to inline routines we don't really want to inline due to codesize, like multiply-with-overflow, or minnum. Or we have to add weird checks along the lines of D70852. (This is made worse by the fact that SelectionDAG lowering can't really generate control flow.) We basically can't add new routines to compiler-rt builtins because a large fraction of users end up linking with libgcc.

It might be worth considering if we could come up with a mechanism to embed the routines we need into each object file; sort of like compiler-rt builtins, but you wouldn't have to actually link against compiler-rt. So each object file that needs a helper contains a hidden weak symbol, e.g. __llvm_mul_with_overflow_32_v1, and the linker picks one. Sort of wasteful in terms of disk space in object files and static libraries, but it would allow us to add helpers while staying compatible with build systems we don't control.

Just food for thought; I don't have a complete proposal at this point.

[irichter]

The tests look good; I still need to see how it handles the usecase that originally prompted my bug report.

In D122610#3412307, @efriedma wrote:

(As a followup, we could consider querying TargetLibraryInfo to see if fmax is available, instead of assuming it isn't.)

It might be nice to have a switch, possibly controlled by one of the -Os, that would prefer the fmax call.

It might be worth considering if we could come up with a mechanism to embed the routines we need into each object file; sort of like compiler-rt builtins, but you wouldn't have to actually link against compiler-rt. So each object file that needs a helper contains a hidden weak symbol, e.g. __llvm_mul_with_overflow_32_v1, and the linker picks one. Sort of wasteful in terms of disk space in object files and static libraries, but it would allow us to add helpers while staying compatible with build systems we don't control.

Regarding disk space, while it's worse than using a compiler-rt builtin, it's not generally worse than just embedding the code at every point that needs it, since it only appears once per file. Moreover, if this is done by adding intrinsics, the additional disk space would only be realized after machine code generation, and would not be an issue at all with LTO.

Just food for thought; I don't have a complete proposal at this point.

I like this idea, and not just for this particular issue, but more generally for things that are tightly integrated with the compiler, but require runtime support (e.g.: sanitizers).

llvm/include/llvm/CodeGen/TargetLowering.h

   /// any further refinement of the estimate.
   /// An empty SDValue return means no estimate sequence can be created.
   virtual SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG,
                                   int Enabled, int &RefinementSteps,
                                   bool &UseOneConstNR, bool Reciprocal) const {
     return SDValue();
   }
 
+  /// Try to convert the fminnum/fmaxnum to a compare/select sequence. This is
+  /// required for correctness since InstCombine might have canonicalized a
+  /// fcmp+select sequence to a FMINNUM/FMAXNUM intrinsic.  If we were to fall
+  /// through to the default expansion/soften to libcall, we might introduce a
+  /// link-time dependency on libm into a file that originally did not have one.
+  SDValue createSelectForFMINNUM_FMAXNUM(SDNode *Node, SelectionDAG &DAG) const;
+
   /// Return a reciprocal estimate value for the input operand.
   /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
   /// 'Enabled' as set by a potential default override attribute.
   /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
   /// refinement iterations required to generate a sufficient (though not
   /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
   /// A target may choose to implement its own refinement within this function.
   /// If that's true, then return '0' as the number of RefinementSteps to avoid

llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

SDValue DAGTypeLegalizer::SoftenFloatRes_FABS(SDNode *N) {
   APInt API = APInt::getAllOnes(Size);
   API.clearBit(Size - 1);
   SDValue Mask = DAG.getConstant(API, SDLoc(N), NVT);
   SDValue Op = GetSoftenedFloat(N->getOperand(0));
   return DAG.getNode(ISD::AND, SDLoc(N), NVT, Op, Mask);
 }
 
 SDValue DAGTypeLegalizer::SoftenFloatRes_FMINNUM(SDNode *N) {
+  if (SDValue SelCC = TLI.createSelectForFMINNUM_FMAXNUM(N, DAG))
+    return SoftenFloatRes_SELECT_CC(SelCC.getNode());
   return SoftenFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),
                                                RTLIB::FMIN_F32,
                                                RTLIB::FMIN_F64,
                                                RTLIB::FMIN_F80,
                                                RTLIB::FMIN_F128,
                                                RTLIB::FMIN_PPCF128));
 }
 
 SDValue DAGTypeLegalizer::SoftenFloatRes_FMAXNUM(SDNode *N) {
+  if (SDValue SelCC = TLI.createSelectForFMINNUM_FMAXNUM(N, DAG))
+    return SoftenFloatRes_SELECT_CC(SelCC.getNode());
   return SoftenFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),
                                                RTLIB::FMAX_F32,
                                                RTLIB::FMAX_F64,
                                                RTLIB::FMAX_F80,
                                                RTLIB::FMAX_F128,
                                                RTLIB::FMAX_PPCF128));
 }
 

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

bool TargetLowering::expandUINT_TO_FP(SDNode *Node, SDValue &Result,
   SDValue LoFlt = DAG.getBitcast(DstVT, LoOr);
   SDValue HiFlt = DAG.getBitcast(DstVT, HiOr);
   SDValue HiSub =
       DAG.getNode(ISD::FSUB, dl, DstVT, HiFlt, TwoP84PlusTwoP52);
   Result = DAG.getNode(ISD::FADD, dl, DstVT, LoFlt, HiSub);
   return true;
 }
 
+SDValue
+TargetLowering::createSelectForFMINNUM_FMAXNUM(SDNode *Node,
+                                               SelectionDAG &DAG) const {
+  unsigned Opcode = Node->getOpcode();
+  assert((Opcode == ISD::FMINNUM || Opcode == ISD::FMAXNUM ||
+          Opcode == ISD::STRICT_FMINNUM || Opcode == ISD::STRICT_FMAXNUM) &&
+         "Wrong opcode");
+
+  if (Node->getFlags().hasNoNaNs()) {
+    ISD::CondCode Pred = Opcode == ISD::FMINNUM ? ISD::SETLT : ISD::SETGT;
+    SDValue Op1 = Node->getOperand(0);
+    SDValue Op2 = Node->getOperand(1);
+    SDValue SelCC = DAG.getSelectCC(SDLoc(Node), Op1, Op2, Op1, Op2, Pred);
+    // Copy FMF flags, but always set the no-signed-zeros flag
+    // as this is implied by the FMINNUM/FMAXNUM semantics.
+    SDNodeFlags Flags = Node->getFlags();
+    Flags.setNoSignedZeros(true);
+    SelCC->setFlags(Flags);
+    return SelCC;
+  }
+
+  return SDValue();
+}
+
 SDValue TargetLowering::expandFMINNUM_FMAXNUM(SDNode *Node,
                                               SelectionDAG &DAG) const {
   SDLoc dl(Node);
   unsigned NewOp = Node->getOpcode() == ISD::FMINNUM ?
     ISD::FMINNUM_IEEE : ISD::FMAXNUM_IEEE;
   EVT VT = Node->getValueType(0);
 
   if (VT.isScalableVector())
if (Node->getFlags().hasNoNaNs()) {
     unsigned IEEE2018Op =
         Node->getOpcode() == ISD::FMINNUM ? ISD::FMINIMUM : ISD::FMAXIMUM;
     if (isOperationLegalOrCustom(IEEE2018Op, VT)) {
       return DAG.getNode(IEEE2018Op, dl, VT, Node->getOperand(0),
                          Node->getOperand(1), Node->getFlags());
     }
   }
 
-  // If none of the above worked, but there are no NaNs, then expand to
-  // a compare/select sequence.  This is required for correctness since
-  // InstCombine might have canonicalized a fcmp+select sequence to a
-  // FMINNUM/FMAXNUM node.  If we were to fall through to the default
-  // expansion to libcall, we might introduce a link-time dependency
-  // on libm into a file that originally did not have one.
-  if (Node->getFlags().hasNoNaNs()) {
-    ISD::CondCode Pred =
-        Node->getOpcode() == ISD::FMINNUM ? ISD::SETLT : ISD::SETGT;
-    SDValue Op1 = Node->getOperand(0);
-    SDValue Op2 = Node->getOperand(1);
-    SDValue SelCC = DAG.getSelectCC(dl, Op1, Op2, Op1, Op2, Pred);
-    // Copy FMF flags, but always set the no-signed-zeros flag
-    // as this is implied by the FMINNUM/FMAXNUM semantics.
-    SDNodeFlags Flags = Node->getFlags();
-    Flags.setNoSignedZeros(true);
-    SelCC->setFlags(Flags);
+  if (SDValue SelCC = createSelectForFMINNUM_FMAXNUM(Node, DAG))
     return SelCC;
-  }
 
   return SDValue();
 }
 
 // Only expand vector types if we have the appropriate vector bit operations.
 static bool canExpandVectorCTPOP(const TargetLowering &TLI, EVT VT) {
   assert(VT.isVector() && "Expected vector type");
   unsigned Len = VT.getScalarSizeInBits();

llvm/test/CodeGen/ARM/vecreduce-fmax-legalization-soft-float.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=arm-none-eabi -mattr=-neon | FileCheck %s --check-prefix=CHECK
 
 declare half @llvm.vector.reduce.fmax.v4f16(<4 x half>)
 declare float @llvm.vector.reduce.fmax.v4f32(<4 x float>)
 declare double @llvm.vector.reduce.fmax.v2f64(<2 x double>)
 declare fp128 @llvm.vector.reduce.fmax.v2f128(<2 x fp128>)
 
 define half @test_v4f16(<4 x half> %a) nounwind {
 ; CHECK-LABEL: test_v4f16:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    .save {r4, r5, r6, r7, r8, lr}
-; CHECK-NEXT:    push {r4, r5, r6, r7, r8, lr}
-; CHECK-NEXT:    mov r4, #255
-; CHECK-NEXT:    mov r7, r0
-; CHECK-NEXT:    orr r4, r4, #65280
-; CHECK-NEXT:    mov r5, r2
-; CHECK-NEXT:    and r0, r3, r4
-; CHECK-NEXT:    mov r6, r1
-; CHECK-NEXT:    bl __aeabi_h2f
-; CHECK-NEXT:    mov r8, r0
-; CHECK-NEXT:    and r0, r5, r4
-; CHECK-NEXT:    bl __aeabi_h2f
-; CHECK-NEXT:    mov r5, r0
-; CHECK-NEXT:    and r0, r7, r4
+; CHECK-NEXT:    .save {r4, r5, r6, r7, r8, r9, r11, lr}
+; CHECK-NEXT:    push {r4, r5, r6, r7, r8, r9, r11, lr}
+; CHECK-NEXT:    mov r9, #255
+; CHECK-NEXT:    mov r8, r3
+; CHECK-NEXT:    orr r9, r9, #65280
+; CHECK-NEXT:    mov r6, r2
+; CHECK-NEXT:    and r0, r0, r9
+; CHECK-NEXT:    mov r5, r1
 ; CHECK-NEXT:    bl __aeabi_h2f
 ; CHECK-NEXT:    mov r7, r0
-; CHECK-NEXT:    and r0, r6, r4
+; CHECK-NEXT:    and r0, r5, r9
 ; CHECK-NEXT:    bl __aeabi_h2f
-; CHECK-NEXT:    mov r1, r0
+; CHECK-NEXT:    mov r5, r0
 ; CHECK-NEXT:    mov r0, r7
-; CHECK-NEXT:    bl fmaxf
 ; CHECK-NEXT:    mov r1, r5
-; CHECK-NEXT:    bl fmaxf
-; CHECK-NEXT:    mov r1, r8
-; CHECK-NEXT:    bl fmaxf
+; CHECK-NEXT:    bl __aeabi_fcmpgt
+; CHECK-NEXT:    mov r4, r0
+; CHECK-NEXT:    and r0, r6, r9
+; CHECK-NEXT:    bl __aeabi_h2f
+; CHECK-NEXT:    cmp r4, #0
+; CHECK-NEXT:    mov r6, r0
+; CHECK-NEXT:    movne r5, r7
+; CHECK-NEXT:    mov r1, r6
+; CHECK-NEXT:    mov r0, r5
+; CHECK-NEXT:    bl __aeabi_fcmpgt
+; CHECK-NEXT:    cmp r0, #0
+; CHECK-NEXT:    and r0, r8, r9
+; CHECK-NEXT:    moveq r5, r6
+; CHECK-NEXT:    bl __aeabi_h2f
+; CHECK-NEXT:    mov r4, r0
+; CHECK-NEXT:    mov r0, r5
+; CHECK-NEXT:    mov r1, r4
+; CHECK-NEXT:    bl __aeabi_fcmpgt
+; CHECK-NEXT:    cmp r0, #0
+; CHECK-NEXT:    moveq r5, r4
+; CHECK-NEXT:    mov r0, r5
 ; CHECK-NEXT:    bl __aeabi_f2h
-; CHECK-NEXT:    pop {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT:    pop {r4, r5, r6, r7, r8, r9, r11, lr}
 ; CHECK-NEXT:    mov pc, lr
   %b = call fast half @llvm.vector.reduce.fmax.v4f16(<4 x half> %a)
   ret half %b
 }
 
 define float @test_v4f32(<4 x float> %a) nounwind {
 ; CHECK-LABEL: test_v4f32:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    .save {r4, r5, r11, lr}
-; CHECK-NEXT:    push {r4, r5, r11, lr}
+; CHECK-NEXT:    .save {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT:    push {r4, r5, r6, r7, r11, lr}
 ; CHECK-NEXT:    mov r4, r3
-; CHECK-NEXT:    mov r5, r2
-; CHECK-NEXT:    bl fmaxf
-; CHECK-NEXT:    mov r1, r5
-; CHECK-NEXT:    bl fmaxf
+; CHECK-NEXT:    mov r6, r2
+; CHECK-NEXT:    mov r5, r1
+; CHECK-NEXT:    mov r7, r0
+; CHECK-NEXT:    bl __aeabi_fcmpgt
+; CHECK-NEXT:    cmp r0, #0
+; CHECK-NEXT:    mov r1, r6
+; CHECK-NEXT:    movne r5, r7
+; CHECK-NEXT:    mov r0, r5
+; CHECK-NEXT:    bl __aeabi_fcmpgt
+; CHECK-NEXT:    cmp r0, #0
 ; CHECK-NEXT:    mov r1, r4
-; CHECK-NEXT:    bl fmaxf
-; CHECK-NEXT:    pop {r4, r5, r11, lr}
+; CHECK-NEXT:    moveq r5, r6
+; CHECK-NEXT:    mov r0, r5
+; CHECK-NEXT:    bl __aeabi_fcmpgt
+; CHECK-NEXT:    cmp r0, #0
+; CHECK-NEXT:    moveq r5, r4
+; CHECK-NEXT:    mov r0, r5
+; CHECK-NEXT:    pop {r4, r5, r6, r7, r11, lr}
 ; CHECK-NEXT:    mov pc, lr
   %b = call fast float @llvm.vector.reduce.fmax.v4f32(<4 x float> %a)
   ret float %b
 }
 
 define double @test_v2f64(<2 x double> %a) nounwind {
 ; CHECK-LABEL: test_v2f64:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    .save {r11, lr}
-; CHECK-NEXT:    push {r11, lr}
-; CHECK-NEXT:    bl fmax
-; CHECK-NEXT:    pop {r11, lr}
+; CHECK-NEXT:    .save {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT:    push {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT:    mov r4, r3
+; CHECK-NEXT:    mov r6, r2
+; CHECK-NEXT:    mov r8, r1
+; CHECK-NEXT:    mov r7, r0
+; CHECK-NEXT:    bl __aeabi_dcmpgt
+; CHECK-NEXT:    cmp r0, #0
+; CHECK-NEXT:    mov r5, r6
+; CHECK-NEXT:    mov r0, r7
+; CHECK-NEXT:    mov r1, r8
+; CHECK-NEXT:    mov r2, r6
+; CHECK-NEXT:    mov r3, r4
+; CHECK-NEXT:    movne r5, r7
+; CHECK-NEXT:    bl __aeabi_dcmpgt
+; CHECK-NEXT:    cmp r0, #0
+; CHECK-NEXT:    mov r0, r5
+; CHECK-NEXT:    movne r4, r8
+; CHECK-NEXT:    mov r1, r4
+; CHECK-NEXT:    pop {r4, r5, r6, r7, r8, lr}
 ; CHECK-NEXT:    mov pc, lr
   %b = call fast double @llvm.vector.reduce.fmax.v2f64(<2 x double> %a)
   ret double %b
 }
 
 define fp128 @test_v2f128(<2 x fp128> %a) nounwind {
 ; CHECK-LABEL: test_v2f128:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    .save {r11, lr}
-; CHECK-NEXT:    push {r11, lr}
-; CHECK-NEXT:    .pad #16
-; CHECK-NEXT:    sub sp, sp, #16
-; CHECK-NEXT:    ldr r12, [sp, #36]
-; CHECK-NEXT:    str r12, [sp, #12]
-; CHECK-NEXT:    ldr r12, [sp, #32]
-; CHECK-NEXT:    str r12, [sp, #8]
-; CHECK-NEXT:    ldr r12, [sp, #28]
-; CHECK-NEXT:    str r12, [sp, #4]
-; CHECK-NEXT:    ldr r12, [sp, #24]
-; CHECK-NEXT:    str r12, [sp]
-; CHECK-NEXT:    bl fmaxl
-; CHECK-NEXT:    add sp, sp, #16
-; CHECK-NEXT:    pop {r11, lr}
+; CHECK-NEXT:    .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
+; CHECK-NEXT:    push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
+; CHECK-NEXT:    .pad #28
+; CHECK-NEXT:    sub sp, sp, #28
+; CHECK-NEXT:    ldr r5, [sp, #76]
+; CHECK-NEXT:    mov r8, r3
+; CHECK-NEXT:    ldr r6, [sp, #72]
+; CHECK-NEXT:    mov r9, r2
+; CHECK-NEXT:    ldr r4, [sp, #68]
+; CHECK-NEXT:    mov r10, r1
+; CHECK-NEXT:    ldr r7, [sp, #64]
+; CHECK-NEXT:    mov r11, r0
+; CHECK-NEXT:    str r5, [sp, #12]
+; CHECK-NEXT:    str r6, [sp, #8]
+; CHECK-NEXT:    str r4, [sp, #4]
+; CHECK-NEXT:    str r7, [sp]
+; CHECK-NEXT:    bl __gttf2
+; CHECK-NEXT:    str r0, [sp, #24] @ 4-byte Spill
+; CHECK-NEXT:    mov r0, r11
+; CHECK-NEXT:    mov r1, r10
+; CHECK-NEXT:    mov r2, r9
+; CHECK-NEXT:    mov r3, r8
+; CHECK-NEXT:    str r7, [sp]
+; CHECK-NEXT:    stmib sp, {r4, r6}
+; CHECK-NEXT:    str r5, [sp, #12]
+; CHECK-NEXT:    bl __gttf2
+; CHECK-NEXT:    str r0, [sp, #20] @ 4-byte Spill
+; CHECK-NEXT:    mov r0, r11
+; CHECK-NEXT:    mov r1, r10
+; CHECK-NEXT:    mov r2, r9
+; CHECK-NEXT:    mov r3, r8
+; CHECK-NEXT:    str r7, [sp]
+; CHECK-NEXT:    stmib sp, {r4, r6}
+; CHECK-NEXT:    str r5, [sp, #12]
+; CHECK-NEXT:    bl __gttf2
+; CHECK-NEXT:    cmp r0, #0
+; CHECK-NEXT:    ldr r0, [sp, #20] @ 4-byte Reload
+; CHECK-NEXT:    str r7, [sp]
+; CHECK-NEXT:    movgt r7, r11
+; CHECK-NEXT:    cmp r0, #0
+; CHECK-NEXT:    ldr r0, [sp, #24] @ 4-byte Reload
+; CHECK-NEXT:    stmib sp, {r4, r6}
+; CHECK-NEXT:    movgt r4, r10
+; CHECK-NEXT:    cmp r0, #0
+; CHECK-NEXT:    mov r0, r11
+; CHECK-NEXT:    mov r1, r10
+; CHECK-NEXT:    mov r2, r9
+; CHECK-NEXT:    mov r3, r8
+; CHECK-NEXT:    str r5, [sp, #12]
+; CHECK-NEXT:    movgt r6, r9
+; CHECK-NEXT:    bl __gttf2
+; CHECK-NEXT:    cmp r0, #0
+; CHECK-NEXT:    mov r0, r7
+; CHECK-NEXT:    movgt r5, r8
+; CHECK-NEXT:    mov r1, r4
+; CHECK-NEXT:    mov r2, r6
+; CHECK-NEXT:    mov r3, r5
+; CHECK-NEXT:    add sp, sp, #28
+; CHECK-NEXT:    pop {r4, r5, r6, r7, r8, r9, r10, r11, lr}
 ; CHECK-NEXT:    mov pc, lr
   %b = call fast fp128 @llvm.vector.reduce.fmax.v2f128(<2 x fp128> %a)
   ret fp128 %b
 }

llvm/test/CodeGen/ARM/vecreduce-fmin-legalization-soft-float.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=arm-none-eabi -mattr=-neon | FileCheck %s --check-prefix=CHECK
 
 declare half @llvm.vector.reduce.fmin.v4f16(<4 x half>)
 declare float @llvm.vector.reduce.fmin.v4f32(<4 x float>)
 declare double @llvm.vector.reduce.fmin.v2f64(<2 x double>)
 declare fp128 @llvm.vector.reduce.fmin.v2f128(<2 x fp128>)
 
 define half @test_v4f16(<4 x half> %a) nounwind {
 ; CHECK-LABEL: test_v4f16:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    .save {r4, r5, r6, r7, r8, lr}
-; CHECK-NEXT:    push {r4, r5, r6, r7, r8, lr}
-; CHECK-NEXT:    mov r4, #255
-; CHECK-NEXT:    mov r7, r0
-; CHECK-NEXT:    orr r4, r4, #65280
-; CHECK-NEXT:    mov r5, r2
-; CHECK-NEXT:    and r0, r3, r4
-; CHECK-NEXT:    mov r6, r1
-; CHECK-NEXT:    bl __aeabi_h2f
-; CHECK-NEXT:    mov r8, r0
-; CHECK-NEXT:    and r0, r5, r4
-; CHECK-NEXT:    bl __aeabi_h2f
-; CHECK-NEXT:    mov r5, r0
-; CHECK-NEXT:    and r0, r7, r4
+; CHECK-NEXT:    .save {r4, r5, r6, r7, r8, r9, r11, lr}
+; CHECK-NEXT:    push {r4, r5, r6, r7, r8, r9, r11, lr}
+; CHECK-NEXT:    mov r9, #255
+; CHECK-NEXT:    mov r8, r3
+; CHECK-NEXT:    orr r9, r9, #65280
+; CHECK-NEXT:    mov r6, r2
+; CHECK-NEXT:    and r0, r0, r9
+; CHECK-NEXT:    mov r5, r1
 ; CHECK-NEXT:    bl __aeabi_h2f
 ; CHECK-NEXT:    mov r7, r0
-; CHECK-NEXT:    and r0, r6, r4
+; CHECK-NEXT:    and r0, r5, r9
 ; CHECK-NEXT:    bl __aeabi_h2f
-; CHECK-NEXT:    mov r1, r0
+; CHECK-NEXT:    mov r5, r0
 ; CHECK-NEXT:    mov r0, r7
-; CHECK-NEXT:    bl fminf
 ; CHECK-NEXT:    mov r1, r5
-; CHECK-NEXT:    bl fminf
-; CHECK-NEXT:    mov r1, r8
-; CHECK-NEXT:    bl fminf
+; CHECK-NEXT:    bl __aeabi_fcmplt
+; CHECK-NEXT:    mov r4, r0
+; CHECK-NEXT:    and r0, r6, r9
+; CHECK-NEXT:    bl __aeabi_h2f
+; CHECK-NEXT:    cmp r4, #0
+; CHECK-NEXT:    mov r6, r0
+; CHECK-NEXT:    movne r5, r7
+; CHECK-NEXT:    mov r1, r6
+; CHECK-NEXT:    mov r0, r5
+; CHECK-NEXT:    bl __aeabi_fcmplt
+; CHECK-NEXT:    cmp r0, #0
+; CHECK-NEXT:    and r0, r8, r9
+; CHECK-NEXT:    moveq r5, r6
+; CHECK-NEXT:    bl __aeabi_h2f
+; CHECK-NEXT:    mov r4, r0
+; CHECK-NEXT:    mov r0, r5
+; CHECK-NEXT:    mov r1, r4
+; CHECK-NEXT:    bl __aeabi_fcmplt
+; CHECK-NEXT:    cmp r0, #0
+; CHECK-NEXT:    moveq r5, r4
+; CHECK-NEXT:    mov r0, r5
 ; CHECK-NEXT:    bl __aeabi_f2h
-; CHECK-NEXT:    pop {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT:    pop {r4, r5, r6, r7, r8, r9, r11, lr}
 ; CHECK-NEXT:    mov pc, lr
   %b = call fast half @llvm.vector.reduce.fmin.v4f16(<4 x half> %a)
   ret half %b
 }
 
 define float @test_v4f32(<4 x float> %a) nounwind {
 ; CHECK-LABEL: test_v4f32:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    .save {r4, r5, r11, lr}
-; CHECK-NEXT:    push {r4, r5, r11, lr}
+; CHECK-NEXT:    .save {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT:    push {r4, r5, r6, r7, r11, lr}
 ; CHECK-NEXT:    mov r4, r3
-; CHECK-NEXT:    mov r5, r2
-; CHECK-NEXT:    bl fminf
-; CHECK-NEXT:    mov r1, r5
-; CHECK-NEXT:    bl fminf
+; CHECK-NEXT:    mov r6, r2
+; CHECK-NEXT:    mov r5, r1
+; CHECK-NEXT:    mov r7, r0
+; CHECK-NEXT:    bl __aeabi_fcmplt
+; CHECK-NEXT:    cmp r0, #0
+; CHECK-NEXT:    mov r1, r6
+; CHECK-NEXT:    movne r5, r7
+; CHECK-NEXT:    mov r0, r5
+; CHECK-NEXT:    bl __aeabi_fcmplt
+; CHECK-NEXT:    cmp r0, #0
 ; CHECK-NEXT:    mov r1, r4
-; CHECK-NEXT:    bl fminf
-; CHECK-NEXT:    pop {r4, r5, r11, lr}
+; CHECK-NEXT:    moveq r5, r6
+; CHECK-NEXT:    mov r0, r5
+; CHECK-NEXT:    bl __aeabi_fcmplt
+; CHECK-NEXT:    cmp r0, #0
+; CHECK-NEXT:    moveq r5, r4
+; CHECK-NEXT:    mov r0, r5
+; CHECK-NEXT:    pop {r4, r5, r6, r7, r11, lr}
 ; CHECK-NEXT:    mov pc, lr
   %b = call fast float @llvm.vector.reduce.fmin.v4f32(<4 x float> %a)
   ret float %b
 }
 
 define double @test_v2f64(<2 x double> %a) nounwind {
 ; CHECK-LABEL: test_v2f64:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    .save {r11, lr}
-; CHECK-NEXT:    push {r11, lr}
-; CHECK-NEXT:    bl fmin
-; CHECK-NEXT:    pop {r11, lr}
+; CHECK-NEXT:    .save {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT:    push {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT:    mov r4, r3
+; CHECK-NEXT:    mov r6, r2
+; CHECK-NEXT:    mov r8, r1
+; CHECK-NEXT:    mov r7, r0
+; CHECK-NEXT:    bl __aeabi_dcmplt
+; CHECK-NEXT:    cmp r0, #0
+; CHECK-NEXT:    mov r5, r6
+; CHECK-NEXT:    mov r0, r7
+; CHECK-NEXT:    mov r1, r8
+; CHECK-NEXT:    mov r2, r6
+; CHECK-NEXT:    mov r3, r4
+; CHECK-NEXT:    movne r5, r7
+; CHECK-NEXT:    bl __aeabi_dcmplt
+; CHECK-NEXT:    cmp r0, #0
+; CHECK-NEXT:    mov r0, r5
+; CHECK-NEXT:    movne r4, r8
+; CHECK-NEXT:    mov r1, r4
+; CHECK-NEXT:    pop {r4, r5, r6, r7, r8, lr}
 ; CHECK-NEXT:    mov pc, lr
   %b = call fast double @llvm.vector.reduce.fmin.v2f64(<2 x double> %a)
   ret double %b
 }
 
 define fp128 @test_v2f128(<2 x fp128> %a) nounwind {
 ; CHECK-LABEL: test_v2f128:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    .save {r11, lr}
-; CHECK-NEXT:    push {r11, lr}
-; CHECK-NEXT:    .pad #16
-; CHECK-NEXT:    sub sp, sp, #16
-; CHECK-NEXT:    ldr r12, [sp, #36]
-; CHECK-NEXT:    str r12, [sp, #12]
-; CHECK-NEXT:    ldr r12, [sp, #32]
-; CHECK-NEXT:    str r12, [sp, #8]
-; CHECK-NEXT:    ldr r12, [sp, #28]
-; CHECK-NEXT:    str r12, [sp, #4]
-; CHECK-NEXT:    ldr r12, [sp, #24]
-; CHECK-NEXT:    str r12, [sp]
-; CHECK-NEXT:    bl fminl
-; CHECK-NEXT:    add sp, sp, #16
-; CHECK-NEXT:    pop {r11, lr}
+; CHECK-NEXT:    .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
+; CHECK-NEXT:    push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
+; CHECK-NEXT:    .pad #28
+; CHECK-NEXT:    sub sp, sp, #28
+; CHECK-NEXT:    ldr r5, [sp, #76]
+; CHECK-NEXT:    mov r8, r3
+; CHECK-NEXT:    ldr r6, [sp, #72]
+; CHECK-NEXT:    mov r9, r2
+; CHECK-NEXT:    ldr r4, [sp, #68]
+; CHECK-NEXT:    mov r10, r1
+; CHECK-NEXT:    ldr r7, [sp, #64]
+; CHECK-NEXT:    mov r11, r0
+; CHECK-NEXT:    str r5, [sp, #12]
+; CHECK-NEXT:    str r6, [sp, #8]
+; CHECK-NEXT:    str r4, [sp, #4]
+; CHECK-NEXT:    str r7, [sp]
+; CHECK-NEXT:    bl __lttf2
+; CHECK-NEXT:    str r0, [sp, #24] @ 4-byte Spill
+; CHECK-NEXT:    mov r0, r11
+; CHECK-NEXT:    mov r1, r10
+; CHECK-NEXT:    mov r2, r9
+; CHECK-NEXT:    mov r3, r8
+; CHECK-NEXT:    str r7, [sp]
+; CHECK-NEXT:    stmib sp, {r4, r6}
+; CHECK-NEXT:    str r5, [sp, #12]
+; CHECK-NEXT:    bl __lttf2
+; CHECK-NEXT:    str r0, [sp, #20] @ 4-byte Spill
+; CHECK-NEXT:    mov r0, r11
+; CHECK-NEXT:    mov r1, r10
+; CHECK-NEXT:    mov r2, r9
+; CHECK-NEXT:    mov r3, r8
+; CHECK-NEXT:    str r7, [sp]
+; CHECK-NEXT:    stmib sp, {r4, r6}
+; CHECK-NEXT:    str r5, [sp, #12]
+; CHECK-NEXT:    bl __lttf2
+; CHECK-NEXT:    cmp r0, #0
+; CHECK-NEXT:    ldr r0, [sp, #20] @ 4-byte Reload
+; CHECK-NEXT:    str r7, [sp]
+; CHECK-NEXT:    movmi r7, r11
+; CHECK-NEXT:    cmp r0, #0
+; CHECK-NEXT:    ldr r0, [sp, #24] @ 4-byte Reload
+; CHECK-NEXT:    stmib sp, {r4, r6}
+; CHECK-NEXT:    movmi r4, r10
+; CHECK-NEXT:    cmp r0, #0
+; CHECK-NEXT:    mov r0, r11
+; CHECK-NEXT:    mov r1, r10
+; CHECK-NEXT:    mov r2, r9
+; CHECK-NEXT:    mov r3, r8
+; CHECK-NEXT:    str r5, [sp, #12]
+; CHECK-NEXT:    movmi r6, r9
+; CHECK-NEXT:    bl __lttf2
+; CHECK-NEXT:    cmp r0, #0
+; CHECK-NEXT:    mov r0, r7
+; CHECK-NEXT:    movmi r5, r8
+; CHECK-NEXT:    mov r1, r4
+; CHECK-NEXT:    mov r2, r6
+; CHECK-NEXT:    mov r3, r5
+; CHECK-NEXT:    add sp, sp, #28
+; CHECK-NEXT:    pop {r4, r5, r6, r7, r8, r9, r10, r11, lr}
 ; CHECK-NEXT:    mov pc, lr
   %b = call fast fp128 @llvm.vector.reduce.fmin.v2f128(<2 x fp128> %a)
   ret fp128 %b
 }

llvm/test/CodeGen/RISCV/fmax-fmin.ll

; R64-NEXT:    ret
   ret float %r
 }
 
 define float @maxnum_f32_fast(float %x, float %y) nounwind {
 ; R32-LABEL: maxnum_f32_fast:
 ; R32:       # %bb.0:
 ; R32-NEXT:    addi sp, sp, -16
 ; R32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; R32-NEXT:    call fmaxf@plt
+; R32-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; R32-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; R32-NEXT:    mv s1, a1
+; R32-NEXT:    mv s0, a0
+; R32-NEXT:    call __gtsf2@plt
+; R32-NEXT:    bgtz a0, .LBB1_2
+; R32-NEXT:  # %bb.1:
+; R32-NEXT:    mv s0, s1
+; R32-NEXT:  .LBB1_2:
+; R32-NEXT:    mv a0, s0
 ; R32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; R32-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; R32-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; R32-NEXT:    addi sp, sp, 16
 ; R32-NEXT:    ret
 ;
 ; R64-LABEL: maxnum_f32_fast:
 ; R64:       # %bb.0:
-; R64-NEXT:    addi sp, sp, -16
-; R64-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; R64-NEXT:    call fmaxf@plt
-; R64-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
-; R64-NEXT:    addi sp, sp, 16
+; R64-NEXT:    addi sp, sp, -32
+; R64-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; R64-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+; R64-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
+; R64-NEXT:    mv s1, a1
+; R64-NEXT:    mv s0, a0
+; R64-NEXT:    call __gtsf2@plt
+; R64-NEXT:    bgtz a0, .LBB1_2
+; R64-NEXT:  # %bb.1:
+; R64-NEXT:    mv s0, s1
+; R64-NEXT:  .LBB1_2:
+; R64-NEXT:    mv a0, s0
+; R64-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; R64-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; R64-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
+; R64-NEXT:    addi sp, sp, 32
 ; R64-NEXT:    ret
   %r = call fast float @llvm.maxnum.f32(float %x, float %y)
   ret float %r
 }
 
 define double @maxnum_f64(double %x, double %y) nounwind {
 ; R32-LABEL: maxnum_f64:
 ; R32:       # %bb.0:

 ; R64-NEXT:    ret
   %r = call double @llvm.maxnum.f64(double %x, double %y)
   ret double %r
 }
 
 define double @maxnum_f64_nnan(double %x, double %y) nounwind {
 ; R32-LABEL: maxnum_f64_nnan:
 ; R32:       # %bb.0:
-; R32-NEXT:    addi sp, sp, -16
-; R32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; R32-NEXT:    call fmax@plt
-; R32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
-; R32-NEXT:    addi sp, sp, 16
+; R32-NEXT:    addi sp, sp, -32
+; R32-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
+; R32-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
+; R32-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
+; R32-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
+; R32-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
+; R32-NEXT:    sw s4, 8(sp) # 4-byte Folded Spill
+; R32-NEXT:    mv s1, a3
+; R32-NEXT:    mv s2, a2
+; R32-NEXT:    mv s0, a1
+; R32-NEXT:    mv s4, a0
+; R32-NEXT:    call __gtdf2@plt
+; R32-NEXT:    mv s3, s4
+; R32-NEXT:    bgtz a0, .LBB3_2
+; R32-NEXT:  # %bb.1:
+; R32-NEXT:    mv s3, s2
+; R32-NEXT:  .LBB3_2:
+; R32-NEXT:    mv a0, s4
+; R32-NEXT:    mv a1, s0
+; R32-NEXT:    mv a2, s2
+; R32-NEXT:    mv a3, s1
+; R32-NEXT:    call __gtdf2@plt
+; R32-NEXT:    bgtz a0, .LBB3_4
+; R32-NEXT:  # %bb.3:
+; R32-NEXT:    mv s0, s1
+; R32-NEXT:  .LBB3_4:
+; R32-NEXT:    mv a0, s3
+; R32-NEXT:    mv a1, s0
+; R32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
+; R32-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
+; R32-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
+; R32-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
+; R32-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
+; R32-NEXT:    lw s4, 8(sp) # 4-byte Folded Reload
+; R32-NEXT:    addi sp, sp, 32
 ; R32-NEXT:    ret
 ;
 ; R64-LABEL: maxnum_f64_nnan:
 ; R64:       # %bb.0:
-; R64-NEXT:    addi sp, sp, -16
-; R64-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; R64-NEXT:    call fmax@plt
-; R64-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
-; R64-NEXT:    addi sp, sp, 16
+; R64-NEXT:    addi sp, sp, -32
+; R64-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; R64-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+; R64-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
+; R64-NEXT:    mv s1, a1
+; R64-NEXT:    mv s0, a0
+; R64-NEXT:    call __gtdf2@plt
+; R64-NEXT:    bgtz a0, .LBB3_2
+; R64-NEXT:  # %bb.1:
+; R64-NEXT:    mv s0, s1
+; R64-NEXT:  .LBB3_2:
+; R64-NEXT:    mv a0, s0
+; R64-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; R64-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; R64-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
+; R64-NEXT:    addi sp, sp, 32
 ; R64-NEXT:    ret
   %r = call nnan double @llvm.maxnum.f64(double %x, double %y)
   ret double %r
 }
 
 define float @minnum_f32(float %x, float %y) nounwind {
 ; R32-LABEL: minnum_f32:
 ; R32:       # %bb.0:
; R64-NEXT:    ret
   ret float %r
 }
 
 define float @minnum_f32_nnan(float %x, float %y) nounwind {
 ; R32-LABEL: minnum_f32_nnan:
 ; R32:       # %bb.0:
 ; R32-NEXT:    addi sp, sp, -16
 ; R32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; R32-NEXT:    call fminf@plt
+; R32-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; R32-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; R32-NEXT:    mv s1, a1
+; R32-NEXT:    mv s0, a0
+; R32-NEXT:    call __ltsf2@plt
+; R32-NEXT:    bltz a0, .LBB5_2
+; R32-NEXT:  # %bb.1:
+; R32-NEXT:    mv s0, s1
+; R32-NEXT:  .LBB5_2:
+; R32-NEXT:    mv a0, s0
 ; R32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; R32-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; R32-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; R32-NEXT:    addi sp, sp, 16
 ; R32-NEXT:    ret
 ;
 ; R64-LABEL: minnum_f32_nnan:
 ; R64:       # %bb.0:
-; R64-NEXT:    addi sp, sp, -16
-; R64-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; R64-NEXT:    call fminf@plt
-; R64-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
-; R64-NEXT:    addi sp, sp, 16
+; R64-NEXT:    addi sp, sp, -32
+; R64-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; R64-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+; R64-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
+; R64-NEXT:    mv s1, a1
+; R64-NEXT:    mv s0, a0
+; R64-NEXT:    call __ltsf2@plt
+; R64-NEXT:    bltz a0, .LBB5_2
+; R64-NEXT:  # %bb.1:
+; R64-NEXT:    mv s0, s1
+; R64-NEXT:  .LBB5_2:
+; R64-NEXT:    mv a0, s0
+; R64-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; R64-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; R64-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
+; R64-NEXT:    addi sp, sp, 32
 ; R64-NEXT:    ret
   %r = call nnan float @llvm.minnum.f32(float %x, float %y)
   ret float %r
 }
 
 define double @minnum_f64(double %x, double %y) nounwind {
 ; R32-LABEL: minnum_f64:
 ; R32:       # %bb.0:

 ; R64-NEXT:    ret
   %r = call double @llvm.minnum.f64(double %x, double %y)
   ret double %r
 }
 
 define double @minnum_f64_fast(double %x, double %y) nounwind {
 ; R32-LABEL: minnum_f64_fast:
 ; R32:       # %bb.0:
-; R32-NEXT:    addi sp, sp, -16
-; R32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; R32-NEXT:    call fmin@plt
-; R32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
-; R32-NEXT:    addi sp, sp, 16
+; R32-NEXT:    addi sp, sp, -32
+; R32-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
+; R32-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
+; R32-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
+; R32-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
+; R32-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
+; R32-NEXT:    sw s4, 8(sp) # 4-byte Folded Spill
+; R32-NEXT:    mv s1, a3
+; R32-NEXT:    mv s2, a2
+; R32-NEXT:    mv s0, a1
+; R32-NEXT:    mv s4, a0
+; R32-NEXT:    call __ltdf2@plt
+; R32-NEXT:    mv s3, s4
+; R32-NEXT:    bltz a0, .LBB7_2
+; R32-NEXT:  # %bb.1:
+; R32-NEXT:    mv s3, s2
+; R32-NEXT:  .LBB7_2:
+; R32-NEXT:    mv a0, s4
+; R32-NEXT:    mv a1, s0
+; R32-NEXT:    mv a2, s2
+; R32-NEXT:    mv a3, s1
+; R32-NEXT:    call __ltdf2@plt
+; R32-NEXT:    bltz a0, .LBB7_4
+; R32-NEXT:  # %bb.3:
+; R32-NEXT:    mv s0, s1
+; R32-NEXT:  .LBB7_4:
+; R32-NEXT:    mv a0, s3
+; R32-NEXT:    mv a1, s0
+; R32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
+; R32-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
+; R32-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
+; R32-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
+; R32-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
+; R32-NEXT:    lw s4, 8(sp) # 4-byte Folded Reload
+; R32-NEXT:    addi sp, sp, 32
 ; R32-NEXT:    ret
 ;
 ; R64-LABEL: minnum_f64_fast:
 ; R64:       # %bb.0:
-; R64-NEXT:    addi sp, sp, -16
-; R64-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; R64-NEXT:    call fmin@plt
-; R64-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
-; R64-NEXT:    addi sp, sp, 16
+; R64-NEXT:    addi sp, sp, -32
+; R64-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; R64-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+; R64-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
+; R64-NEXT:    mv s1, a1
+; R64-NEXT:    mv s0, a0
+; R64-NEXT:    call __ltdf2@plt
+; R64-NEXT:    bltz a0, .LBB7_2
+; R64-NEXT:  # %bb.1:
+; R64-NEXT:    mv s0, s1
+; R64-NEXT:  .LBB7_2:
+; R64-NEXT:    mv a0, s0
+; R64-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; R64-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; R64-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
+; R64-NEXT:    addi sp, sp, 32
 ; R64-NEXT:    ret
   %r = call fast double @llvm.minnum.f64(double %x, double %y)
   ret double %r
 }
 
 declare float @llvm.maxnum.f32(float, float)
 declare double @llvm.maxnum.f64(double, double)
 declare float @llvm.minnum.f32(float, float)
 declare double @llvm.minnum.f64(double, double)