MIRParser: Fix asserting with invalid flags on machine operands

[arsenm]

Summary

Constructing an operand with kills on defs and deads on uses asserts
in the constructor, so diagnose these.

[arsenm]

Forgot to commit style change

[arsenm]

ced1250b0f458c3dfeecb8157dd4838d87c8288d

llvm/lib/CodeGen/MIRParser/MIParser.cpp

bool MIParser::parseRegisterOperand(MachineOperand &Dest,
   } else if (Register::isVirtualRegister(Reg)) {
     // Generic virtual registers must have a type.
     // If we end up here this means the type hasn't been specified and
     // this is bad!
     if (RegInfo->Kind == VRegInfo::GENERIC ||
         RegInfo->Kind == VRegInfo::REGBANK)
       return error("generic virtual registers must have a type");
   }
+
+  if ((Flags & RegState::Define) && (Flags & RegState::Kill))
+    return error("cannot have a killed def operand");
+
+  if (!(Flags & RegState::Define) && (Flags & RegState::Dead))
+    return error("cannot have a dead use operand");
+
   Dest = MachineOperand::CreateReg(
       Reg, Flags & RegState::Define, Flags & RegState::Implicit,
       Flags & RegState::Kill, Flags & RegState::Dead, Flags & RegState::Undef,
       Flags & RegState::EarlyClobber, SubReg, Flags & RegState::Debug,
       Flags & RegState::InternalRead, Flags & RegState::Renamable);
 
   return false;
 }

llvm/test/CodeGen/MIR/AMDGPU/dead-flag-on-use-operand-parse-error.mir

+# RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -run-pass=none %s -o /dev/null 2>&1 | FileCheck %s
+---
+name:            foo
+tracksRegLiveness: true
+body:             |
+  bb.0:
+
+    %0:sgpr_32 = S_MOV_B32 0
+    ; CHECK: [[@LINE+1]]:24: cannot have a dead use operand
+    S_ENDPGM 0, dead %0
+
+...

llvm/test/CodeGen/MIR/AMDGPU/killed-flag-on-def-parse-error.mir

+# RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -run-pass=none %s -o /dev/null 2>&1 | FileCheck %s
+---
+name:            foo
+tracksRegLiveness: true
+body:             |
+  bb.0:
+
+    ; CHECK: [[@LINE+1]]:23: cannot have a killed def operand
+    killed %0:sgpr_32 = S_MOV_B32 0
+    S_ENDPGM 0
+
+...