[RISCV][NFC] Remove redundant check and rename functions in some IR tests

[Jimerlife]

Summary

Remove redundant check and rename functions in some IR tests

[Jimerlife]

update

[frasercrmck]

LGTM, thanks

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll

117 ↗

(On Diff #418110)

woah, how'd that happen, I wonder

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnsra-vnsrl.ll

2

We don't need --check-prefixes=CHECK here, since you're modifying the test anyway

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll

 ; CHECK-NEXT:    ret
   %a = load <4 x i32>, <4 x i32>* %x
   %b = extractelement <4 x i32> %a, i32 2
   store i32 %b, i32* %p
   ret void
 }
 
 ; FIXME: Use vse64.v on RV32 to avoid two scalar extracts and two scalar stores.
-define void @store_extractelt_v4i64(<2 x i64>* %x, i64* %p) nounwind {
-; RV32-LABEL: store_extractelt_v4i64:
+define void @store_extractelt_v2i64(<2 x i64>* %x, i64* %p) nounwind {
+; RV32-LABEL: store_extractelt_v2i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, mu
 ; RV32-NEXT:    vle64.v v8, (a0)
 ; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
 ; RV32-NEXT:    vslidedown.vi v8, v8, 1
 ; RV32-NEXT:    li a0, 32
 ; RV32-NEXT:    vsrl.vx v9, v8, a0
 ; RV32-NEXT:    vmv.x.s a0, v9
 ; RV32-NEXT:    vmv.x.s a2, v8
 ; RV32-NEXT:    sw a2, 0(a1)
 ; RV32-NEXT:    sw a0, 4(a1)
 ; RV32-NEXT:    ret
 ;
-; RV64-LABEL: store_extractelt_v4i64:
+; RV64-LABEL: store_extractelt_v2i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli zero, 2, e64, m1, ta, mu
 ; RV64-NEXT:    vle64.v v8, (a0)
 ; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
 ; RV64-NEXT:    vslidedown.vi v8, v8, 1
 ; RV64-NEXT:    vse64.v v8, (a1)
 ; RV64-NEXT:    ret
   %a = load <2 x i64>, <2 x i64>* %x
   %b = extractelement <2 x i64> %a, i64 1
   store i64 %b, i64* %p
   ret void
 }
 
-define void @store_extractelt_v4f64(<2 x double>* %x, double* %p) nounwind {
-; CHECK-LABEL: store_extractelt_v4f64:
+define void @store_extractelt_v2f64(<2 x double>* %x, double* %p) nounwind {
+; CHECK-LABEL: store_extractelt_v2f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, mu
 ; CHECK-NEXT:    vle64.v v8, (a0)
 ; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
 ; CHECK-NEXT:    vslidedown.vi v8, v8, 1
 ; CHECK-NEXT:    vse64.v v8, (a1)
 ; CHECK-NEXT:    ret
   %a = load <2 x double>, <2 x double>* %x
   %b = extractelement <2 x double> %a, i64 1
   store double %b, double* %p
   ret void
 }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnsra-vnsrl.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
 ; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
 
 define <8 x i8> @vnsra_v8i16_v8i8_scalar(<8 x i16> %x, i16 %y) {
 ; CHECK-LABEL: vnsra_v8i16_v8i8_scalar:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vnsra.wx v8, v8, a0
 ; CHECK-NEXT:    ret

 }
 
 define <2 x i32> @vnsra_v2i64_v2i32_scalar(<2 x i64> %x, i64 %y) {
 ; CHECK-LABEL: vnsra_v2i64_v2i32_scalar:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, mu
 ; CHECK-NEXT:    vnsra.wx v8, v8, a0
 ; CHECK-NEXT:    ret
-; RV32-LABEL: vnsra_v2i64_v2i32_scalar:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetivli zero, 2, e64,m1,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v25, (a0), zero
-; RV32-NEXT:    vsra.vv v25, v8, v25
-; RV32-NEXT:    vsetivli zero, 2, e32,mf2,ta,mu
-; RV32-NEXT:    vnsrl.wi v8, v25, 0
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-; RV64-LABEL: vnsra_v2i64_v2i32_scalar:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 2, e32,mf2,ta,mu
-; RV64-NEXT:    vnsra.wx v25, v8, a0
-; RV64-NEXT:    vmv1r.v v8, v25
-; RV64-NEXT:    ret
   %insert = insertelement <2 x i64> poison, i64 %y, i32 0
   %splat = shufflevector <2 x i64> %insert, <2 x i64> poison, <2 x i32> zeroinitializer
   %a = ashr <2 x i64> %x, %splat
   %b = trunc <2 x i64> %a to <2 x i32>
   ret <2 x i32> %b
 }
 
 define <8 x i8> @vnsra_v8i16_v8i8_imm(<8 x i16> %x) {

 }
 
 define <2 x i32> @vnsrl_v2i64_v2i32_scalar(<2 x i64> %x, i64 %y) {
 ; CHECK-LABEL: vnsrl_v2i64_v2i32_scalar:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, mu
 ; CHECK-NEXT:    vnsrl.wx v8, v8, a0
 ; CHECK-NEXT:    ret
-; RV32-LABEL: vnsrl_v2i64_v2i32_scalar:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetivli zero, 2, e64,m1,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v25, (a0), zero
-; RV32-NEXT:    vsrl.vv v25, v8, v25
-; RV32-NEXT:    vsetivli zero, 2, e32,mf2,ta,mu
-; RV32-NEXT:    vnsrl.wi v8, v25, 0
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-; RV64-LABEL: vnsrl_v2i64_v2i32_scalar:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 2, e32,mf2,ta,mu
-; RV64-NEXT:    vnsrl.wx v25, v8, a0
-; RV64-NEXT:    vmv1r.v v8, v25
-; RV64-NEXT:    ret
   %insert = insertelement <2 x i64> poison, i64 %y, i32 0
   %splat = shufflevector <2 x i64> %insert, <2 x i64> poison, <2 x i32> zeroinitializer
   %a = lshr <2 x i64> %x, %splat
   %b = trunc <2 x i64> %a to <2 x i32>
   ret <2 x i32> %b
 }
 
 define <8 x i8> @vnsrl_v8i16_v8i8_imm(<8 x i16> %x) {