[MIRVRegNamer] Avoid opcode hash collision

[john.brawn]

Summary

D121929 happens to cause CodeGen/MIR/AArch64/mirnamer.mir to fail due to a hash collision caused by adding two extra opcodes. The collision is only in the top 19 bits of the hashed opcode so fix this by just using the whole hash (in fixed width hex for consistency) instead of the top 5 decimal digits.

[plotfi]

LGTM, Nice work John.

Would format_hex_no_prefix be replaceable with std::format once C++20 for LLVM drops?

@aditya_nandakumar Any thoughts? Are you folks still using the pass in places where the change in hashing could break things?

[john.brawn]

In D137155#3899932, @plotfi wrote:

LGTM, Nice work John.

Would format_hex_no_prefix be replaceable with std::format once C++20 for LLVM drops?

Yes, it looks like std::format with format string "{:016x}" should so the same thing as format_hex_no_prefix.

llvm/lib/CodeGen/MIRVRegNamerUtils.cpp

std::string VRegRenamer::getInstructionOpcodeHash(MachineInstr &MI) {
   std::string S;
   raw_string_ostream OS(S);
 
   if (UseStableNamerHash) {
     auto Hash = stableHashValue(MI, /* HashVRegs */ true,
                                 /* HashConstantPoolIndices */ true,
                                 /* HashMemOperands */ true);
     assert(Hash && "Expected non-zero Hash");
-    return std::to_string(Hash).substr(0, 5);
+    OS << format_hex_no_prefix(Hash, 16, true);
+    return OS.str();
   }
 
   // Gets a hashable artifact from a given MachineOperand (ie an unsigned).
   auto GetHashableMO = [this](const MachineOperand &MO) -> unsigned {
     switch (MO.getType()) {
     case MachineOperand::MO_CImmediate:
       return hash_combine(MO.getType(), MO.getTargetFlags(),
                           MO.getCImm()->getZExtValue());
for (const auto *Op : MI.memoperands()) {
     MIOperands.push_back((unsigned)Op->getSuccessOrdering());
     MIOperands.push_back((unsigned)Op->getAddrSpace());
     MIOperands.push_back((unsigned)Op->getSyncScopeID());
     MIOperands.push_back((unsigned)Op->getBaseAlign().value());
     MIOperands.push_back((unsigned)Op->getFailureOrdering());
   }
 
   auto HashMI = hash_combine_range(MIOperands.begin(), MIOperands.end());
-  return std::to_string(HashMI).substr(0, 5);
+  OS << format_hex_no_prefix(HashMI, 16, true);
+  return OS.str();
 }
 
 unsigned VRegRenamer::createVirtualRegister(unsigned VReg) {
   assert(Register::isVirtualRegister(VReg) && "Expected Virtual Registers");
   std::string Name = getInstructionOpcodeHash(*MRI.getVRegDef(VReg));
   return createVirtualRegisterWithLowerName(VReg, Name);
 }
 

llvm/test/CodeGen/MIR/AArch64/mir-canon-constant-pool-hash.mir

 # RUN: llc -o - -run-pass mir-canonicalizer -verify-machineinstrs %s | FileCheck %s
 # RUN: llc -o - -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -verify-machineinstrs %s | FileCheck %s
 --- |
   target triple = "aarch64-unknown-unknown"
   define void @f() { unreachable }
 ...
 ---
 name: f
 constants:
   - id:              0
     value:           '<1 x i8> <i8 0>'
   - id:              1
     value:           '<1 x i8> <i8 1>'
 body: |
   bb.0:
     ; Test that we no longer have hash collisions between two different consts:
-    ;CHECK: %bb{{[0-9]+}}_{{[0-9]+}}__1:gpr64common = ADR
-    ;CHECK: %bb{{[0-9]+}}_{{[0-9]+}}__1:gpr64common = ADR
+    ;CHECK: %bb{{[0-9a-f]+}}_{{[0-9a-f]+}}__1:gpr64common = ADR
+    ;CHECK: %bb{{[0-9a-f]+}}_{{[0-9a-f]+}}__1:gpr64common = ADR
     %vreg0:gpr64common = ADRP target-flags(aarch64-page) %const.0
     %vreg1:gpr64common = ADRP target-flags(aarch64-page) %const.1
 ...

llvm/test/CodeGen/MIR/AArch64/mir-canon-jump-table.mir

entries:
     - id:              3
       blocks:          [ '%bb.2', '%bb.3' ]
 body:             |
   bb.0:
   bb.1:
   bb.2:
   bb.3:
   bb.7:
-    ;CHECK: %bb{{[0-9]+}}_{{[0-9]+}}__1:_(p0) = G_JUMP_TABLE %jump-table.0
-    ;CHECK: %bb{{[0-9]+}}_{{[0-9]+}}__1:_(p0) = G_JUMP_TABLE %jump-table.1
-    ;CHECK: %bb{{[0-9]+}}_{{[0-9]+}}__1:_(p0) = G_JUMP_TABLE %jump-table.2
-    ;CHECK: %bb{{[0-9]+}}_{{[0-9]+}}__1:_(p0) = G_JUMP_TABLE %jump-table.3
+    ;CHECK: %bb{{[0-9a-f]+}}_{{[0-9a-f]+}}__1:_(p0) = G_JUMP_TABLE %jump-table.0
+    ;CHECK: %bb{{[0-9a-f]+}}_{{[0-9a-f]+}}__1:_(p0) = G_JUMP_TABLE %jump-table.1
+    ;CHECK: %bb{{[0-9a-f]+}}_{{[0-9a-f]+}}__1:_(p0) = G_JUMP_TABLE %jump-table.2
+    ;CHECK: %bb{{[0-9a-f]+}}_{{[0-9a-f]+}}__1:_(p0) = G_JUMP_TABLE %jump-table.3
     %a:_(p0) = G_JUMP_TABLE %jump-table.0
     %b:_(p0) = G_JUMP_TABLE %jump-table.1
     %c:_(p0) = G_JUMP_TABLE %jump-table.2
     %d:_(p0) = G_JUMP_TABLE %jump-table.3
 
 ...
 

llvm/test/CodeGen/MIR/AArch64/mirCanonCopyCopyProp.mir

- { id: 6, type: default, offset: 0, size: 8, alignment: 8,
       debug-info-location: '' }
 constants:
 body: |
   bb.0:
     liveins: $x0, $x1, $d0, $d1
 
     %42:gpr32 = LDRWui %stack.0, 0 :: (dereferenceable load (s64))
 
-    ;CHECK: %bb0_{{[0-9]+}}__1:gpr32 = LDRWui %stack.0, 0 :: (dereferenceable load (s64))
+    ;CHECK: %bb0_{{[0-9a-f]+}}__1:gpr32 = LDRWui %stack.0, 0 :: (dereferenceable load (s64))
     ;CHECK-NEXT: $w0 = COPY %bb0_
     ;CHECK-NEXT: RET_ReallyLR implicit $w0
 
     %vreg1234:gpr32 = COPY %42
     %vreg1235:gpr32 = COPY %vreg1234
     %vreg1236:gpr32 = COPY %vreg1235
     $w0 = COPY %vreg1236
     RET_ReallyLR implicit $w0
 
 ...

llvm/test/CodeGen/MIR/AArch64/mirCanonIdempotent.mir

 # RUN: llc -mtriple=arm64-apple-ios11.0.0 -o - -verify-machineinstrs -run-pass mir-canonicalizer %s | FileCheck %s
 # RUN: llc -mtriple=arm64-apple-ios11.0.0 -o - -mir-vreg-namer-use-stable-hash -verify-machineinstrs -run-pass mir-canonicalizer %s | FileCheck %s
 # These Idempotent instructions are sorted alphabetically (based on after the '=')
-# CHECK: %bb0_{{[0-9]+}}__1:gpr64 = MOVi64imm 4617315517961601024
-# CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = MOVi32imm 408
-# CHECK-NEXT: %bb0_{{[0-9]+}}__2:gpr32 = MOVi32imm 408
-# CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr64all = IMPLICIT_DEF
-# CHECK-NEXT: %bb0_{{[0-9]+}}__1:fpr64 = FMOVDi 20
-# CHECK-NEXT: %bb0_{{[0-9]+}}__1:fpr64 = FMOVDi 112
+# CHECK: %bb0_{{[0-9a-f]+}}__1:gpr64 = MOVi64imm 4617315517961601024
+# CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:gpr32 = MOVi32imm 408
+# CHECK-NEXT: %bb0_{{[0-9a-f]+}}__2:gpr32 = MOVi32imm 408
+# CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:gpr64all = IMPLICIT_DEF
+# CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:fpr64 = FMOVDi 20
+# CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:fpr64 = FMOVDi 112
 
 ...
 ---
 name: Proc8
 stack:
   - { id: 0, type: default, offset: 0, size: 4, alignment: 4,
       stack-id: default, callee-saved-register: '', callee-saved-restored: true,
       local-offset: -4, debug-info-variable: '', debug-info-expression: '',

llvm/test/CodeGen/MIR/AArch64/mirnamer.mir

 # RUN: llc -x mir -mtriple aarch64-apple-ios -run-pass mir-namer -mir-vreg-namer-use-stable-hash -verify-machineinstrs -o - < %s | FileCheck %s
 
 ---
 name: foo
 body:             |
   bb.0:
 
     ;CHECK-LABEL: bb.0
     ;CHECK-NEXT: liveins
     ;CHECK-NEXT: {{  $}}
-    ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:_(p0) = COPY $d0
-    ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:_(<4 x s32>) = COPY $q0
-    ;CHECK-NEXT: G_STORE %bb0_{{[0-9]+}}__1(<4 x s32>), %bb0_{{[0-9]+}}__1(p0) :: (store (<4 x s32>))
+    ;CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:_(p0) = COPY $d0
+    ;CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:_(<4 x s32>) = COPY $q0
+    ;CHECK-NEXT: G_STORE %bb0_{{[0-9a-f]+}}__1(<4 x s32>), %bb0_{{[0-9a-f]+}}__1(p0) :: (store (<4 x s32>))
 
     liveins: $q0, $d0
     %1:fpr(p0) = COPY $d0
     %0:fpr(<4 x s32>) = COPY $q0
     G_STORE %0(<4 x s32>), %1(p0) :: (store (<4 x s32>))
 ...
 ---
 name: bar
 stack:
   - { id: 0, type: default, offset: 0, size: 4, alignment: 4,
       stack-id: default, callee-saved-register: '', callee-saved-restored: true,
       local-offset: -4, debug-info-variable: '', debug-info-expression: '',
       debug-info-location: '' }
 body:             |
   bb.0:
 
     ;CHECK-LABEL: bb.0
-    ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = LDRWui
-    ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = MOVi32imm 1
-    ;CHECK-NEXT: %bb0_{{[0-9]+}}__2:gpr32 = LDRWui
-    ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = MOVi32imm 2
-    ;CHECK-NEXT: %bb0_{{[0-9]+}}__3:gpr32 = LDRWui
-    ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = MOVi32imm 3
-    ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = nsw ADDWrr
-    ;CHECK-NEXT: %bb0_{{[0-9]+}}__4:gpr32 = LDRWui
-    ;CHECK-NEXT: %bb0_{{[0-9]+}}__2:gpr32 = nsw ADDWrr
-    ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = MOVi32imm 4
-    ;CHECK-NEXT: %bb0_{{[0-9]+}}__3:gpr32 = nsw ADDWrr
-    ;CHECK-NEXT: %bb0_{{[0-9]+}}__5:gpr32 = LDRWui
-    ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = MOVi32imm 5
+    ;CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:gpr32 = LDRWui
+    ;CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:gpr32 = MOVi32imm 1
+    ;CHECK-NEXT: %bb0_{{[0-9a-f]+}}__2:gpr32 = LDRWui
+    ;CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:gpr32 = MOVi32imm 2
+    ;CHECK-NEXT: %bb0_{{[0-9a-f]+}}__3:gpr32 = LDRWui
+    ;CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:gpr32 = MOVi32imm 3
+    ;CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:gpr32 = nsw ADDWrr
+    ;CHECK-NEXT: %bb0_{{[0-9a-f]+}}__4:gpr32 = LDRWui
+    ;CHECK-NEXT: %bb0_{{[0-9a-f]+}}__2:gpr32 = nsw ADDWrr
+    ;CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:gpr32 = MOVi32imm 4
+    ;CHECK-NEXT: %bb0_{{[0-9a-f]+}}__3:gpr32 = nsw ADDWrr
+    ;CHECK-NEXT: %bb0_{{[0-9a-f]+}}__5:gpr32 = LDRWui
+    ;CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:gpr32 = MOVi32imm 5
 
     %0:gpr32 = LDRWui %stack.0, 0 :: (dereferenceable load (s64))
     %1:gpr32 = MOVi32imm 1
     %2:gpr32 = LDRWui %stack.0, 0 :: (dereferenceable load (s64))
     %3:gpr32 = MOVi32imm 2
     %4:gpr32 = LDRWui %stack.0, 0 :: (dereferenceable load (s64))
     %5:gpr32 = MOVi32imm 3
     %10:gpr32 = nsw ADDWrr %0:gpr32, %1:gpr32
- { id: 0, type: default, offset: 0, size: 4, alignment: 4,
       debug-info-location: '' }
 body:             |
   bb.0:
     liveins: $x0, $x1, $d0, $d1
 
     ;CHECK-LABEL: bb.0:
     ;CHECK-NEXT: liveins
     ;CHECK-NEXT: {{  $}}
-    ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = LDRWui %stack.0, 0
-    ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = COPY %bb0_{{[0-9]+}}__1
-    ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = COPY %bb0_{{[0-9]+}}__1
-    ;CHECK-NEXT: %bb0_{{[0-9]+}}__2:gpr32 = COPY %bb0_{{[0-9]+}}__1
-    ;CHECK-NEXT: $w0 = COPY %bb0_{{[0-9]+}}__2
+    ;CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:gpr32 = LDRWui %stack.0, 0
+    ;CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:gpr32 = COPY %bb0_{{[0-9a-f]+}}__1
+    ;CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:gpr32 = COPY %bb0_{{[0-9a-f]+}}__1
+    ;CHECK-NEXT: %bb0_{{[0-9a-f]+}}__2:gpr32 = COPY %bb0_{{[0-9a-f]+}}__1
+    ;CHECK-NEXT: $w0 = COPY %bb0_{{[0-9a-f]+}}__2
 
     %0:gpr32 = LDRWui %stack.0, 0 :: (dereferenceable load (s64))
     %1:gpr32 = COPY %0
     %2:gpr32 = COPY %1
     %3:gpr32 = COPY %2
     $w0 = COPY %3
     RET_ReallyLR implicit $w0
 ...
 

llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir

 # RUN: llc -o -  -march=amdgcn  -run-pass mir-canonicalizer -verify-machineinstrs %s | FileCheck %s
 # RUN: llc -o -  -march=amdgcn  -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -verify-machineinstrs %s | FileCheck %s
 
 # This tests for the itereator invalidation fix (reviews.llvm.org/D62713)
 ...
 ---
 name: foo
 body:             |
   bb.0:
     ; CHECK-LABEL: name: foo
-    ; CHECK: %bb0_{{[0-9]+}}__1:sreg_32_xm0 = S_MOV_B32 61440
-    ; CHECK: %bb0_{{[0-9]+}}__1:sreg_32_xm0 = S_MOV_B32 0
-    ; CHECK: %bb0_{{[0-9]+}}__1:vgpr_32 = COPY $vgpr0
-    ; CHECK: %bb0_{{[0-9]+}}__1:sgpr_64 = COPY $sgpr0_sgpr1
-    ; CHECK: %bb0_{{[0-9]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %bb0_{{[0-9]+}}__1, 9, 0
-    ; CHECK: %bb0_{{[0-9]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %bb0_{{[0-9]+}}__1, 11, 0
-    ; CHECK: %bb0_{{[0-9]+}}__1:vgpr_32 = COPY %bb0_{{[0-9]+}}__1
-    ; CHECK: %bb0_{{[0-9]+}}__1:vgpr_32 = COPY %bb0_{{[0-9]+}}__1
-    ; CHECK: %bb0_{{[0-9]+}}__2:vgpr_32 = COPY %bb0_{{[0-9]+}}__1
-    ; CHECK: %bb0_{{[0-9]+}}__1:vreg_64 = REG_SEQUENCE %bb0_{{[0-9]+}}__1, %subreg.sub0, %bb0_{{[0-9]+}}__1, %subreg.sub1
-    ; CHECK: %bb0_{{[0-9]+}}__1:sgpr_128 = REG_SEQUENCE %bb0_{{[0-9]+}}__1, %subreg.sub0, %bb0_{{[0-9]+}}__1, %subreg.sub1, %bb0_{{[0-9]+}}__1, %subreg.sub2, %bb0_{{[0-9]+}}__2, %subreg.sub3
-    ; CHECK: BUFFER_STORE_DWORD_ADDR64 %bb0_{{[0-9]+}}__1, %bb0_{{[0-9]+}}__1, %bb0_{{[0-9]+}}__1, 0, 0, 0, 0, 0, implicit $exec
+    ; CHECK: %bb0_{{[0-9a-f]+}}__1:sreg_32_xm0 = S_MOV_B32 61440
+    ; CHECK: %bb0_{{[0-9a-f]+}}__1:sreg_32_xm0 = S_MOV_B32 0
+    ; CHECK: %bb0_{{[0-9a-f]+}}__1:vgpr_32 = COPY $vgpr0
+    ; CHECK: %bb0_{{[0-9a-f]+}}__1:sgpr_64 = COPY $sgpr0_sgpr1
+    ; CHECK: %bb0_{{[0-9a-f]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %bb0_{{[0-9a-f]+}}__1, 9, 0
+    ; CHECK: %bb0_{{[0-9a-f]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %bb0_{{[0-9a-f]+}}__1, 11, 0
+    ; CHECK: %bb0_{{[0-9a-f]+}}__1:vgpr_32 = COPY %bb0_{{[0-9a-f]+}}__1
+    ; CHECK: %bb0_{{[0-9a-f]+}}__1:vgpr_32 = COPY %bb0_{{[0-9a-f]+}}__1
+    ; CHECK: %bb0_{{[0-9a-f]+}}__2:vgpr_32 = COPY %bb0_{{[0-9a-f]+}}__1
+    ; CHECK: %bb0_{{[0-9a-f]+}}__1:vreg_64 = REG_SEQUENCE %bb0_{{[0-9a-f]+}}__1, %subreg.sub0, %bb0_{{[0-9a-f]+}}__1, %subreg.sub1
+    ; CHECK: %bb0_{{[0-9a-f]+}}__1:sgpr_128 = REG_SEQUENCE %bb0_{{[0-9a-f]+}}__1, %subreg.sub0, %bb0_{{[0-9a-f]+}}__1, %subreg.sub1, %bb0_{{[0-9a-f]+}}__1, %subreg.sub2, %bb0_{{[0-9a-f]+}}__2, %subreg.sub3
+    ; CHECK: BUFFER_STORE_DWORD_ADDR64 %bb0_{{[0-9a-f]+}}__1, %bb0_{{[0-9a-f]+}}__1, %bb0_{{[0-9a-f]+}}__1, 0, 0, 0, 0, 0, implicit $exec
     ; CHECK: S_ENDPGM 0
     %10:sreg_32_xm0 = S_MOV_B32 61440
     %11:sreg_32_xm0 = S_MOV_B32 0
     %3:vgpr_32 = COPY $vgpr0
 
     %vreg123_0:vgpr_32 = COPY %3
     %0:sgpr_64 = COPY $sgpr0_sgpr1
     %vreg123_1:vgpr_32 = COPY %11

llvm/test/CodeGen/MIR/AMDGPU/mircanon-memoperands.mir

registers:
   - { id: 6, class: sreg_64_xexec }
 liveins:
   - { reg: '$sgpr4_sgpr5', virtual-reg: '%4' }
 body:             |
   bb.0:
     liveins: $sgpr4_sgpr5
 
     ; CHECK: COPY
-    ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM
-    ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM
-    ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM
-    ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM
-    ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM
-    ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM
+    ; CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM
+    ; CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM
+    ; CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM
+    ; CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM
+    ; CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM
+    ; CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM
 
     %0 = COPY $sgpr4_sgpr5
     %1 = S_LOAD_DWORDX2_IMM %0, 0, 0 :: (non-temporal dereferenceable invariant load (s64) from `i64 addrspace(4)* undef`)
     %2 = S_LOAD_DWORDX2_IMM %0, 0, 0 :: (             dereferenceable invariant load (s64) from `i64 addrspace(4)* undef`)
     %3 = S_LOAD_DWORDX2_IMM %0, 0, 0 :: (                             invariant load (s64) from `i64 addrspace(4)* undef`)
     %4 = S_LOAD_DWORDX2_IMM %0, 0, 0 :: (                                       load (s64) from `i64 addrspace(4)* undef`)
     %5 = S_LOAD_DWORDX2_IMM %0, 0, 0 :: (                                       load (s64) from `i64 addrspace(2)* undef`)
     %6 = S_LOAD_DWORDX2_IMM %0, 0, 0 :: (                                       load (s64) from `i64 addrspace(1)* undef`)
 
 ...

llvm/test/CodeGen/MIR/X86/mir-canon-hash-bb.mir

bb.0:
     %tmp6:_(p0) = G_FRAME_INDEX %stack.1.tmp1
     G_STORE %tmp0(s32), %tmp5(p0) :: (store (s32) into %ir.tmp)
     %tmp7:_(s32) = G_LOAD %tmp5(p0) :: (load (s32) from %ir.tmp)
     %tmp8:_(s1) = G_ICMP intpred(ne), %tmp7(s32), %tmp1
     G_BRCOND %tmp8(s1), %bb.1
     G_BR %bb.2
 
   ; CHECK: bb.1:
-  ; CHECK: %bb2_{{[0-9]+}}__1:_(s32) = G_CONSTANT
+  ; CHECK: %bb2_{{[0-9a-f]+}}__1:_(s32) = G_CONSTANT
   bb.1:
     %tmp4:_(s32) = G_CONSTANT i32 1
     G_STORE %tmp4(s32), %tmp6(p0) :: (store (s32) into %ir.tmp1)
     G_BR %bb.3
 
 
   ; CHECK: bb.2:
-  ; CHECK: %bb1_{{[0-9]+}}__1:_(s32) = G_CONSTANT
+  ; CHECK: %bb1_{{[0-9a-f]+}}__1:_(s32) = G_CONSTANT
   bb.2:
     %tmp3:_(s32) = G_CONSTANT i32 2
     G_STORE %tmp3(s32), %tmp6(p0) :: (store (s32) into %ir.tmp1)
 
   ; CHECK: bb.3:
-  ; CHECK: %bb3_{{[0-9]+}}__1:_(s32) =  G_LOAD
+  ; CHECK: %bb3_{{[0-9a-f]+}}__1:_(s32) =  G_LOAD
   bb.3:
     %tmp9:_(s32) = G_LOAD %tmp6(p0) :: (load (s32) from %ir.tmp1)
     $eax = COPY %tmp9(s32)
     RET 0, implicit $eax
 
 ...

llvm/test/CodeGen/MIR/X86/mircanon-flags.mir

 # RUN: llc -march=x86-64 -run-pass mir-canonicalizer -verify-machineinstrs -o - %s | FileCheck %s
 # RUN: llc -march=x86-64 -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -verify-machineinstrs -o - %s | FileCheck %s
 # The purpose of this test is to ensure that differing flags do in-fact cause
 # naming collisions with the new vreg renamers naming scheme.
 --- |
   target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
   define void @baz() { unreachable }
 ...
 ---
 name:            baz
 body:             |
   bb.0:
 
     ; CHECK: COPY
-    ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = nnan VMULSSrr
-    ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = ninf VMULSSrr
-    ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = nsz VMULSSrr
-    ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = arcp VMULSSrr
-    ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = contract VMULSSrr
-    ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = afn VMULSSrr
-    ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = reassoc VMULSSrr
-    ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = nsz arcp contract afn reassoc VMULSSrr
-    ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = contract afn reassoc VMULSSrr
+    ; CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:fr32 = nnan VMULSSrr
+    ; CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:fr32 = ninf VMULSSrr
+    ; CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:fr32 = nsz VMULSSrr
+    ; CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:fr32 = arcp VMULSSrr
+    ; CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:fr32 = contract VMULSSrr
+    ; CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:fr32 = afn VMULSSrr
+    ; CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:fr32 = reassoc VMULSSrr
+    ; CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:fr32 = nsz arcp contract afn reassoc VMULSSrr
+    ; CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:fr32 = contract afn reassoc VMULSSrr
 
     %0:fr32 = COPY $xmm0
     %1:fr32 = nnan VMULSSrr %0, %0, implicit $mxcsr
     %2:fr32 = ninf VMULSSrr %1, %1, implicit $mxcsr
     %3:fr32 = nsz VMULSSrr %2, %2, implicit $mxcsr
     %4:fr32 = arcp VMULSSrr %3, %3, implicit $mxcsr
     %5:fr32 = contract VMULSSrr %4, %4, implicit $mxcsr
     %6:fr32 = afn VMULSSrr %5, %5, implicit $mxcsr
     %7:fr32 = reassoc VMULSSrr %6, %6, implicit $mxcsr
     %8:fr32 = nsz arcp contract afn reassoc VMULSSrr %7, %7, implicit $mxcsr
     %9:fr32 = contract afn reassoc VMULSSrr %8, %8, implicit $mxcsr
     $xmm0 = COPY %9
     RET 0, $xmm0
 
 ...