[AVR] Reject/Reserve R0~R15 on AVRTiny

[benshi001]

This patch partially fixes https://github.com/llvm/llvm-project/issues/53459 .

[benshi001]

This comment was removed by benshi001.

[benshi001]

This patch partially fixes https://github.com/llvm/llvm-project/issues/53459 .

[benshi001]

The build failure is about libFuzzer.libFuzzer::large.test , not caused by my patch.

[aykevl]

llvm/lib/Target/AVR/AVRCallingConv.td

39

I don't think this is needed. Reserved registers are not part of the regular calling convention anyway.

llvm/lib/Target/AVR/AVRISelLowering.cpp

1059–1062

I think it would make sense to use a vector here, to make the code safer. Take a look here to see the recommended vector types for use in LLVM: https://llvm.org/docs/ProgrammersManual.html#sequential-containers-std-vector-std-list-etc

llvm/lib/Target/AVR/AVRRegisterInfo.cpp

60–62

I think it would make sense to change these hardcoded R0/R1/R1R0 registers to properties of AVRSubtarget (a bit like getIORegisterOffset for example). This would make the code below a bit more sensible: it could just reserve R0-R15 instead of R2-R17 which looks a bit strange.
Such a change should probably need to be done in a separate patch, as a cleanup before this patch. Such a patch could also fix the hardcoded R0/R1 registers in AVRFrameLowering.cpp, AVRExpandPseudoInsts.cpp, etc.

[aykevl]

llvm/lib/Target/AVR/AVRRegisterInfo.cpp

60–62

It looks like you already added these getters to AVRSubtarget in D119807.

[benshi001]

llvm/lib/Target/AVR/AVRRegisterInfo.cpp

60–62

Thanks for your suggestion.

But I do not think reserve R0-R15 looks good. Since R0&R1 are always reserved on both avr and avrtiny. While R2-R15 are only reserved on avrtiny. It looks strange like

if (STI.hasTinyEncoding()) {
    for (unsigned Reg = AVR::R0; Reg <= AVR::R17; Reg++)
      Reserved.set(Reg);
else {
      Reserved.set(R0);
      Reserved.set(R1);
}

My points are

1. R0 and R1 are always reserved, no matter avr or avrtiny.
2. R2-R17 are reserved only on avrtiny, while are available on avr.

[benshi001]

llvm/lib/Target/AVR/AVRRegisterInfo.cpp

60–62

One more issue of doing

Reserved.set(getTempReg());
Reserved.set(getZeroReg());

is that, we also have to reserve 16-bit registers R0R1/R16R15/R17R16/R18/R17 on avrtiny. It makes sence to define getTempReg() and getZeroRegs(), but not for something like getTinyReservedRegs().

[benshi001]

llvm/lib/Target/AVR/AVRCallingConv.td

39

Unfortunately this is a must. Since R19 and R18 are callee saved registers on avrtiny, according to https://gcc.gnu.org/wiki/avr-gcc#Reduced_Tiny, though they are not so on normal avr.

So we should explicitly mark R19/R18 as callee saved for avrtiny, and exclude R17/R16 from interrupt/singal_handler saved list.

[aykevl]

llvm/lib/Target/AVR/AVRCallingConv.td

39

Ah, I see. You are correct.

[aykevl]

llvm/lib/Target/AVR/AVRISelLowering.cpp

1149–1150

While updating D131867 I found there is a bug in this code: RegList16 has 6 elements while RegIdx below can be up to 7. This results in an array out of bounds error.
I believe the issue here is that return values greater than 4 bytes should be returned via the stack on avrtiny, see: https://godbolt.org/z/GzxGezE81

[benshi001]

llvm/lib/Target/AVR/AVRISelLowering.cpp

1149–1150

Thanks for your information. I have made a patch to fix that.

https://reviews.llvm.org/D138125

Beside changes in the clang side, some extra work is need on the backend, and I will do that later this week.

[benshi001]

llvm/lib/Target/AVR/AVRISelLowering.cpp

1149–1150

The corresponding fix in the backend is here, https://reviews.llvm.org/D138201

llvm/lib/Target/AVR/AVRCallingConv.td

def ArgCC_AVR_Vararg : CallingConv<[
   CCAssignToStack<2, 1>
 ]>;
 
 //===----------------------------------------------------------------------===//
 // Callee-saved register lists.
 //===----------------------------------------------------------------------===//
 
 def CSR_Normal : CalleeSavedRegs<(add R29, R28, (sequence "R%u", 17, 2))>;
+def CSR_NormalTiny : CalleeSavedRegs<(add R29, R28, R19, R18)>;
 def CSR_Interrupts : CalleeSavedRegs<(add(sequence "R%u", 31, 2))>;
+def CSR_InterruptsTiny : CalleeSavedRegs<(add(sequence "R%u", 31, 18))>;

llvm/lib/Target/AVR/AVRISelLowering.cpp

 //===----------------------------------------------------------------------===//
 //             Formal Arguments Calling Convention Implementation
 //===----------------------------------------------------------------------===//
 
 #include "AVRGenCallingConv.inc"
 
 /// Registers for calling conventions, ordered in reverse as required by ABI.
 /// Both arrays must be of the same length.
-static const MCPhysReg RegList8[] = {
+static const MCPhysReg RegList8AVR[] = {
     AVR::R25, AVR::R24, AVR::R23, AVR::R22, AVR::R21, AVR::R20,
     AVR::R19, AVR::R18, AVR::R17, AVR::R16, AVR::R15, AVR::R14,
     AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9,  AVR::R8};
-static const MCPhysReg RegList16[] = {
+static const MCPhysReg RegList8Tiny[] = {
+    AVR::R25, AVR::R24, AVR::R23, AVR::R22, AVR::R21, AVR::R20};
+static const MCPhysReg RegList16AVR[] = {
     AVR::R26R25, AVR::R25R24, AVR::R24R23, AVR::R23R22, AVR::R22R21,
     AVR::R21R20, AVR::R20R19, AVR::R19R18, AVR::R18R17, AVR::R17R16,
     AVR::R16R15, AVR::R15R14, AVR::R14R13, AVR::R13R12, AVR::R12R11,
     AVR::R11R10, AVR::R10R9,  AVR::R9R8};
+static const MCPhysReg RegList16Tiny[] = {
+    AVR::R26R25, AVR::R25R24, AVR::R24R23, AVR::R23R22, AVR::R22R21,
+    AVR::R21R20};
 
-static_assert(array_lengthof(RegList8) == array_lengthof(RegList16),
+static_assert(array_lengthof(RegList8AVR) == array_lengthof(RegList16AVR),
+              "8-bit and 16-bit register arrays must be of equal length");
+static_assert(array_lengthof(RegList8Tiny) == array_lengthof(RegList16Tiny),
               "8-bit and 16-bit register arrays must be of equal length");
 
 /// Analyze incoming and outgoing function arguments. We need custom C++ code
 /// to handle special constraints in the ABI.
 /// In addition, all pieces of a certain argument have to be passed either
 /// using registers or the stack but never mixing both.
 template <typename ArgT>
 static void
 analyzeArguments(TargetLowering::CallLoweringInfo *CLI, const Function *F,
                  const DataLayout *TD, const SmallVectorImpl<ArgT> &Args,
-                 SmallVectorImpl<CCValAssign> &ArgLocs, CCState &CCInfo) {
+                 SmallVectorImpl<CCValAssign> &ArgLocs, CCState &CCInfo,
+                 bool Tiny) {
+  const MCPhysReg *RegList8 = Tiny ? RegList8Tiny : RegList8AVR;
+  const MCPhysReg *RegList16 = Tiny ? RegList16Tiny : RegList16AVR;
+  const unsigned RegAmount =
+      Tiny ? array_lengthof(RegList8Tiny) : array_lengthof(RegList8AVR);
   unsigned NumArgs = Args.size();
   // This is the index of the last used register, in RegList*.
   // -1 means R26 (R26 is never actually used in CC).
   int RegLastIdx = -1;
   // Once a value is passed to the stack it will always be used
   bool UseStack = false;
   for (unsigned i = 0; i != NumArgs;) {
     MVT VT = Args[i].VT;
     // We have to count the number of bytes for each function argument, that is
     // those Args with the same OrigArgIndex. This is important in case the
     // function takes an aggregate type.
for (unsigned i = 0; i != NumArgs;) {
     TotalBytes = alignTo(TotalBytes, 2);
     // Skip zero sized arguments
     if (TotalBytes == 0)
       continue;
     // The index of the first register to be used
     unsigned RegIdx = RegLastIdx + TotalBytes;
     RegLastIdx = RegIdx;
     // If there are not enough registers, use the stack
-    if (RegIdx >= array_lengthof(RegList8)) {
+    if (RegIdx >= RegAmount) {
       UseStack = true;
     }
     for (; i != j; ++i) {
       MVT VT = Args[i].VT;
 
       if (UseStack) {
         auto evt = EVT(VT).getTypeForEVT(CCInfo.getContext());
         unsigned Offset = CCInfo.AllocateStack(TD->getTypeAllocSize(evt),
getTotalArgumentsSizeInBytes(const SmallVectorImpl<ArgT> &Args) {
   return TotalBytes;
 }
 
 /// Analyze incoming and outgoing value of returning from a function.
 /// The algorithm is similar to analyzeArguments, but there can only be
 /// one value, possibly an aggregate, and it is limited to 8 bytes.
 template <typename ArgT>
 static void analyzeReturnValues(const SmallVectorImpl<ArgT> &Args,
-                                CCState &CCInfo) {
+                                CCState &CCInfo, bool Tiny) {
   unsigned NumArgs = Args.size();
   unsigned TotalBytes = getTotalArgumentsSizeInBytes(Args);
   // CanLowerReturn() guarantees this assertion.
   assert(TotalBytes <= 8 &&
          "return values greater than 8 bytes cannot be lowered");
 
+  const MCPhysReg *RegList8 = Tiny ? RegList8Tiny : RegList8AVR;
+  const MCPhysReg *RegList16 = Tiny ? RegList16Tiny : RegList16AVR;
+
   // GCC-ABI says that the size is rounded up to the next even number,
   // but actually once it is more than 4 it will always round up to 8.
   if (TotalBytes > 4) {
     TotalBytes = 8;
   } else {
     TotalBytes = alignTo(TotalBytes, 2);
   }
 
   // The index of the first register to use.
   int RegIdx = TotalBytes - 1;
   for (unsigned i = 0; i != NumArgs; ++i) {
SDValue AVRTargetLowering::LowerFormalArguments(
   SmallVector<CCValAssign, 16> ArgLocs;
   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
                  *DAG.getContext());
 
   // Variadic functions do not need all the analysis below.
   if (isVarArg) {
     CCInfo.AnalyzeFormalArguments(Ins, ArgCC_AVR_Vararg);
   } else {
-    analyzeArguments(nullptr, &MF.getFunction(), &DL, Ins, ArgLocs, CCInfo);
+    analyzeArguments(nullptr, &MF.getFunction(), &DL, Ins, ArgLocs, CCInfo,
+                     Subtarget.hasTinyEncoding());
   }
 
   SDValue ArgValue;
   for (CCValAssign &VA : ArgLocs) {
 
     // Arguments stored on registers.
     if (VA.isRegLoc()) {
       EVT RegVT = VA.getLocVT();
if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
     Callee = DAG.getTargetExternalSymbol(ES->getSymbol(),
                                          getPointerTy(DAG.getDataLayout()));
   }
 
   // Variadic functions do not need all the analysis below.
   if (isVarArg) {
     CCInfo.AnalyzeCallOperands(Outs, ArgCC_AVR_Vararg);
   } else {
-    analyzeArguments(&CLI, F, &DAG.getDataLayout(), Outs, ArgLocs, CCInfo);
+    analyzeArguments(&CLI, F, &DAG.getDataLayout(), Outs, ArgLocs, CCInfo,
+                     Subtarget.hasTinyEncoding());
   }
 
   // Get a count of how many bytes are to be pushed on the stack.
   unsigned NumBytes = CCInfo.getNextStackOffset();
 
   Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
 
   SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
SDValue AVRTargetLowering::LowerCallResult(
   SmallVector<CCValAssign, 16> RVLocs;
   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
                  *DAG.getContext());
 
   // Handle runtime calling convs.
   if (CallConv == CallingConv::AVR_BUILTIN) {
     CCInfo.AnalyzeCallResult(Ins, RetCC_AVR_BUILTIN);
   } else {
-    analyzeReturnValues(Ins, CCInfo);
+    analyzeReturnValues(Ins, CCInfo, Subtarget.hasTinyEncoding());
   }
 
   // Copy all of the result registers out of their specified physreg.
   for (CCValAssign const &RVLoc : RVLocs) {
     Chain = DAG.getCopyFromReg(Chain, dl, RVLoc.getLocReg(), RVLoc.getValVT(),
                                InFlag)
                 .getValue(1);
     InFlag = Chain.getValue(2);
CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
                  *DAG.getContext());
 
   MachineFunction &MF = DAG.getMachineFunction();
 
   // Analyze return values.
   if (CallConv == CallingConv::AVR_BUILTIN) {
     CCInfo.AnalyzeReturn(Outs, RetCC_AVR_BUILTIN);
   } else {
-    analyzeReturnValues(Outs, CCInfo);
+    analyzeReturnValues(Outs, CCInfo, Subtarget.hasTinyEncoding());
   }
 
   SDValue Flag;
   SmallVector<SDValue, 4> RetOps(1, Chain);
   // Copy the result values into the output registers.
   for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
     CCValAssign &VA = RVLocs[i];
     assert(VA.isRegLoc() && "Can only return in registers!");

llvm/lib/Target/AVR/AVRRegisterInfo.cpp

 
 namespace llvm {
 
 AVRRegisterInfo::AVRRegisterInfo() : AVRGenRegisterInfo(0) {}
 
 const uint16_t *
 AVRRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
   const AVRMachineFunctionInfo *AFI = MF->getInfo<AVRMachineFunctionInfo>();
-
+  const AVRSubtarget &STI = MF->getSubtarget<AVRSubtarget>();
+  if (STI.hasTinyEncoding())
+    return AFI->isInterruptOrSignalHandler() ? CSR_InterruptsTiny_SaveList
+                                             : CSR_NormalTiny_SaveList;
+  else
     return AFI->isInterruptOrSignalHandler() ? CSR_Interrupts_SaveList
                                              : CSR_Normal_SaveList;
 }
 
 const uint32_t *
 AVRRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
                                       CallingConv::ID CC) const {
-  return CSR_Normal_RegMask;
+  const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
+  return STI.hasTinyEncoding() ? CSR_NormalTiny_RegMask : CSR_Normal_RegMask;
 }
 
 BitVector AVRRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   BitVector Reserved(getNumRegs());
 
   // Reserve the intermediate result registers r1 and r2
   // The result of instructions like 'mul' is always stored here.
   Reserved.set(AVR::R0);
   Reserved.set(AVR::R1);
   Reserved.set(AVR::R1R0);
 
-  //  Reserve the stack pointer.
+  // Reserve the stack pointer.
   Reserved.set(AVR::SPL);
   Reserved.set(AVR::SPH);
   Reserved.set(AVR::SP);
 
+  // Reserve R2~R17 on avrtiny.
+  const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
+  if (STI.hasTinyEncoding()) {
+    // Reserve 8-bit registers R2~R15, Rtmp(R16) and Zero(R17).
+    for (unsigned Reg = AVR::R2; Reg <= AVR::R17; Reg++)
+      Reserved.set(Reg);
+    // Reserve 16-bit registers R3R2~R18R17.
+    for (unsigned Reg = AVR::R3R2; Reg <= AVR::R18R17; Reg++)
+      Reserved.set(Reg);
+  }
+
   // We tenatively reserve the frame pointer register r29:r28 because the
   // function may require one, but we cannot tell until register allocation
   // is complete, which can be too late.
   //
   // Instead we just unconditionally reserve the Y register.
   //
   // TODO: Write a pass to enumerate functions which reserved the Y register
   //       but didn't end up needing a frame pointer. In these, we can

llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp

 namespace {
 /// Parses AVR assembly from a stream.
 class AVRAsmParser : public MCTargetAsmParser {
   const MCSubtargetInfo &STI;
   MCAsmParser &Parser;
   const MCRegisterInfo *MRI;
   const std::string GENERATE_STUBS = "gs";
 
+  enum AVRMatchResultTy {
+    Match_InvalidRegisterOnTiny = FIRST_TARGET_MATCH_RESULT_TY + 1,
+  };
+
 #define GET_ASSEMBLER_HEADER
 #include "AVRGenAsmMatcher.inc"
 
   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                                OperandVector &Operands, MCStreamer &Out,
                                uint64_t &ErrorInfo,
                                bool MatchingInlineAsm) override;
 
bool AVRAsmParser::MatchAndEmitInstruction(SMLoc Loc, unsigned &Opcode,
   case Match_Success:
     return emit(Inst, Loc, Out);
   case Match_MissingFeature:
     return missingFeature(Loc, ErrorInfo);
   case Match_InvalidOperand:
     return invalidOperand(Loc, Operands, ErrorInfo);
   case Match_MnemonicFail:
     return Error(Loc, "invalid instruction");
+  case Match_InvalidRegisterOnTiny:
+    return Error(Loc, "invalid register on avrtiny");
   default:
     return true;
   }
 }
 
 /// Parses a register name using a given matching function.
 /// Checks for lowercase or uppercase if necessary.
 int AVRAsmParser::parseRegisterName(unsigned (*matchFn)(StringRef)) {

 }
 
 bool AVRAsmParser::tryParseRegisterOperand(OperandVector &Operands) {
   int RegNo = parseRegister();
 
   if (RegNo == AVR::NoRegister)
     return true;
 
+  // Reject R0~R15 on avrtiny.
+  if (AVR::R0 <= RegNo && RegNo <= AVR::R15 &&
+      STI.hasFeature(AVR::FeatureTinyEncoding))
+    return Error(Parser.getTok().getLoc(), "invalid register on avrtiny");
+
   AsmToken const &T = Parser.getTok();
   Operands.push_back(AVROperand::CreateReg(RegNo, T.getLoc(), T.getEndLoc()));
   Parser.Lex(); // Eat register token.
 
   return false;
 }
 
 bool AVRAsmParser::tryParseExpression(OperandVector &Operands) {
unsigned AVRAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
   AVROperand &Op = static_cast<AVROperand &>(AsmOp);
   MatchClassKind Expected = static_cast<MatchClassKind>(ExpectedKind);
 
   // If need be, GCC converts bare numbers to register names
   // It's ugly, but GCC supports it.
   if (Op.isImm()) {
     if (MCConstantExpr const *Const = dyn_cast<MCConstantExpr>(Op.getImm())) {
       int64_t RegNum = Const->getValue();
+
+      // Reject R0~R15 on avrtiny.
+      if (0 <= RegNum && RegNum <= 15 &&
+          STI.hasFeature(AVR::FeatureTinyEncoding))
+        return Match_InvalidRegisterOnTiny;
+
       std::ostringstream RegName;
       RegName << "r" << RegNum;
       RegNum = MatchRegisterName(RegName.str());
       if (RegNum != AVR::NoRegister) {
         Op.makeReg(RegNum);
         if (validateOperandClass(Op, Expected) == Match_Success) {
           return Match_Success;
         }

llvm/test/CodeGen/AVR/calling-conv/c/tiny.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=avr -mcpu=avrtiny | FileCheck %s
+
+; NOTE: Both %a(i8) and %b(i8) cost two registers.
+define i8 @foo0(i8 %a, i8 %b) {
+; CHECK-LABEL: foo0:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    sub r24, r22
+; CHECK-NEXT:    ret
+  %c = sub i8 %a, %b
+  ret i8 %c
+}
+
+; NOTE: Both %a(i16) and %b(i16) cost two registers.
+define i16 @foo1(i16 %a, i16 %b) {
+; CHECK-LABEL: foo1:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    sub r24, r22
+; CHECK-NEXT:    sbc r25, r23
+; CHECK-NEXT:    ret
+  %c = sub i16 %a, %b
+  ret i16 %c
+}
+
+; NOTE: %a(i16), %b(i16) and %c(i16) each costs two registers.
+define i16 @foo2(i16 %a, i16 %b, i16 %c) {
+; CHECK-LABEL: foo2:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    sub r22, r24
+; CHECK-NEXT:    sbc r23, r25
+; CHECK-NEXT:    add r22, r20
+; CHECK-NEXT:    adc r23, r21
+; CHECK-NEXT:    mov r24, r22
+; CHECK-NEXT:    mov r25, r23
+; CHECK-NEXT:    ret
+  %d = sub i16 %a, %b
+  %e = sub i16 %c, %d
+  ret i16 %e
+}
+
+; NOTE:  %a(i16), %b(i16) and %c(i16) each costs two registers,
+;        while %d(i16) is passed via the stack.
+; FIXME: The `ldd` instruction is invalid on avrtiny, this test just shows
+;        how arguments are passed.
+define i16 @foo3(i16 %a, i16 %b, i16 %c, i16 %d) {
+; CHECK-LABEL: foo3:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    push r28
+; CHECK-NEXT:    push r29
+; CHECK-NEXT:    in r28, 61
+; CHECK-NEXT:    in r29, 62
+; CHECK-NEXT:    ldd r30, Y+5
+; CHECK-NEXT:    ldd r31, Y+6
+; CHECK-NEXT:    sub r20, r30
+; CHECK-NEXT:    sbc r21, r31
+; CHECK-NEXT:    sub r24, r22
+; CHECK-NEXT:    sbc r25, r23
+; CHECK-NEXT:    add r24, r20
+; CHECK-NEXT:    adc r25, r21
+; CHECK-NEXT:    pop r29
+; CHECK-NEXT:    pop r28
+; CHECK-NEXT:    ret
+  %e = sub i16 %a, %b
+  %g = sub i16 %c, %d
+  %h = add i16 %e, %g
+  ret i16 %h
+}
+
+; NOTE: %a(i32) costs four registers, while %b(i32) is passed via the stack.
+; FIXME: The `ldd` instruction is invalid on avrtiny, this test just shows
+;        how arguments are passed.
+define i32 @foo4(i32 %a, i32 %b) {
+; CHECK-LABEL: foo4:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    push r28
+; CHECK-NEXT:    push r29
+; CHECK-NEXT:    in r28, 61
+; CHECK-NEXT:    in r29, 62
+; CHECK-NEXT:    ldd r20, Y+5
+; CHECK-NEXT:    ldd r21, Y+6
+; CHECK-NEXT:    ldd r30, Y+7
+; CHECK-NEXT:    ldd r31, Y+8
+; CHECK-NEXT:    sub r20, r22
+; CHECK-NEXT:    sbc r21, r23
+; CHECK-NEXT:    sbc r30, r24
+; CHECK-NEXT:    sbc r31, r25
+; CHECK-NEXT:    mov r22, r20
+; CHECK-NEXT:    mov r23, r21
+; CHECK-NEXT:    mov r24, r30
+; CHECK-NEXT:    mov r25, r31
+; CHECK-NEXT:    pop r29
+; CHECK-NEXT:    pop r28
+; CHECK-NEXT:    ret
+  %c = sub i32 %b, %a
+  ret i32 %c
+}
+
+; NOTE: Though %0 costs 5 registers and there is one vacant register,
+;       %1(i8) passed via the stack.
+; FIXME: The `ldd` instruction is invalid on avrtiny, this test just shows
+;        how arguments are passed.
+define i8 @foo5([5 x i8] %0, i8 %1) {
+; CHECK-LABEL: foo5:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    push r28
+; CHECK-NEXT:    push r29
+; CHECK-NEXT:    in r28, 61
+; CHECK-NEXT:    in r29, 62
+; CHECK-NEXT:    ldd r24, Y+5
+; CHECK-NEXT:    add r24, r20
+; CHECK-NEXT:    pop r29
+; CHECK-NEXT:    pop r28
+; CHECK-NEXT:    ret
+  %3 = extractvalue [5 x i8] %0, 0
+  %4 = add i8 %3, %1
+  ret i8 %4
+}
+
+; NOTE: %0 costs two registers and %1 costs four registers.
+define i8 @foo6([2 x i8] %0, [4 x i8] %1) {
+; CHECK-LABEL: foo6:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    add r24, r20
+; CHECK-NEXT:    ret
+  %3 = extractvalue [2 x i8] %0, 0
+  %4 = extractvalue [4 x i8] %1, 0
+  %5 = add i8 %3, %4
+  ret i8 %5
+}
+
+; NOTE: %0 cost four registers, while %1 is passed via the stack,
+;       though there are two vacant registers.
+; FIXME: The `ldd` instruction is invalid on avrtiny, this test just shows
+;        how arguments are passed.
+define i8 @foo7([3 x i8] %0, [3 x i8] %1) {
+; CHECK-LABEL: foo7:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    push r28
+; CHECK-NEXT:    push r29
+; CHECK-NEXT:    in r28, 61
+; CHECK-NEXT:    in r29, 62
+; CHECK-NEXT:    ldd r24, Y+5
+; CHECK-NEXT:    add r24, r22
+; CHECK-NEXT:    pop r29
+; CHECK-NEXT:    pop r28
+; CHECK-NEXT:    ret
+  %3 = extractvalue [3 x i8] %0, 0
+  %4 = extractvalue [3 x i8] %1, 0
+  %5 = add i8 %3, %4
+  ret i8 %5
+}
+
+; NOTE: %0 costs four registers, and %1 costs two registers, while %2 is
+        passed via the stack, though there is one vacant register.
+; FIXME: The `ldd` instruction is invalid on avrtiny, this test just shows
+;        how arguments are passed.
+define i8 @foo8([3 x i8] %0, i8 %1, i8 %2) {
+; CHECK-LABEL: foo8:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    push r28
+; CHECK-NEXT:    push r29
+; CHECK-NEXT:    in r28, 61
+; CHECK-NEXT:    in r29, 62
+; CHECK-NEXT:    add r22, r20
+; CHECK-NEXT:    ldd r24, Y+5
+; CHECK-NEXT:    sub r24, r22
+; CHECK-NEXT:    pop r29
+; CHECK-NEXT:    pop r28
+; CHECK-NEXT:    ret
+  %4 = extractvalue [3 x i8] %0, 0
+  %5 = add i8 %4, %1
+  %6 = sub i8 %2, %5
+  ret i8 %6
+}
+
+; NOTE: %0 is passed via registers, though there are 6 vacant registers.
+; FIXME: The `ldd` instruction is invalid on avrtiny, this test just shows
+;        how arguments are passed.
+define i8 @foo9([7 x i8] %0) {
+; CHECK-LABEL: foo9:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    push r28
+; CHECK-NEXT:    push r29
+; CHECK-NEXT:    in r28, 61
+; CHECK-NEXT:    in r29, 62
+; CHECK-NEXT:    ldd r25, Y+6
+; CHECK-NEXT:    ldd r24, Y+5
+; CHECK-NEXT:    add r24, r25
+; CHECK-NEXT:    pop r29
+; CHECK-NEXT:    pop r28
+; CHECK-NEXT:    ret
+  %2 = extractvalue [7 x i8] %0, 0
+  %3 = extractvalue [7 x i8] %0, 1
+  %4 = add i8 %2, %3
+  ret i8 %4
+}
+
+; NOTE: %0 costs 6 registers, while %1 and %2 are passed via the stack.
+; FIXME: The `ldd` instruction is invalid on avrtiny, this test just shows
+;        how arguments are passed.
+define i8 @fooa([6 x i8] %0, i8 %1, i8 %2) {
+; CHECK-LABEL: fooa:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    push r28
+; CHECK-NEXT:    push r29
+; CHECK-NEXT:    in r28, 61
+; CHECK-NEXT:    in r29, 62
+; CHECK-NEXT:    ldd r25, Y+5
+; CHECK-NEXT:    ldd r24, Y+6
+; CHECK-NEXT:    sub r24, r25
+; CHECK-NEXT:    sub r24, r20
+; CHECK-NEXT:    pop r29
+; CHECK-NEXT:    pop r28
+; CHECK-NEXT:    ret
+  %4 = extractvalue [6 x i8] %0, 0
+  %5 = sub i8 %2, %1
+  %6 = sub i8 %5, %4
+  ret i8 %6
+}

llvm/test/MC/AVR/error.s

+# RUN: not llvm-mc -triple avr -mcpu=avrtiny %s 2>&1 \
+# RUN:     | FileCheck -check-prefix=AVRTINY %s
+# RUN: not llvm-mc -triple avr -mcpu=avr2 %s 2>&1 \
+# RUN:     | FileCheck -check-prefix=AVR2 %s
+
+# AVRTINY: error: invalid register on avrtiny
+mov r0, r16
+
+# AVRTINY: error: invalid register on avrtiny
+mov 1, r16
+
+# AVR2: error: invalid operand for instruction
+ldi r1, 15
+
+# AVR2: error: instruction requires a CPU feature not currently enabled
+lpm r8, Z+