[AVR][NFC] Fix incorrect register states in expanding pseudo instructions

[benshi001]

Five new tests are added

ASRBNRd.mir
LSLBNRd.mir
LSLWNRd.mir
LSRBNRd.mir
LSRWNRd.mir

Actually one extra ASRWNRd.mir should be added, I omitted it since it is added in D115618

[benshi001]

llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp

2088

The SrcReg should not be set killed when SrcReg==DstLoReg.

[benshi001]

llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp

2088

For example,

$r19r18 = sext killed $r18, though the src r18 is killed, but r19r18 is defined and live, so r18 can not be set to killed when expanding the pseudo.

[benshi001]

Without this patch, the following simple C code will crash.

int foo(char a, char b, ...) {
  return a + b;
}

The crash message is

# After AVR pseudo instruction expansion pass
# Machine code for function add: NoPHIs, TracksLiveness, NoVRegs, TiedOpsRewritten
Frame Objects:
  fi#-3: size=2, align=1, fixed, at location [SP+6]
  fi#-2: size=1, align=1, fixed, at location [SP+4]
  fi#-1: size=2, align=1, fixed, at location [SP+2]
  fi#0: dead
  fi#1: dead
  fi#2: size=1, align=1, at location [SP-1]
  fi#3: size=1, align=1, at location [SP-2]

bb.0 (%ir-block.2):
  liveins: $r28, $r29
  frame-setup PUSHRr killed $r28, implicit-def $sp, implicit $sp
  frame-setup PUSHRr killed $r29, implicit-def $sp, implicit $sp
  $r28 = frame-setup INRdA 61
  $r29 = frame-setup INRdA 62
  dead early-clobber $r24 = LDDRdPtrQ $r29r28, 7 :: (load (s8) from %fixed-stack.1)
  early-clobber $r24 = LDDRdPtrQ $r29r28, 5 :: (load (s16) from %fixed-stack.2, align 1)
  early-clobber $r25 = LDDRdPtrQ $r29r28, 6 :: (load (s16) from %fixed-stack.2, align 1)
  early-clobber $r24 = LDDRdPtrQ $r29r28, 5 :: (dereferenceable load (s16) from %ir.3, align 1)
  early-clobber $r25 = LDDRdPtrQ $r29r28, 6 :: (dereferenceable load (s16) from %ir.3, align 1)
  early-clobber $r18 = LDDRdPtrQ $r29r28, 7 :: (dereferenceable load (s8) from %ir.4)
  $r19 = MOVRdRr killed $r18
  $r19 = ADDRdRr $r19(tied-def 0), killed $r19, implicit-def $sreg
  $r19 = SBCRdRr killed $r19(tied-def 0), killed $r19, implicit-def dead $sreg, implicit killed $sreg
  $r24 = ADDRdRr $r24(tied-def 0), killed $r18, implicit-def $sreg
  $r25 = ADCRdRr $r25(tied-def 0), killed $r19, implicit-def dead $sreg, implicit killed $sreg
  $r29 = POPRd implicit-def $sp, implicit $sp
  $r28 = POPRd implicit-def $sp, implicit $sp
  RET implicit killed $r25r24

# End machine code for function add.

*** Bad machine code: Using an undefined physical register ***
- function:    add
- basic block: %bb.0  (0x55dbe136ed40)
- instruction: $r24 = ADDRdRr $r24(tied-def 0), killed $r18, implicit-def $sreg
- operand 2:   killed $r18
fatal error: error in backend: Found 1 machine code errors.
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace, preprocessed source, and associated run script.
Stack dump:
0.      Program arguments: ../build-avr-1/bin/clang test.c --target=avr -mmcu=atmega328 -S
1.      <eof> parser at end of file
2.      Code generation
3.      Running pass 'Function Pass Manager' on module 'test.c'.
4.      Running pass 'Verify generated machine code' on function '@add'
 #0 0x000055dbdce2227f PrintStackTraceSignalHandler(void*) Signals.cpp:0:0
 #1 0x000055dbdce1fdfc llvm::sys::CleanupOnSignal(unsigned long) (../build-avr-1/bin/clang+0x1fc0dfc)
 #2 0x000055dbdcd6d968 llvm::CrashRecoveryContext::HandleExit(int) (../build-avr-1/bin/clang+0x1f0e968)
 #3 0x000055dbdce181be llvm::sys::Process::Exit(int, bool) (../build-avr-1/bin/clang+0x1fb91be)
 #4 0x000055dbdbad90a6 (../build-avr-1/bin/clang+0xc7a0a6)
 #5 0x000055dbdcd7530f llvm::report_fatal_error(llvm::Twine const&, bool) (../build-avr-1/bin/clang+0x1f1630f)
 #6 0x000055dbdc247a3e (anonymous namespace)::MachineVerifierPass::runOnMachineFunction(llvm::MachineFunction&) (.part.480) MachineVerifier.cpp:0:0
 #7 0x000055dbdc247a71 (anonymous namespace)::MachineVerifierPass::runOnMachineFunction(llvm::MachineFunction&) MachineVerifier.cpp:0:0
 #8 0x000055dbdc1e1038 llvm::MachineFunctionPass::runOnFunction(llvm::Function&) (../build-avr-1/bin/clang+0x1382038)
 #9 0x000055dbdc6a345f llvm::FPPassManager::runOnFunction(llvm::Function&) (../build-avr-1/bin/clang+0x184445f)
#10 0x000055dbdc6a36f1 llvm::FPPassManager::runOnModule(llvm::Module&) (../build-avr-1/bin/clang+0x18446f1)
#11 0x000055dbdc6a49ef llvm::legacy::PassManagerImpl::run(llvm::Module&) (../build-avr-1/bin/clang+0x18459ef)
#12 0x000055dbdd138b4a clang::EmitBackendOutput(clang::DiagnosticsEngine&, clang::HeaderSearchOptions const&, clang::CodeGenOptions const&, clang::TargetOptions const&, clang::LangOptions const&, llvm::StringRef, llvm::Module*, clang::BackendAction, std::unique_ptr<llvm::raw_pwrite_stream, std::default_delete<llvm::raw_pwrite_stream> >) (../build-avr-1/bin/clang+0x22d9b4a)
#13 0x000055dbddd6a919 clang::BackendConsumer::HandleTranslationUnit(clang::ASTContext&) crtstuff.c:0:0
#14 0x000055dbde95d4a9 clang::ParseAST(clang::Sema&, bool, bool) (../build-avr-1/bin/clang+0x3afe4a9)
#15 0x000055dbddd6ab02 clang::CodeGenAction::ExecuteAction() (../build-avr-1/bin/clang+0x2f0bb02)
#16 0x000055dbdd7972e1 clang::FrontendAction::Execute() (../build-avr-1/bin/clang+0x29382e1)
#17 0x000055dbdd73119a clang::CompilerInstance::ExecuteAction(clang::FrontendAction&) (../build-avr-1/bin/clang+0x28d219a)
#18 0x000055dbdd8627b7 clang::ExecuteCompilerInvocation(clang::CompilerInstance*) (../build-avr-1/bin/clang+0x2a037b7)
#19 0x000055dbdbadaa84 cc1_main(llvm::ArrayRef<char const*>, char const*, void*) (../build-avr-1/bin/clang+0xc7ba84)
#20 0x000055dbdbad693d ExecuteCC1Tool(llvm::SmallVectorImpl<char const*>&) driver.cpp:0:0
#21 0x000055dbdd5caa75 void llvm::function_ref<void ()>::callback_fn<clang::driver::CC1Command::Execute(llvm::ArrayRef<llvm::Optional<llvm::StringRef> >, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >*, bool*) const::'lambda'()>(long) Job.cpp:0:0
#22 0x000055dbdcd6d813 llvm::CrashRecoveryContext::RunSafely(llvm::function_ref<void ()>) (../build-avr-1/bin/clang+0x1f0e813)
#23 0x000055dbdd5cce68 clang::driver::CC1Command::Execute(llvm::ArrayRef<llvm::Optional<llvm::StringRef> >, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >*, bool*) const (../build-avr-1/bin/clang+0x276de68)
#24 0x000055dbdd5a08ba clang::driver::Compilation::ExecuteCommand(clang::driver::Command const&, clang::driver::Command const*&) const (../build-avr-1/bin/clang+0x27418ba)
#25 0x000055dbdd5a148f clang::driver::Compilation::ExecuteJobs(clang::driver::JobList const&, llvm::SmallVectorImpl<std::pair<int, clang::driver::Command const*> >&) const (../build-avr-1/bin/clang+0x274248f)
#26 0x000055dbdd5a86e7 clang::driver::Driver::ExecuteCompilation(clang::driver::Compilation&, llvm::SmallVectorImpl<std::pair<int, clang::driver::Command const*> >&) (../build-avr-1/bin/clang+0x27496e7)
#27 0x000055dbdba4cd78 main (../build-avr-1/bin/clang+0xbedd78)
#28 0x00007f1836a46bf7 __libc_start_main /build/glibc-S9d2JN/glibc-2.27/csu/../csu/libc-start.c:344:0
#29 0x000055dbdbad64ea _start (../build-avr-1/bin/clang+0xc774ea)
clang-14: error: clang frontend command failed with exit code 70 (use -v to see invocation)
clang version 14.0.0 ([e-mail]:llvm/llvm-project.git 0adf0fd5cb59211934e96bfcdaedb18bfbb6357d)
Target: avr
Thread model: posix
InstalledDir: /home/shiben/work/llvm-project/build-avr-4/../build-avr-1/bin
clang-14: note: diagnostic msg:
********************

PLEASE ATTACH THE FOLLOWING FILES TO THE BUG REPORT:
Preprocessed source(s) and associated run script(s) are located at:
clang-14: note: diagnostic msg: /tmp/test-c9b549.c
clang-14: note: diagnostic msg: /tmp/test-c9b549.sh
clang-14: note: diagnostic msg:

********************

[benshi001]

llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp

2084

We can not set MOV's Operand(1) to killed when SrcReg==DstHiReg, since DstHiReg is the source operand of the following ADDRdRr.

llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp

bool AVRExpandPseudo::expand<AVR::NEGWRd>(Block &MBB, BlockIt MBBI) {
   bool DstIsKill = MI.getOperand(1).isKill();
   bool ImpIsDead = MI.getOperand(2).isDead();
   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
 
   // Do NEG on the upper byte.
   auto MIBHI =
       buildMI(MBB, MBBI, AVR::NEGRd)
           .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
-          .addReg(DstHiReg, getKillRegState(DstIsKill));
+          .addReg(DstHiReg, RegState::Kill);
   // SREG is always implicitly dead
   MIBHI->getOperand(2).setIsDead();
 
   // Do NEG on the lower byte.
   buildMI(MBB, MBBI, AVR::NEGRd)
       .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
       .addReg(DstLoReg, getKillRegState(DstIsKill));
 
bool AVRExpandPseudo::expand<AVR::ROLBRd>(Block &MBB, BlockIt MBBI) {
   // instead of 8. This is useful when we are dealing with numbers over
   // multiple registers, but when we actually need to rotate stuff, we have
   // to explicitly add the carry bit.
 
   MachineInstr &MI = *MBBI;
   unsigned OpShift, OpCarry;
   Register DstReg = MI.getOperand(0).getReg();
   bool DstIsDead = MI.getOperand(0).isDead();
+  bool DstIsKill = MI.getOperand(1).isKill();
   OpShift = AVR::ADDRdRr;
   OpCarry = AVR::ADCRdRr;
 
   // add r16, r16
   // adc r16, r1
 
   // Shift part
   buildMI(MBB, MBBI, OpShift)
       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
-      .addReg(DstReg)
-      .addReg(DstReg);
+      .addReg(DstReg, RegState::Kill)
+      .addReg(DstReg, RegState::Kill);
 
   // Add the carry bit
   auto MIB = buildMI(MBB, MBBI, OpCarry)
                  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
-                 .addReg(DstReg)
+                 .addReg(DstReg, getKillRegState(DstIsKill))
                  .addReg(ZERO_REGISTER);
 
   // SREG is always implicitly killed
   MIB->getOperand(2).setIsKill();
 
   MI.eraseFromParent();
   return true;
 }
bool AVRExpandPseudo::expand<AVR::LSLWRd>(Block &MBB, BlockIt MBBI) {
   bool ImpIsDead = MI.getOperand(2).isDead();
   unsigned OpLo = AVR::ADDRdRr; // ADD Rd, Rd <==> LSL Rd
   unsigned OpHi = AVR::ADCRdRr; // ADC Rd, Rd <==> ROL Rd
   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
 
   // Low part
   buildMI(MBB, MBBI, OpLo)
       .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
-      .addReg(DstLoReg)
+      .addReg(DstLoReg, getKillRegState(DstIsKill))
       .addReg(DstLoReg, getKillRegState(DstIsKill));
 
   auto MIBHI =
       buildMI(MBB, MBBI, OpHi)
           .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
-          .addReg(DstHiReg)
+          .addReg(DstHiReg, getKillRegState(DstIsKill))
           .addReg(DstHiReg, getKillRegState(DstIsKill));
 
   if (ImpIsDead)
     MIBHI->getOperand(3).setIsDead();
 
   // SREG is always implicitly killed
   MIBHI->getOperand(4).setIsKill();
 
bool AVRExpandPseudo::expandLSLW4Rd(Block &MBB, BlockIt MBBI) {
   bool DstIsKill = MI.getOperand(1).isKill();
   bool ImpIsDead = MI.getOperand(3).isDead();
   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
 
   // swap Rh
   // swap Rl
   buildMI(MBB, MBBI, AVR::SWAPRd)
       .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
-      .addReg(DstHiReg, getKillRegState(DstIsKill));
+      .addReg(DstHiReg, RegState::Kill);
   buildMI(MBB, MBBI, AVR::SWAPRd)
       .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
-      .addReg(DstLoReg, getKillRegState(DstIsKill));
+      .addReg(DstLoReg, RegState::Kill);
 
   // andi Rh, 0xf0
   auto MI0 =
       buildMI(MBB, MBBI, AVR::ANDIRdK)
           .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
-          .addReg(DstHiReg, getKillRegState(DstIsKill))
+          .addReg(DstHiReg, RegState::Kill)
           .addImm(0xf0);
   // SREG is implicitly dead.
   MI0->getOperand(3).setIsDead();
 
   // eor Rh, Rl
   auto MI1 =
       buildMI(MBB, MBBI, AVR::EORRdRr)
           .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
-          .addReg(DstHiReg, getKillRegState(DstIsKill))
+          .addReg(DstHiReg, RegState::Kill)
           .addReg(DstLoReg);
   // SREG is implicitly dead.
   MI1->getOperand(3).setIsDead();
 
   // andi Rl, 0xf0
   auto MI2 =
       buildMI(MBB, MBBI, AVR::ANDIRdK)
           .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
bool AVRExpandPseudo::expandLSLW12Rd(Block &MBB, BlockIt MBBI) {
   // mov Rh, Rl
   buildMI(MBB, MBBI, AVR::MOVRdRr)
       .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
       .addReg(DstLoReg);
 
   // swap Rh
   buildMI(MBB, MBBI, AVR::SWAPRd)
       .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
-      .addReg(DstHiReg, getKillRegState(DstIsKill));
+      .addReg(DstHiReg, RegState::Kill);
 
   // andi Rh, 0xf0
   auto MI0 =
       buildMI(MBB, MBBI, AVR::ANDIRdK)
           .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
           .addReg(DstHiReg, getKillRegState(DstIsKill))
           .addImm(0xf0);
   // SREG is implicitly dead.
bool AVRExpandPseudo::expandLSRW4Rd(Block &MBB, BlockIt MBBI) {
   bool DstIsKill = MI.getOperand(1).isKill();
   bool ImpIsDead = MI.getOperand(3).isDead();
   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
 
   // swap Rh
   // swap Rl
   buildMI(MBB, MBBI, AVR::SWAPRd)
       .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
-      .addReg(DstHiReg, getKillRegState(DstIsKill));
+      .addReg(DstHiReg, RegState::Kill);
   buildMI(MBB, MBBI, AVR::SWAPRd)
       .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
-      .addReg(DstLoReg, getKillRegState(DstIsKill));
+      .addReg(DstLoReg, RegState::Kill);
 
   // andi Rl, 0xf
   auto MI0 =
       buildMI(MBB, MBBI, AVR::ANDIRdK)
           .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
-          .addReg(DstLoReg, getKillRegState(DstIsKill))
+          .addReg(DstLoReg, RegState::Kill)
           .addImm(0xf);
   // SREG is implicitly dead.
   MI0->getOperand(3).setIsDead();
 
   // eor Rl, Rh
   auto MI1 =
       buildMI(MBB, MBBI, AVR::EORRdRr)
           .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
-          .addReg(DstLoReg, getKillRegState(DstIsKill))
+          .addReg(DstLoReg, RegState::Kill)
           .addReg(DstHiReg);
   // SREG is implicitly dead.
   MI1->getOperand(3).setIsDead();
 
   // andi Rh, 0xf
   auto MI2 =
       buildMI(MBB, MBBI, AVR::ANDIRdK)
           .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
bool AVRExpandPseudo::expandLSRW12Rd(Block &MBB, BlockIt MBBI) {
   // Move upper byte to lower byte.
   buildMI(MBB, MBBI, AVR::MOVRdRr)
       .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
       .addReg(DstHiReg);
 
   // swap Rl
   buildMI(MBB, MBBI, AVR::SWAPRd)
       .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
-      .addReg(DstLoReg, getKillRegState(DstIsKill));
+      .addReg(DstLoReg, RegState::Kill);
 
   // andi Rl, 0xf
   auto MI0 =
       buildMI(MBB, MBBI, AVR::ANDIRdK)
           .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
           .addReg(DstLoReg, getKillRegState(DstIsKill))
           .addImm(0xf);
   // SREG is implicitly dead.
bool AVRExpandPseudo::expandASRW8Rd(Block &MBB, BlockIt MBBI) {
 
   // Move upper byte to lower byte.
   buildMI(MBB, MBBI, AVR::MOVRdRr)
       .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
       .addReg(DstHiReg);
 
   // Move the sign bit to the C flag.
   buildMI(MBB, MBBI, AVR::ADDRdRr)
-      .addReg(DstHiReg, RegState::Define, getDeadRegState(DstIsDead))
-      .addReg(DstHiReg, getKillRegState(DstIsKill) | getDeadRegState(DstIsDead))
-      .addReg(DstHiReg, getKillRegState(DstIsKill));
+      .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
+      .addReg(DstHiReg, RegState::Kill)
+      .addReg(DstHiReg, RegState::Kill);
 
   // Set upper byte to 0 or -1.
   auto MIBHI =
       buildMI(MBB, MBBI, AVR::SBCRdRr)
           .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
           .addReg(DstHiReg, getKillRegState(DstIsKill))
           .addReg(DstHiReg, getKillRegState(DstIsKill));
   if (ImpIsDead)
bool AVRExpandPseudo::expandLSLB7Rd(Block &MBB, BlockIt MBBI) {
   bool ImpIsDead = MI.getOperand(3).isDead();
 
   // ror r24
   // clr r24
   // ror r24
 
   buildMI(MBB, MBBI, AVR::RORRd)
       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
-      .addReg(DstReg, getKillRegState(DstIsKill))
+      .addReg(DstReg, RegState::Kill)
       ->getOperand(3)
       .setIsUndef(true);
 
   buildMI(MBB, MBBI, AVR::EORRdRr)
       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
-      .addReg(DstReg, getKillRegState(DstIsKill))
-      .addReg(DstReg, getKillRegState(DstIsKill));
+      .addReg(DstReg, RegState::Kill)
+      .addReg(DstReg, RegState::Kill);
 
   auto MIRRC =
       buildMI(MBB, MBBI, AVR::RORRd)
           .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
           .addReg(DstReg, getKillRegState(DstIsKill));
 
   if (ImpIsDead)
     MIRRC->getOperand(2).setIsDead();
bool AVRExpandPseudo::expandLSRB7Rd(Block &MBB, BlockIt MBBI) {
   bool ImpIsDead = MI.getOperand(3).isDead();
 
   // rol r24
   // clr r24
   // rol r24
 
   buildMI(MBB, MBBI, AVR::ADCRdRr)
       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
-      .addReg(DstReg, getKillRegState(DstIsKill))
-      .addReg(DstReg, getKillRegState(DstIsKill))
+      .addReg(DstReg, RegState::Kill)
+      .addReg(DstReg, RegState::Kill)
       ->getOperand(4)
       .setIsUndef(true);
 
   buildMI(MBB, MBBI, AVR::EORRdRr)
       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
-      .addReg(DstReg, getKillRegState(DstIsKill))
-      .addReg(DstReg, getKillRegState(DstIsKill));
+      .addReg(DstReg, RegState::Kill)
+      .addReg(DstReg, RegState::Kill);
 
   auto MIRRC =
       buildMI(MBB, MBBI, AVR::ADCRdRr)
           .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
           .addReg(DstReg, getKillRegState(DstIsKill))
           .addReg(DstReg, getKillRegState(DstIsKill));
 
   if (ImpIsDead)
bool AVRExpandPseudo::expandASRB6Rd(Block &MBB, BlockIt MBBI) {
   buildMI(MBB, MBBI, AVR::BST)
       .addReg(DstReg)
       .addImm(6)
       ->getOperand(2)
       .setIsUndef(true);
 
   buildMI(MBB, MBBI, AVR::ADDRdRr) // LSL Rd <==> ADD Rd, Rd
       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
-      .addReg(DstReg, getKillRegState(DstIsKill))
-      .addReg(DstReg, getKillRegState(DstIsKill));
+      .addReg(DstReg, RegState::Kill)
+      .addReg(DstReg, RegState::Kill);
 
   buildMI(MBB, MBBI, AVR::SBCRdRr)
       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
-      .addReg(DstReg, getKillRegState(DstIsKill))
-      .addReg(DstReg, getKillRegState(DstIsKill));
+      .addReg(DstReg, RegState::Kill)
+      .addReg(DstReg, RegState::Kill);
 
   buildMI(MBB, MBBI, AVR::BLD)
       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
       .addReg(DstReg, getKillRegState(DstIsKill))
       .addImm(0)
       ->getOperand(3)
       .setIsKill();
 
   MI.eraseFromParent();
   return true;
 }
 
 bool AVRExpandPseudo::expandASRB7Rd(Block &MBB, BlockIt MBBI) {
   MachineInstr &MI = *MBBI;
   Register DstReg = MI.getOperand(0).getReg();
   bool DstIsDead = MI.getOperand(0).isDead();
   bool DstIsKill = MI.getOperand(1).isKill();
   bool ImpIsDead = MI.getOperand(3).isDead();
 
   // lsl r24
   // sbc r24, r24
 
   buildMI(MBB, MBBI, AVR::ADDRdRr)
       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
-      .addReg(DstReg, getKillRegState(DstIsKill))
-      .addReg(DstReg, getKillRegState(DstIsKill));
+      .addReg(DstReg, RegState::Kill)
+      .addReg(DstReg, RegState::Kill);
 
   auto MIRRC =
       buildMI(MBB, MBBI, AVR::SBCRdRr)
           .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
           .addReg(DstReg, getKillRegState(DstIsKill))
           .addReg(DstReg, getKillRegState(DstIsKill));
 
   if (ImpIsDead)
template <> bool AVRExpandPseudo::expand<AVR::SEXT>(Block &MBB, BlockIt MBBI) {
   // sbc     r17, r17
   Register DstReg = MI.getOperand(0).getReg();
   Register SrcReg = MI.getOperand(1).getReg();
   bool DstIsDead = MI.getOperand(0).isDead();
   bool SrcIsKill = MI.getOperand(1).isKill();
   bool ImpIsDead = MI.getOperand(2).isDead();
   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
 
-  if (SrcReg != DstLoReg) {
-    auto MOV =
-        buildMI(MBB, MBBI, AVR::MOVRdRr)
-            .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
-            .addReg(SrcReg);
+  if (SrcReg != DstLoReg)
 
-    if (SrcReg == DstHiReg) {
-      MOV->getOperand(1).setIsKill();
-    }
-  }
-
   if (SrcReg != DstHiReg) {
-    buildMI(MBB, MBBI, AVR::MOVRdRr)
+    auto MOV = buildMI(MBB, MBBI, AVR::MOVRdRr)
                    .addReg(DstHiReg, RegState::Define)
-        .addReg(SrcReg, getKillRegState(SrcIsKill));
+                   .addReg(SrcReg);
+    if (SrcReg != DstLoReg && SrcIsKill)
+      MOV->getOperand(1).setIsKill();
   }
 
   buildMI(MBB, MBBI, AVR::ADDRdRr) // LSL Rd <==> ADD Rd, Rr
       .addReg(DstHiReg, RegState::Define)
-      .addReg(DstHiReg)
+      .addReg(DstHiReg, RegState::Kill)
       .addReg(DstHiReg, RegState::Kill);
 
   auto SBC =
       buildMI(MBB, MBBI, AVR::SBCRdRr)
           .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
           .addReg(DstHiReg, RegState::Kill)
           .addReg(DstHiReg, RegState::Kill);
 

llvm/test/CodeGen/AVR/pseudo/ASRBNRd.mir

+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
+
+--- |
+  target triple = "avr--"
+  define void @test() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test
+body: |
+  bb.0.entry:
+    liveins: $r17
+
+    ; CHECK-LABEL: test
+
+    ; CHECK:      $r17 = ADDRdRr killed $r17, killed $r17, implicit-def $sreg
+    ; CHECK-NEXT: $r17 = SBCRdRr $r17, $r17, implicit-def $sreg, implicit killed $sreg
+    $r17 = ASRBNRd $r17, 7, implicit-def $sreg
+...

llvm/test/CodeGen/AVR/pseudo/LSLBNRd.mir

+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
+
+--- |
+  target triple = "avr--"
+  define void @test() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test
+body: |
+  bb.0.entry:
+    liveins: $r17
+
+    ; CHECK-LABEL: test
+
+    ; CHECK:      $r17 = RORRd killed $r17, implicit-def $sreg, implicit undef $sreg
+    ; CHECK-NEXT: $r17 = EORRdRr killed $r17, killed $r17, implicit-def $sreg
+    ; CHECK-NEXT: $r17 = RORRd $r17, implicit-def $sreg, implicit killed $sreg
+    $r17 = LSLBNRd $r17, 7, implicit-def $sreg
+...

llvm/test/CodeGen/AVR/pseudo/LSLWNRd.mir

+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
+
+--- |
+  target triple = "avr--"
+  define void @test() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test
+body: |
+  bb.0.entry:
+    liveins: $r17r16, $r19r18, $r21r20
+
+    ; CHECK-LABEL: test
+
+    ; CHECK:      $r17 = SWAPRd killed $r17
+    ; CHECK-NEXT: $r16 = SWAPRd killed $r16
+    ; CHECK-NEXT: $r17 = ANDIRdK killed $r17, 240, implicit-def dead $sreg
+    ; CHECK-NEXT: $r17 = EORRdRr killed $r17, $r16, implicit-def dead $sreg
+    ; CHECK-NEXT: $r16 = ANDIRdK $r16, 240, implicit-def dead $sreg
+    ; CHECK-NEXT: $r17 = EORRdRr $r17, $r16, implicit-def $sreg
+    $r17r16 = LSLWNRd $r17r16,  4, implicit-def $sreg
+
+    ; CHECK-NEXT: $r19 = MOVRdRr $r18
+    ; CHECK-NEXT: $r18 = EORRdRr $r18, $r18, implicit-def $sreg
+    $r19r18 = LSLWNRd $r19r18,  8, implicit-def $sreg
+
+    ; CHECK-NEXT: $r21 = MOVRdRr $r20
+    ; CHECK-NEXT: $r21 = SWAPRd killed $r21
+    ; CHECK-NEXT: $r21 = ANDIRdK $r21, 240, implicit-def dead $sreg
+    ; CHECK-NEXT: $r20 = EORRdRr $r20, $r20, implicit-def $sreg
+    $r21r20 = LSLWNRd $r21r20, 12, implicit-def $sreg
+...

llvm/test/CodeGen/AVR/pseudo/LSRBNRd.mir

+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
+
+--- |
+  target triple = "avr--"
+  define void @test() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test
+body: |
+  bb.0.entry:
+    liveins: $r17
+
+    ; CHECK-LABEL: test
+
+    ; CHECK:      $r17 = ADCRdRr killed $r17, killed $r17, implicit-def $sreg, implicit undef $sreg
+    ; CHECK-NEXT: $r17 = EORRdRr killed $r17, killed $r17, implicit-def $sreg
+    ; CHECK-NEXT: $r17 = ADCRdRr $r17, $r17, implicit-def $sreg, implicit killed $sreg
+    $r17 = LSRBNRd $r17, 7, implicit-def $sreg
+...

llvm/test/CodeGen/AVR/pseudo/LSRWNRd.mir

+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
+
+--- |
+  target triple = "avr--"
+  define void @test() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test
+body: |
+  bb.0.entry:
+    liveins: $r17r16, $r19r18, $r21r20
+
+    ; CHECK-LABEL: test
+
+    ; CHECK:      $r17 = SWAPRd killed $r17
+    ; CHECK-NEXT: $r16 = SWAPRd killed $r16
+    ; CHECK-NEXT: $r16 = ANDIRdK killed $r16, 15, implicit-def dead $sreg
+    ; CHECK-NEXT: $r16 = EORRdRr killed $r16, $r17, implicit-def dead $sreg
+    ; CHECK-NEXT: $r17 = ANDIRdK $r17, 15, implicit-def dead $sreg
+    ; CHECK-NEXT: $r16 = EORRdRr $r16, $r17, implicit-def $sreg
+    $r17r16 = LSRWNRd $r17r16,  4, implicit-def $sreg
+
+    ; CHECK-NEXT: $r18 = MOVRdRr $r19
+    ; CHECK-NEXT: $r19 = EORRdRr $r19, $r19, implicit-def $sreg
+    $r19r18 = LSRWNRd $r19r18,  8, implicit-def $sreg
+
+    ; CHECK-NEXT: $r20 = MOVRdRr $r21
+    ; CHECK-NEXT: $r20 = SWAPRd killed $r20
+    ; CHECK-NEXT: $r20 = ANDIRdK $r20, 15, implicit-def dead $sreg
+    ; CHECK-NEXT: $r21 = EORRdRr $r21, $r21, implicit-def $sreg
+    $r21r20 = LSRWNRd $r21r20, 12, implicit-def $sreg
+...

llvm/test/CodeGen/AVR/pseudo/NEGWRd.mir

 ---
 name:            test_negwrd
 body: |
   bb.0.entry:
     liveins: $r15r14
 
     ; CHECK-LABEL: test_negwrd
 
-    ; CHECK:      $r15 = NEGRd $r15, implicit-def dead $sreg
+    ; CHECK:      $r15 = NEGRd killed $r15, implicit-def dead $sreg
     ; CHECK-NEXT: $r14 = NEGRd $r14
     ; CHECK-NEXT: $r15 = SBCRdRr $r15, $r1, implicit-def $sreg, implicit killed $sreg
 
     $r15r14 = NEGWRd $r15r14, implicit-def $sreg
 ...

llvm/test/CodeGen/AVR/pseudo/SEXT.mir

 body: |
   bb.0.entry:
     liveins: $r31
 
     ; CHECK-LABEL: test
 
     ; CHECK:      $r14 = MOVRdRr $r31
     ; CHECK-NEXT: $r15 = MOVRdRr $r31
-    ; CHECK-NEXT: $r15 = ADDRdRr $r15, killed $r15, implicit-def $sreg
+    ; CHECK-NEXT: $r15 = ADDRdRr killed $r15, killed $r15, implicit-def $sreg
     ; CHECK-NEXT: $r15 = SBCRdRr killed $r15, killed $r15, implicit-def $sreg, implicit killed $sreg
 
     $r15r14 = SEXT $r31, implicit-def $sreg
 ...

llvm/test/CodeGen/AVR/pseudo/ZEXT.mir

 body: |
   bb.0.entry:
     liveins: $r31
 
     ; CHECK-LABEL: test
 
     ; CHECK:      $r14 = MOVRdRr $r31
     ; CHECK-NEXT: $r15 = MOVRdRr $r31
-    ; CHECK-NEXT: $r15 = ADDRdRr $r15, killed $r15, implicit-def $sreg
+    ; CHECK-NEXT: $r15 = ADDRdRr killed $r15, killed $r15, implicit-def $sreg
     ; CHECK-NEXT: $r15 = SBCRdRr killed $r15, killed $r15, implicit-def $sreg, implicit killed $sreg
 
     $r15r14 = SEXT $r31, implicit-def $sreg
 ...