This is an archive of the discontinued LLVM Phabricator instance.

Differential D120197

[libunwind] Further fix for 32-bit PowerPC processors without AltiVec
ClosedPublic

Authored by brad on Feb 19 2022, 4:40 PM.

Details

Reviewers
Bdragon28
MaskRay
luporl
compnerd
jhibbits
Group Reviewers
Restricted Project
Commits
rG3fa2e66c10aa: [libunwind] Further fix for 32-bit PowerPC processors without AltiVec
Summary

OpenBSD had a local patch to fix libunwind with 32-bit PowerPC processors without AltiVec support (Motorola G3). https://reviews.llvm.org/D91906 eliminated almost all of our patch, but merging forward to 13 and adjusting based on that commit there was one more piece, which I am presenting here.

Diff Detail

Event Timeline

brad created this revision.Feb 19 2022, 4:40 PM
Herald added 1 blocking reviewer(s): Restricted Project. · View Herald TranscriptFeb 19 2022, 4:40 PM
Herald added subscribers: steven.zhang, shchenz, krytarowski, nemanjai. · View Herald Transcript
brad requested review of this revision.Feb 19 2022, 4:40 PM
brad edited the summary of this revision. (Show Details)Feb 19 2022, 4:47 PM
Harbormaster completed remote builds in B150563: Diff 410116.Feb 19 2022, 5:35 PM
luporl accepted this revision.Feb 21 2022, 3:57 AM

It makes sense. Besides, the corresponding code in src/UnwindRegistersRestore.S doesn't read the saved VRSave register anymore, when __ALTIVEC__ isn't defined.

This revision was not accepted when it landed; it landed in state Needs Review.Feb 21 2022, 12:31 PM
Closed by commit rG3fa2e66c10aa: [libunwind] Further fix for 32-bit PowerPC processors without AltiVec (authored by kernigh, committed by brad). · Explain Why
This revision was automatically updated to reflect the committed changes.
brad added a commit: rG3fa2e66c10aa: [libunwind] Further fix for 32-bit PowerPC processors without AltiVec.

Revision Contents

PathSize
libunwind/
src/
2 lines

Diff 410367

libunwind/src/UnwindRegistersSave.S

Show First 20 Lines • Show All 597 Lines • ▼ Show 20 LinesDEFINE_LIBUNWIND_FUNCTION(__unw_getcontext)
stw 25,108(3) stw 25,108(3)
stw 26,112(3) stw 26,112(3)
stw 27,116(3) stw 27,116(3)
stw 28,120(3) stw 28,120(3)
stw 29,124(3) stw 29,124(3)
stw 30,128(3) stw 30,128(3)
stw 31,132(3) stw 31,132(3)
#if defined(__ALTIVEC__)
// save VRSave register // save VRSave register
mfspr 0, 256 mfspr 0, 256
stw 0, 156(3) stw 0, 156(3)
#endif
// save CR registers // save CR registers
mfcr 0 mfcr 0
stw 0, 136(3) stw 0, 136(3)
// save CTR register // save CTR register
mfctr 0 mfctr 0
stw 0, 148(3) stw 0, 148(3)
#if !defined(__NO_FPRS__) #if !defined(__NO_FPRS__)
▲ Show 20 Lines • Show All 559 Lines • Show Last 20 Lines