[RISCV] Add schedule class for Zbp extension and Zbr extension

[Jimerlife]

Summary

Try to add schedule class for Zbp extension and Zbr extension

[Jimerlife]

rebase main

[Jimerlife]

rebase main

[Jimerlife]

ping

[craig.topper]

LGTM

Out of curiosity, what is your interest in the unratified bitmanip extensions? Do you work for a company that is implementing these extensions in hardware?

[Jimerlife]

In D120012#3350264, @craig.topper wrote:

LGTM

Out of curiosity, what is your interest in the unratified bitmanip extensions? Do you work for a company that is implementing these extensions in hardware?

I just want to complete 10 commits quickly for obtaining commit access of llvm, so I choose bitmanip extensions.

llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

def BSETI : RVBShift_ri<0b00101, 0b001, OPC_OP_IMM, "bseti">,
             Sched<[WriteSingleBitImm, ReadSingleBitImm]>;
 def BINVI : RVBShift_ri<0b01101, 0b001, OPC_OP_IMM, "binvi">,
             Sched<[WriteSingleBitImm, ReadSingleBitImm]>;
 def BEXTI : RVBShift_ri<0b01001, 0b101, OPC_OP_IMM, "bexti">,
             Sched<[WriteSingleBitImm, ReadSingleBitImm]>;
 } // Predicates = [HasStdExtZbs]
 
 let Predicates = [HasStdExtZbp] in {
-def GORC : ALU_rr<0b0010100, 0b101, "gorc">, Sched<[]>;
-def GREV : ALU_rr<0b0110100, 0b101, "grev">, Sched<[]>;
+def GORC : ALU_rr<0b0010100, 0b101, "gorc">,
+           Sched<[WriteORC, ReadORC, ReadORC]>;
+def GREV : ALU_rr<0b0110100, 0b101, "grev">,
+           Sched<[WriteREV, ReadREV, ReadREV]>;
+
+def GREVI : RVBShift_ri<0b01101, 0b101, OPC_OP_IMM, "grevi">,
+            Sched<[WriteREVImm, ReadREVImm]>;
+def GORCI : RVBShift_ri<0b00101, 0b101, OPC_OP_IMM, "gorci">,
+            Sched<[WriteORCImm, ReadORCImm]>;
+
+def SHFL   : ALU_rr<0b0000100, 0b001, "shfl">,
+             Sched<[WriteSHFL, ReadSHFL, ReadSHFL]>;
+def UNSHFL : ALU_rr<0b0000100, 0b101, "unshfl">,
+             Sched<[WriteUNSHFL, ReadUNSHFL, ReadUNSHFL]>;
+
+def SHFLI   : RVBShfl_ri<0b0000100, 0b001, OPC_OP_IMM, "shfli">,
+              Sched<[WriteSHFLImm, ReadSHFLImm]>;
+def UNSHFLI : RVBShfl_ri<0b0000100, 0b101, OPC_OP_IMM, "unshfli">,
+              Sched<[WriteUNSHFLImm, ReadUNSHFLImm]>;
 
-def GREVI : RVBShift_ri<0b01101, 0b101, OPC_OP_IMM, "grevi">, Sched<[]>;
-def GORCI : RVBShift_ri<0b00101, 0b101, OPC_OP_IMM, "gorci">, Sched<[]>;
-
-def SHFL   : ALU_rr<0b0000100, 0b001, "shfl">, Sched<[]>;
-def UNSHFL : ALU_rr<0b0000100, 0b101, "unshfl">, Sched<[]>;
-
-def SHFLI   : RVBShfl_ri<0b0000100, 0b001, OPC_OP_IMM, "shfli">, Sched<[]>;
-def UNSHFLI : RVBShfl_ri<0b0000100, 0b101, OPC_OP_IMM, "unshfli">, Sched<[]>;
-
-def XPERM_H : ALU_rr<0b0010100, 0b110, "xperm.h">, Sched<[]>;
+def XPERM_H : ALU_rr<0b0010100, 0b110, "xperm.h">,
+              Sched<[WriteXPERMH, ReadXPERMH, ReadXPERMH]>;
 } // Predicates = [HasStdExtZbp]
 
 let Predicates = [HasStdExtZbp, IsRV64] in {
-def GORCW  : ALUW_rr<0b0010100, 0b101, "gorcw">, Sched<[]>;
-def GREVW  : ALUW_rr<0b0110100, 0b101, "grevw">, Sched<[]>;
-
-def GORCIW : RVBShiftW_ri<0b0010100, 0b101, OPC_OP_IMM_32, "gorciw">, Sched<[]>;
-def GREVIW : RVBShiftW_ri<0b0110100, 0b101, OPC_OP_IMM_32, "greviw">, Sched<[]>;
+def GORCW  : ALUW_rr<0b0010100, 0b101, "gorcw">,
+             Sched<[WriteORC32, ReadORC32, ReadORC32]>;
+def GREVW  : ALUW_rr<0b0110100, 0b101, "grevw">,
+             Sched<[WriteREV32, ReadREV32, ReadREV32]>;
+
+def GORCIW : RVBShiftW_ri<0b0010100, 0b101, OPC_OP_IMM_32, "gorciw">,
+             Sched<[WriteREVImm32, ReadREVImm32]>;
+def GREVIW : RVBShiftW_ri<0b0110100, 0b101, OPC_OP_IMM_32, "greviw">,
+             Sched<[WriteORCImm32, ReadORCImm32]>;
+
+def SHFLW   : ALUW_rr<0b0000100, 0b001, "shflw">,
+              Sched<[WriteSHFL32, ReadSHFL32, ReadSHFL32]>;
+def UNSHFLW : ALUW_rr<0b0000100, 0b101, "unshflw">,
+              Sched<[WriteUNSHFL32, ReadUNSHFL32, ReadUNSHFL32]>;
 
-def SHFLW   : ALUW_rr<0b0000100, 0b001, "shflw">, Sched<[]>;
-def UNSHFLW : ALUW_rr<0b0000100, 0b101, "unshflw">, Sched<[]>;
-
-def XPERM_W : ALU_rr<0b0010100, 0b000, "xperm.w">, Sched<[]>;
+def XPERM_W : ALU_rr<0b0010100, 0b000, "xperm.w">,
+              Sched<[WriteXPERMW, ReadXPERMW, ReadXPERMW]>;
 } // Predicates = [HasStdExtZbp, IsRV64]
 
 // These instructions were named xperm.n and xperm.b in the last version of
 // the draft bit manipulation specification they were included in. However, we
 // use the mnemonics given to them in the ratified Zbkx extension.
 let Predicates = [HasStdExtZbpOrZbkx] in {
 def XPERM4 : ALU_rr<0b0010100, 0b010, "xperm4">, Sched<[]>;
 def XPERM8 : ALU_rr<0b0010100, 0b100, "xperm8">, Sched<[]>;

 def SEXT_B : RVBUnary<0b0110000, 0b00100, 0b001, OPC_OP_IMM, "sext.b">,
              Sched<[WriteIALU, ReadIALU]>;
 def SEXT_H : RVBUnary<0b0110000, 0b00101, 0b001, OPC_OP_IMM, "sext.h">,
              Sched<[WriteIALU, ReadIALU]>;
 } // Predicates = [HasStdExtZbb]
 
 let Predicates = [HasStdExtZbr] in {
 def CRC32_B : RVBUnary<0b0110000, 0b10000, 0b001, OPC_OP_IMM, "crc32.b">,
-              Sched<[]>;
+              Sched<[WriteCRCB, ReadCRCB]>;
 def CRC32_H : RVBUnary<0b0110000, 0b10001, 0b001, OPC_OP_IMM, "crc32.h">,
-              Sched<[]>;
+              Sched<[WriteCRCH, ReadCRCH]>;
 def CRC32_W : RVBUnary<0b0110000, 0b10010, 0b001, OPC_OP_IMM, "crc32.w">,
-              Sched<[]>;
+              Sched<[WriteCRCW, ReadCRCW]>;
 
 def CRC32C_B : RVBUnary<0b0110000, 0b11000, 0b001, OPC_OP_IMM, "crc32c.b">,
-               Sched<[]>;
+               Sched<[WriteCRCCB, ReadCRCCB]>;
 def CRC32C_H : RVBUnary<0b0110000, 0b11001, 0b001, OPC_OP_IMM, "crc32c.h">,
-               Sched<[]>;
+               Sched<[WriteCRCCH, ReadCRCCH]>;
 def CRC32C_W : RVBUnary<0b0110000, 0b11010, 0b001, OPC_OP_IMM, "crc32c.w">,
-               Sched<[]>;
+               Sched<[WriteCRCCW, ReadCRCCW]>;
 } // Predicates = [HasStdExtZbr]
 
 let Predicates = [HasStdExtZbr, IsRV64] in {
 def CRC32_D  : RVBUnary<0b0110000, 0b10011, 0b001, OPC_OP_IMM, "crc32.d">,
-               Sched<[]>;
+               Sched<[WriteCRCD, ReadCRCD]>;
 
 def CRC32C_D : RVBUnary<0b0110000, 0b11011, 0b001, OPC_OP_IMM, "crc32c.d">,
-               Sched<[]>;
+               Sched<[WriteCRCCD, ReadCRCCD]>;
 } // Predicates = [HasStdExtZbr, IsRV64]
 
 let Predicates = [HasStdExtZbc] in {
 def CLMULR : ALU_rr<0b0000101, 0b010, "clmulr">,
              Sched<[WriteCLMUL, ReadCLMUL, ReadCLMUL]>;
 } // Predicates = [HasStdExtZbc]
 
 let Predicates = [HasStdExtZbcOrZbkc] in {

 let Predicates = [HasStdExtZbe, IsRV64] in {
 // NOTE: These mnemonics are from the 0.94 spec. There is a name conflict with
 // bextw in the 0.93 spec.
 def BDECOMPRESSW : ALUW_rr<0b0100100, 0b110, "bdecompressw">, Sched<[]>;
 def BCOMPRESSW   : ALUW_rr<0b0000100, 0b110, "bcompressw">, Sched<[]>;
 } // Predicates = [HasStdExtZbe, IsRV64]
 
 let Predicates = [HasStdExtZbpOrZbkb] in {
-def PACK  : ALU_rr<0b0000100, 0b100, "pack">, Sched<[]>;
-def PACKH : ALU_rr<0b0000100, 0b111, "packh">, Sched<[]>;
+def PACK  : ALU_rr<0b0000100, 0b100, "pack">,
+            Sched<[WritePACK, ReadPACK, ReadPACK]>;
+def PACKH : ALU_rr<0b0000100, 0b111, "packh">,
+            Sched<[WritePACK, ReadPACK, ReadPACK]>;
 } // Predicates = [HasStdExtZbpOrZbkb]
 
 let Predicates = [HasStdExtZbpOrZbkb, IsRV64] in 
-def PACKW  : ALUW_rr<0b0000100, 0b100, "packw">, Sched<[]>;
+def PACKW  : ALUW_rr<0b0000100, 0b100, "packw">,
+             Sched<[WritePACK32, ReadPACK32, ReadPACK32]>;
 
 let Predicates = [HasStdExtZbp] in 
-def PACKU : ALU_rr<0b0100100, 0b100, "packu">, Sched<[]>;
+def PACKU : ALU_rr<0b0100100, 0b100, "packu">,
+            Sched<[WritePACKU, ReadPACKU, ReadPACKU]>;
 
 let Predicates = [HasStdExtZbp, IsRV64] in 
-def PACKUW : ALUW_rr<0b0100100, 0b100, "packuw">, Sched<[]>;
+def PACKUW : ALUW_rr<0b0100100, 0b100, "packuw">,
+             Sched<[WritePACKU32, ReadPACKU32, ReadPACKU32]>;
 
 let Predicates = [HasStdExtZbm, IsRV64] in {
 def BMATFLIP : RVBUnary<0b0110000, 0b00011, 0b001, OPC_OP_IMM, "bmatflip">,
                Sched<[]>;
 
 def BMATOR   : ALU_rr<0b0000100, 0b011, "bmator">, Sched<[]>;
 def BMATXOR  : ALU_rr<0b0100100, 0b011, "bmatxor">, Sched<[]>;
 } // Predicates = [HasStdExtZbm, IsRV64]

llvm/lib/Target/RISCV/RISCVSchedRocket.td

 //===----------------------------------------------------------------------===//
 // Unsupported extensions
 defm : UnsupportedSchedV;
 defm : UnsupportedSchedZba;
 defm : UnsupportedSchedZbb;
 defm : UnsupportedSchedZbc;
 defm : UnsupportedSchedZbs;
 defm : UnsupportedSchedZbf;
+defm : UnsupportedSchedZbp;
+defm : UnsupportedSchedZbr;
 defm : UnsupportedSchedZfh;
 }

llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

 //===----------------------------------------------------------------------===//
 // Unsupported extensions
 defm : UnsupportedSchedV;
 defm : UnsupportedSchedZba;
 defm : UnsupportedSchedZbb;
 defm : UnsupportedSchedZbc;
 defm : UnsupportedSchedZbs;
 defm : UnsupportedSchedZbf;
+defm : UnsupportedSchedZbp;
+defm : UnsupportedSchedZbr;
 defm : UnsupportedSchedZfh;
 }

llvm/lib/Target/RISCV/RISCVScheduleB.td

 // Zbs extension
 def WriteSingleBit   : SchedWrite; // BCLR/BSET/BINV/BEXT
 def WriteSingleBitImm: SchedWrite; // BCLRI/BSETI/BINVI/BEXTI
 
 // Zbf extension
 def WriteBFP         : SchedWrite; // BFP
 def WriteBFP32       : SchedWrite; // BFPW
 
+// Zbp extension
+def WriteORC         : SchedWrite; // gorc
+def WriteREV         : SchedWrite; // grev
+def WriteORC32       : SchedWrite; // gorcw
+def WriteREV32       : SchedWrite; // grevw
+def WriteREVImm      : SchedWrite; // grevi
+def WriteORCImm      : SchedWrite; // gorci
+def WriteREVImm32    : SchedWrite; // greviw
+def WriteORCImm32    : SchedWrite; // gorciw
+def WriteSHFL        : SchedWrite; // shfl
+def WriteUNSHFL      : SchedWrite; // unshfl
+def WriteSHFL32      : SchedWrite; // shflw
+def WriteUNSHFL32    : SchedWrite; // unshflw
+def WriteSHFLImm     : SchedWrite; // shfli
+def WriteUNSHFLImm   : SchedWrite; // unshfli
+def WriteXPERMH      : SchedWrite; // xperm.h
+def WriteXPERMW      : SchedWrite; // xperm.w
+def WritePACK        : SchedWrite; // pack/packh
+def WritePACK32      : SchedWrite; // packw
+def WritePACKU       : SchedWrite; // packu
+def WritePACKU32     : SchedWrite; // packuw
+
+// Zbr extension
+def WriteCRCB        : SchedWrite; // crc32.b
+def WriteCRCH        : SchedWrite; // crc32.h
+def WriteCRCW        : SchedWrite; // crc32.w
+def WriteCRCD        : SchedWrite; // crc32.d
+def WriteCRCCB       : SchedWrite; // crc32c.b
+def WriteCRCCH       : SchedWrite; // crc32c.h
+def WriteCRCCW       : SchedWrite; // crc32c.w
+def WriteCRCCD       : SchedWrite; // crc32c.d
+
 /// Define scheduler resources associated with use operands.
 
 // Zba extension
 def ReadSHXADD      : SchedRead; // sh1add/sh2add/sh3add
 def ReadSHXADD32    : SchedRead; // sh1add.uw/sh2add.uw/sh3add.uw
 
 // Zbb extension
 def ReadRotateImm   : SchedRead;

 // Zbs extension
 def ReadSingleBit   : SchedRead; // BCLR/BSET/BINV/BEXT
 def ReadSingleBitImm: SchedRead; // BCLRI/BSETI/BINVI/BEXTI
 
 // Zbf extension
 def ReadBFP         : SchedRead; // BFP
 def ReadBFP32       : SchedRead; // BFPW
 
+// Zbp extension
+def ReadORC         : SchedRead; // gorc
+def ReadREV         : SchedRead; // grev
+def ReadORC32       : SchedRead; // gorcw
+def ReadREV32       : SchedRead; // grevw
+def ReadREVImm      : SchedRead; // grevi
+def ReadORCImm      : SchedRead; // groci
+def ReadREVImm32    : SchedRead; // greviw
+def ReadORCImm32    : SchedRead; // gorciw
+def ReadSHFL        : SchedRead; // shfl
+def ReadUNSHFL      : SchedRead; // unshfl
+def ReadSHFL32      : SchedRead; // shflw
+def ReadUNSHFL32    : SchedRead; // unshflw
+def ReadSHFLImm     : SchedRead; // shfli
+def ReadUNSHFLImm   : SchedRead; // unshfli
+def ReadXPERMH      : SchedRead; // xperm.h
+def ReadXPERMW      : SchedRead; // xperm.w
+def ReadPACK        : SchedRead; // pack/packh
+def ReadPACK32      : SchedRead; // packw
+def ReadPACKU       : SchedRead; // packu
+def ReadPACKU32     : SchedRead; // packuw
+
+// Zbr extension
+def ReadCRCB        : SchedRead; // crc32.b
+def ReadCRCH        : SchedRead; // crc32.h
+def ReadCRCW        : SchedRead; // crc32.w
+def ReadCRCD        : SchedRead; // crc32.d
+def ReadCRCCB       : SchedRead; // crc32c.b
+def ReadCRCCH       : SchedRead; // crc32c.h
+def ReadCRCCW       : SchedRead; // crc32c.w
+def ReadCRCCD       : SchedRead; // crc32c.d
+
 /// Define default scheduler resources for B.
 
 multiclass UnsupportedSchedZba {
 let Unsupported = true in {
 def : WriteRes<WriteSHXADD, []>;
 def : WriteRes<WriteSHXADD32, []>;
 
 def : ReadAdvance<ReadSHXADD, 0>;

 let Unsupported = true in {
 def : WriteRes<WriteBFP, []>;
 def : WriteRes<WriteBFP32, []>;
 
 def : ReadAdvance<ReadBFP, 0>;
 def : ReadAdvance<ReadBFP32, 0>;
 }
 }
+
+multiclass UnsupportedSchedZbp {
+let Unsupported = true in {
+def : WriteRes<WriteORC, []>;
+def : WriteRes<WriteREV, []>;
+def : WriteRes<WriteORC32, []>;
+def : WriteRes<WriteREV32, []>;
+def : WriteRes<WriteREVImm, []>;
+def : WriteRes<WriteORCImm, []>;
+def : WriteRes<WriteREVImm32, []>;
+def : WriteRes<WriteORCImm32, []>;
+def : WriteRes<WriteSHFL, []>;
+def : WriteRes<WriteUNSHFL, []>;
+def : WriteRes<WriteSHFL32, []>;
+def : WriteRes<WriteUNSHFL32, []>;
+def : WriteRes<WriteSHFLImm, []>;
+def : WriteRes<WriteUNSHFLImm, []>;
+def : WriteRes<WriteXPERMH, []>;
+def : WriteRes<WriteXPERMW, []>;
+def : WriteRes<WritePACK, []>;
+def : WriteRes<WritePACK32, []>;
+def : WriteRes<WritePACKU, []>;
+def : WriteRes<WritePACKU32, []>;
+
+def : ReadAdvance<ReadORC, 0>;
+def : ReadAdvance<ReadREV, 0>;
+def : ReadAdvance<ReadORC32, 0>;
+def : ReadAdvance<ReadREV32, 0>;
+def : ReadAdvance<ReadREVImm, 0>;
+def : ReadAdvance<ReadORCImm, 0>;
+def : ReadAdvance<ReadREVImm32, 0>;
+def : ReadAdvance<ReadORCImm32, 0>;
+def : ReadAdvance<ReadSHFL, 0>;
+def : ReadAdvance<ReadUNSHFL, 0>;
+def : ReadAdvance<ReadSHFL32, 0>;
+def : ReadAdvance<ReadUNSHFL32, 0>;
+def : ReadAdvance<ReadSHFLImm, 0>;
+def : ReadAdvance<ReadUNSHFLImm, 0>;
+def : ReadAdvance<ReadXPERMH, 0>;
+def : ReadAdvance<ReadXPERMW, 0>;
+def : ReadAdvance<ReadPACK, 0>;
+def : ReadAdvance<ReadPACK32, 0>;
+def : ReadAdvance<ReadPACKU, 0>;
+def : ReadAdvance<ReadPACKU32, 0>;
+}
+}
+
+multiclass UnsupportedSchedZbr {
+let Unsupported = true in {
+def : WriteRes<WriteCRCB, []>;
+def : WriteRes<WriteCRCH, []>;
+def : WriteRes<WriteCRCW, []>;
+def : WriteRes<WriteCRCD, []>;
+def : WriteRes<WriteCRCCB, []>;
+def : WriteRes<WriteCRCCH, []>;
+def : WriteRes<WriteCRCCW, []>;
+def : WriteRes<WriteCRCCD, []>;
+
+def : ReadAdvance<ReadCRCB, 0>;
+def : ReadAdvance<ReadCRCH, 0>;
+def : ReadAdvance<ReadCRCW, 0>;
+def : ReadAdvance<ReadCRCD, 0>;
+def : ReadAdvance<ReadCRCCB, 0>;
+def : ReadAdvance<ReadCRCCH, 0>;
+def : ReadAdvance<ReadCRCCW, 0>;
+def : ReadAdvance<ReadCRCCD, 0>;
+}
+}