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[JITLink] Add R_RISCV_SUB6 relocation
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Authored by StephenFan on Feb 16 2022, 7:44 PM.

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Add R_RISCV_SUB6 relocation

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StephenFan created this revision.Feb 16 2022, 7:44 PM
StephenFan requested review of this revision.Feb 16 2022, 7:44 PM

Hi, StephenFan, I have a question in the inline comment.
Would you be so kind to explain it to us?

llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp
379

Can we safely assumed that, here, the Value is 6 bits?
What if (*FixupPtr & 0xc0) == 0b01000000 and Value == 0b11111111?

jrtc27 added inline comments.Feb 17 2022, 7:24 AM
llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp
377

You need to mask off the upper 2 bits of the value at the address

379

LLD will truncate, not sure if BFD will truncate or error

StephenFan added inline comments.Feb 17 2022, 7:40 AM
llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp
379

You are right, I need to mask off the upper 2 bits of the value at the address and truncate the Value

mask off the upper 2 bits of the value at the address and truncate the Value

fourdim added a comment.EditedFeb 22 2022, 10:36 PM

Please update this file as well and clang format the codes.
llvm/lib/ExecutionEngine/JITLink/riscv.cpp

Address @fourdim 's comments

fourdim accepted this revision.Feb 27 2022, 6:16 PM

LGTM

This revision is now accepted and ready to land.Feb 27 2022, 6:16 PM
This revision was landed with ongoing or failed builds.Feb 28 2022, 9:46 AM
This revision was automatically updated to reflect the committed changes.