[RISCV] Add schedule class for Zbt extension

[Jimerlife]

Summary

Try to add schedule class for Zbt extension

[Jimerlife]

rebase main

[Jimerlife]

ping

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

 // use the mnemonics given to them in the ratified Zbkx extension.
 let Predicates = [HasStdExtZbpOrZbkx] in {
 def XPERM4 : ALU_rr<0b0010100, 0b010, "xperm4">, Sched<[]>;
 def XPERM8 : ALU_rr<0b0010100, 0b100, "xperm8">, Sched<[]>;
 } // Predicates = [HasStdExtZbpOrZbkx]
 
 let Predicates = [HasStdExtZbt] in {
 def CMIX : RVBTernaryR<0b11, 0b001, OPC_OP, "cmix", "$rd, $rs2, $rs1, $rs3">,
-           Sched<[]>;
+           Sched<[WriteCMix, ReadCMix, ReadCMix, ReadCMix]>;
 def CMOV : RVBTernaryR<0b11, 0b101, OPC_OP, "cmov", "$rd, $rs2, $rs1, $rs3">,
-           Sched<[]>;
+           Sched<[WriteCMov, ReadCMov, ReadCMov, ReadCMov]>;
 def FSL  : RVBTernaryR<0b10, 0b001, OPC_OP, "fsl", "$rd, $rs1, $rs3, $rs2">,
-           Sched<[]>;
+           Sched<[WriteFSReg, ReadFSReg, ReadFSReg, ReadFSReg]>;
 def FSR  : RVBTernaryR<0b10, 0b101, OPC_OP, "fsr", "$rd, $rs1, $rs3, $rs2">,
-           Sched<[]>;
+           Sched<[WriteFSReg, ReadFSReg, ReadFSReg, ReadFSReg]>;
 def FSRI : RVBTernaryImm6<0b101, OPC_OP_IMM, "fsri",
-                          "$rd, $rs1, $rs3, $shamt">, Sched<[]>;
+                          "$rd, $rs1, $rs3, $shamt">,
+           Sched<[WriteFSRImm, ReadFSRImm, ReadFSRImm]>;
 } // Predicates = [HasStdExtZbt]
 
 let Predicates = [HasStdExtZbt, IsRV64] in {
 def FSLW  : RVBTernaryR<0b10, 0b001, OPC_OP_32,
-                        "fslw", "$rd, $rs1, $rs3, $rs2">, Sched<[]>;
+                        "fslw", "$rd, $rs1, $rs3, $rs2">,
+            Sched<[WriteFSReg32, ReadFSReg32, ReadFSReg32, ReadFSReg32]>;
 def FSRW  : RVBTernaryR<0b10, 0b101, OPC_OP_32, "fsrw",
-                        "$rd, $rs1, $rs3, $rs2">, Sched<[]>;
+                        "$rd, $rs1, $rs3, $rs2">,
+            Sched<[WriteFSReg32, ReadFSReg32, ReadFSReg32, ReadFSReg32]>;
 def FSRIW : RVBTernaryImm5<0b10, 0b101, OPC_OP_IMM_32,
-                           "fsriw", "$rd, $rs1, $rs3, $shamt">, Sched<[]>;
+                           "fsriw", "$rd, $rs1, $rs3, $shamt">,
+            Sched<[WriteFSRImm32, ReadFSRImm32, ReadFSRImm32]>;
 } // Predicates = [HasStdExtZbt, IsRV64]
 
 let Predicates = [HasStdExtZbb] in {
 def CLZ  : RVBUnary<0b0110000, 0b00000, 0b001, OPC_OP_IMM, "clz">,
            Sched<[WriteCLZ, ReadCLZ]>;
 def CTZ  : RVBUnary<0b0110000, 0b00001, 0b001, OPC_OP_IMM, "ctz">,
            Sched<[WriteCTZ, ReadCTZ]>;
 def CPOP : RVBUnary<0b0110000, 0b00010, 0b001, OPC_OP_IMM, "cpop">,

llvm/lib/Target/RISCV/RISCVSchedRocket.td

 defm : UnsupportedSchedV;
 defm : UnsupportedSchedZba;
 defm : UnsupportedSchedZbb;
 defm : UnsupportedSchedZbc;
 defm : UnsupportedSchedZbs;
 defm : UnsupportedSchedZbe;
 defm : UnsupportedSchedZbf;
 defm : UnsupportedSchedZbm;
+defm : UnsupportedSchedZbt;
 defm : UnsupportedSchedZfh;
 }

llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

 defm : UnsupportedSchedV;
 defm : UnsupportedSchedZba;
 defm : UnsupportedSchedZbb;
 defm : UnsupportedSchedZbc;
 defm : UnsupportedSchedZbs;
 defm : UnsupportedSchedZbe;
 defm : UnsupportedSchedZbf;
 defm : UnsupportedSchedZbm;
+defm : UnsupportedSchedZbt;
 defm : UnsupportedSchedZfh;
 }

llvm/lib/Target/RISCV/RISCVScheduleB.td

 
 // Zbf extension
 def WriteBFP         : SchedWrite; // BFP
 def WriteBFP32       : SchedWrite; // BFPW
 
 // Zbm extension
 def WriteBMatrix     : SchedWrite; // bmator/bmatxor/bmatflip
 
+// Zbt extension
+def WriteCMix        : SchedWrite; // cmix
+def WriteCMov        : SchedWrite; // cmov
+def WriteFSReg       : SchedWrite; // fsl/fsr
+def WriteFSRImm      : SchedWrite; // fsri
+def WriteFSReg32     : SchedWrite; // fslw/fsrw
+def WriteFSRImm32    : SchedWrite; // fsriw
+
 /// Define scheduler resources associated with use operands.
 
 // Zba extension
 def ReadSHXADD      : SchedRead; // sh1add/sh2add/sh3add
 def ReadSHXADD32    : SchedRead; // sh1add.uw/sh2add.uw/sh3add.uw
 
 // Zbb extension
 def ReadRotateImm   : SchedRead;

 
 // Zbf extension
 def ReadBFP         : SchedRead; // BFP
 def ReadBFP32       : SchedRead; // BFPW
 
 // Zbm extension
 def ReadBMatrix     : SchedRead; // bmator/bmatxor/bmatflip
 
+// Zbt extension
+def ReadCMix        : SchedRead; // cmix
+def ReadCMov        : SchedRead; // cmov
+def ReadFSReg       : SchedRead; // fsl/fsr
+def ReadFSRImm      : SchedRead; // fsri
+def ReadFSReg32     : SchedRead; // fslw/fsrw
+def ReadFSRImm32    : SchedRead; // fsriw
+
 /// Define default scheduler resources for B.
 
 multiclass UnsupportedSchedZba {
 let Unsupported = true in {
 def : WriteRes<WriteSHXADD, []>;
 def : WriteRes<WriteSHXADD32, []>;
 
 def : ReadAdvance<ReadSHXADD, 0>;

 
 multiclass UnsupportedSchedZbm {
 let Unsupported = true in {
 def : WriteRes<WriteBMatrix, []>;
 
 def : ReadAdvance<ReadBMatrix, 0>;
 }
 }
+
+multiclass UnsupportedSchedZbt {
+let Unsupported = true in {
+def : WriteRes<WriteCMix, []>;
+def : WriteRes<WriteCMov, []>;
+def : WriteRes<WriteFSReg, []>;
+def : WriteRes<WriteFSRImm, []>;
+def : WriteRes<WriteFSReg32, []>;
+def : WriteRes<WriteFSRImm32, []>;
+
+def : ReadAdvance<ReadCMix, 0>;
+def : ReadAdvance<ReadCMov, 0>;
+def : ReadAdvance<ReadFSReg, 0>;
+def : ReadAdvance<ReadFSRImm, 0>;
+def : ReadAdvance<ReadFSReg32, 0>;
+def : ReadAdvance<ReadFSRImm32, 0>;
+}
+}