[MC] Define and use MCRegisterInfo::regsOverlap

[foad]

Summary

Separate MCRegisterInfo::regsOverlap out from
TargetRegisterInfo::regsOverlap. This is useful in the AMDGPU AsmParser
where we only have access to MCRegisterInfo.

[foad]

llvm/include/llvm/CodeGen/TargetRegisterInfo.h

422

Seems like I need MCRegisterInfo:: here because the overloads can't be disambiguated from the argument type, Register vs MCRegister.

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

3381–3382

I no longer call mc2PseudoReg on the arguments here because I don't understand what it's for. Is that OK?

[MaskRay]

Can you include the motivation to the summary?

llvm/include/llvm/CodeGen/TargetRegisterInfo.h

public:
   ///   MaskB = getSubRegIndexLaneMask(SubB);
   ///
   /// If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by
   /// SubB.
   LaneBitmask getCoveringLanes() const { return CoveringLanes; }
 
   /// Returns true if the two registers are equal or alias each other.
   /// The registers may be virtual registers.
-  bool regsOverlap(Register regA, Register regB) const {
-    if (regA == regB) return true;
-    if (!regA.isPhysical() || !regB.isPhysical())
-      return false;
-
-    // Regunits are numerically ordered. Find a common unit.
-    MCRegUnitIterator RUA(regA.asMCReg(), this);
-    MCRegUnitIterator RUB(regB.asMCReg(), this);
-    do {
-      if (*RUA == *RUB) return true;
-      if (*RUA < *RUB) ++RUA;
-      else             ++RUB;
-    } while (RUA.isValid() && RUB.isValid());
+  bool regsOverlap(Register RegA, Register RegB) const {
+    if (RegA == RegB)
+      return true;
+    if (RegA.isPhysical() && RegB.isPhysical())
+      return MCRegisterInfo::regsOverlap(RegA.asMCReg(), RegB.asMCReg());
     return false;
   }
 
   /// Returns true if Reg contains RegUnit.
   bool hasRegUnit(MCRegister Reg, Register RegUnit) const {
     for (MCRegUnitIterator Units(Reg, this); Units.isValid(); ++Units)
       if (Register(*Units) == RegUnit)
         return true;

llvm/include/llvm/MC/MCRegisterInfo.h

bool isSuperRegisterEq(MCRegister RegA, MCRegister RegB) const {
     return RegA == RegB || isSuperRegister(RegA, RegB);
   }
 
   /// Returns true if RegB is a super-register or sub-register of RegA
   /// or if RegB == RegA.
   bool isSuperOrSubRegisterEq(MCRegister RegA, MCRegister RegB) const {
     return isSubRegisterEq(RegA, RegB) || isSuperRegister(RegA, RegB);
   }
+
+  /// Returns true if the two registers are equal or alias each other.
+  bool regsOverlap(MCRegister RegA, MCRegister RegB) const;
 };
 
 //===----------------------------------------------------------------------===//
 //                          Register List Iterators
 //===----------------------------------------------------------------------===//
 
 // MCRegisterInfo provides lists of super-registers, sub-registers, and
 // aliasing registers. Use these iterator classes to traverse the lists.
MCRegUnitIterator(MCRegister Reg, const MCRegisterInfo *MCRI) {
     init(Reg * Scale, MCRI->DiffLists + Offset);
 
     // That may not be a valid unit, we need to advance by one to get the real
     // unit number. The first differential can be 0 which would normally
     // terminate the list, but since we know every register has at least one
     // unit, we can allow a 0 differential here.
     advance();
   }
+
+  MCRegUnitIterator &operator++() {
+    MCRegisterInfo::DiffListIterator::operator++();
+    return *this;
+  }
 };
 
 /// MCRegUnitMaskIterator enumerates a list of register units and their
 /// associated lane masks for Reg. The register units are in ascending
 /// numerical order.
 class MCRegUnitMaskIterator {
   MCRegUnitIterator RUIter;
   const LaneBitmask *MaskListIter;

llvm/lib/MC/MCRegisterInfo.cpp

if (L2CVRegs.empty())
     report_fatal_error("target does not implement codeview register mapping");
   const DenseMap<MCRegister, int>::const_iterator I = L2CVRegs.find(RegNum);
   if (I == L2CVRegs.end())
     report_fatal_error("unknown codeview register " + (RegNum < getNumRegs()
                                                            ? getName(RegNum)
                                                            : Twine(RegNum)));
   return I->second;
 }
+
+bool MCRegisterInfo::regsOverlap(MCRegister RegA, MCRegister RegB) const {
+  // Regunits are numerically ordered. Find a common unit.
+  MCRegUnitIterator RUA(RegA, this);
+  MCRegUnitIterator RUB(RegB, this);
+  do {
+    if (*RUA == *RUB)
+      return true;
+  } while (*RUA < *RUB ? (++RUA).isValid() : (++RUB).isValid());
+  return false;
+}

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

AMDGPUAsmParser::validateEarlyClobberLimitations(const MCInst &Inst,
 
   const int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
   const int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
   const int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
 
   assert(DstIdx != -1);
   const MCOperand &Dst = Inst.getOperand(DstIdx);
   assert(Dst.isReg());
-  const unsigned DstReg = mc2PseudoReg(Dst.getReg());
 
   const int SrcIndices[] = { Src0Idx, Src1Idx, Src2Idx };
 
   for (int SrcIdx : SrcIndices) {
     if (SrcIdx == -1) break;
     const MCOperand &Src = Inst.getOperand(SrcIdx);
     if (Src.isReg()) {
+      if (TRI->regsOverlap(Dst.getReg(), Src.getReg())) {
         const unsigned SrcReg = mc2PseudoReg(Src.getReg());
-      if (isRegIntersect(DstReg, SrcReg, TRI)) {
         Error(getRegLoc(SrcReg, Operands),
           "destination must be different than all sources");
         return false;
       }
     }
   }
 
   return true;
bool AMDGPUAsmParser::validateMFMA(const MCInst &Inst,
   MCRegister DstReg = Inst.getOperand(0).getReg();
   if (Src2Reg == DstReg)
     return true;
 
   const MCRegisterInfo *TRI = getContext().getRegisterInfo();
   if (TRI->getRegClass(Desc.OpInfo[0].RegClass).getSizeInBits() <= 128)
     return true;
 
-  if (isRegIntersect(Src2Reg, DstReg, TRI)) {
+  if (TRI->regsOverlap(Src2Reg, DstReg)) {
     Error(getRegLoc(mc2PseudoReg(Src2Reg), Operands),
           "source 2 operand must not partially overlap with dst");
     return false;
   }
 
   return true;
 }
 

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h

 bool isGFX10_BEncoding(const MCSubtargetInfo &STI);
 bool hasGFX10_3Insts(const MCSubtargetInfo &STI);
 bool isGFX90A(const MCSubtargetInfo &STI);
 bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI);
 
 /// Is Reg - scalar register
 bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
 
-/// Is there any intersection between registers
-bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI);
-
 /// If \p Reg is a pseudo reg, return the correct hardware register given
 /// \p STI otherwise return \p Reg.
 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
 
 /// Convert hardware register \p Reg to a pseudo register
 LLVM_READNONE
 unsigned mc2PseudoReg(unsigned Reg);
 

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

 
 bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI) {
   const MCRegisterClass SGPRClass = TRI->getRegClass(AMDGPU::SReg_32RegClassID);
   const unsigned FirstSubReg = TRI->getSubReg(Reg, AMDGPU::sub0);
   return SGPRClass.contains(FirstSubReg != 0 ? FirstSubReg : Reg) ||
     Reg == AMDGPU::SCC;
 }
 
-bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI) {
-  for (MCRegAliasIterator R(Reg0, TRI, true); R.isValid(); ++R) {
-    if (*R == Reg1) return true;
-  }
-  return false;
-}
-
 #define MAP_REG2REG \
   using namespace AMDGPU; \
   switch(Reg) { \
   default: return Reg; \
   CASE_CI_VI(FLAT_SCR) \
   CASE_CI_VI(FLAT_SCR_LO) \
   CASE_CI_VI(FLAT_SCR_HI) \
   CASE_VI_GFX9PLUS(TTMP0) \