[DAGCombine] Add simple folds for SSHLSAT/USHLSAT

[bjope]

Summary

Do "simplifyShift" and "FoldConstantArithmetic" folds for the SSHLSAT
and USHLSAT DAG nodes.

This for example include folds such as:

(shlsat 0, x) -> 0
(shlsat x, 0) -> x
(shlsat c1, c2) -> c3

[RKSimon]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

9356

Do you have any test coverage for undef/poison/outofrangeamt operands - that's mainly what simplifyShift handles?

[bjope]

Added test cases for undef/poison/out-of-bounds-shamt:

(shlsat undef/poison, x) -> 0
(shlsat x, undef/poison) -> undef
(shlsat x, too_large_shamt) -> undef

[RKSimon]

LGTM - please can you pre-commit the tests and then rebase so that the patch commit shows the codegen diffs

[bjope]

In D118603#3285506, @RKSimon wrote:

LGTM - please can you pre-commit the tests and then rebase so that the patch commit shows the codegen diffs

Ok, thanks! I did pre-committ the tests before landing.

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

private:
     SDValue visitOR(SDNode *N);
     SDValue visitORLike(SDValue N0, SDValue N1, SDNode *N);
     SDValue visitXOR(SDNode *N);
     SDValue SimplifyVBinOp(SDNode *N, const SDLoc &DL);
     SDValue visitSHL(SDNode *N);
     SDValue visitSRA(SDNode *N);
     SDValue visitSRL(SDNode *N);
     SDValue visitFunnelShift(SDNode *N);
+    SDValue visitSHLSAT(SDNode *N);
     SDValue visitRotate(SDNode *N);
     SDValue visitABS(SDNode *N);
     SDValue visitBSWAP(SDNode *N);
     SDValue visitBITREVERSE(SDNode *N);
     SDValue visitCTLZ(SDNode *N);
     SDValue visitCTLZ_ZERO_UNDEF(SDNode *N);
     SDValue visitCTTZ(SDNode *N);
     SDValue visitCTTZ_ZERO_UNDEF(SDNode *N);
SDValue DAGCombiner::visit(SDNode *N) {
   case ISD::XOR:                return visitXOR(N);
   case ISD::SHL:                return visitSHL(N);
   case ISD::SRA:                return visitSRA(N);
   case ISD::SRL:                return visitSRL(N);
   case ISD::ROTR:
   case ISD::ROTL:               return visitRotate(N);
   case ISD::FSHL:
   case ISD::FSHR:               return visitFunnelShift(N);
+  case ISD::SSHLSAT:
+  case ISD::USHLSAT:            return visitSHLSAT(N);
   case ISD::ABS:                return visitABS(N);
   case ISD::BSWAP:              return visitBSWAP(N);
   case ISD::BITREVERSE:         return visitBITREVERSE(N);
   case ISD::CTLZ:               return visitCTLZ(N);
   case ISD::CTLZ_ZERO_UNDEF:    return visitCTLZ_ZERO_UNDEF(N);
   case ISD::CTTZ:               return visitCTTZ(N);
   case ISD::CTTZ_ZERO_UNDEF:    return visitCTTZ_ZERO_UNDEF(N);
   case ISD::CTPOP:              return visitCTPOP(N);
SDValue DAGCombiner::visitFunnelShift(SDNode *N) {
 
   // Simplify, based on bits shifted out of N0/N1.
   if (SimplifyDemandedBits(SDValue(N, 0)))
     return SDValue(N, 0);
 
   return SDValue();
 }
 
+SDValue DAGCombiner::visitSHLSAT(SDNode *N) {
+  SDValue N0 = N->getOperand(0);
+  SDValue N1 = N->getOperand(1);
+  if (SDValue V = DAG.simplifyShift(N0, N1))
+    return V;
+
+  EVT VT = N0.getValueType();
+
+  // fold (*shlsat c1, c2) -> c1<<c2
+  if (SDValue C =
+          DAG.FoldConstantArithmetic(N->getOpcode(), SDLoc(N), VT, {N0, N1}))
+    return C;
+
+  return SDValue();
+}
+
 // Given a ABS node, detect the following pattern:
 // (ABS (SUB (EXTEND a), (EXTEND b))).
 // Generates UABD/SABD instruction.
 static SDValue combineABSToABD(SDNode *N, SelectionDAG &DAG,
                                const TargetLowering &TLI) {
   SDValue AbsOp1 = N->getOperand(0);
   SDValue Op0, Op1;
 

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

static llvm::Optional<APInt> FoldValue(unsigned Opcode, const APInt &C1,
   case ISD::SMIN: return C1.sle(C2) ? C1 : C2;
   case ISD::SMAX: return C1.sge(C2) ? C1 : C2;
   case ISD::UMIN: return C1.ule(C2) ? C1 : C2;
   case ISD::UMAX: return C1.uge(C2) ? C1 : C2;
   case ISD::SADDSAT: return C1.sadd_sat(C2);
   case ISD::UADDSAT: return C1.uadd_sat(C2);
   case ISD::SSUBSAT: return C1.ssub_sat(C2);
   case ISD::USUBSAT: return C1.usub_sat(C2);
+  case ISD::SSHLSAT: return C1.sshl_sat(C2);
+  case ISD::USHLSAT: return C1.ushl_sat(C2);
   case ISD::UDIV:
     if (!C2.getBoolValue())
       break;
     return C1.udiv(C2);
   case ISD::UREM:
     if (!C2.getBoolValue())
       break;
     return C1.urem(C2);

llvm/test/CodeGen/AArch64/sshl_sat.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
 
 declare i16 @llvm.sshl.sat.i16(i16, i16)
 declare <4 x i16> @llvm.sshl.sat.v4i16(<4 x i16>, <4 x i16>)
 
 ; fold (shlsat undef, x) -> 0
 define i16 @combine_shl_undef(i16 %x, i16 %y) nounwind {
 ; CHECK-LABEL: combine_shl_undef:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, wzr
-; CHECK-NEXT:    mov w9, #-2147483648
-; CHECK-NEXT:    cmp w8, #0
-; CHECK-NEXT:    cinv w9, w9, ge
-; CHECK-NEXT:    csel w8, w9, w8, ne
-; CHECK-NEXT:    asr w0, w8, #16
+; CHECK-NEXT:    mov w0, wzr
 ; CHECK-NEXT:    ret
   %tmp = call i16 @llvm.sshl.sat.i16(i16 undef, i16 %y)
   ret i16 %tmp
 }
 
 ; fold (shlsat x, undef) -> undef
 define i16 @combine_shl_by_undef(i16 %x, i16 %y) nounwind {
 ; CHECK-LABEL: combine_shl_by_undef:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    lsl w9, w0, #16
-; CHECK-NEXT:    mov w8, #-2147483648
-; CHECK-NEXT:    cmp w9, #0
-; CHECK-NEXT:    cinv w8, w8, ge
-; CHECK-NEXT:    cmp w9, w9
-; CHECK-NEXT:    csel w8, w8, w9, ne
-; CHECK-NEXT:    asr w0, w8, #16
 ; CHECK-NEXT:    ret
   %tmp = call i16 @llvm.sshl.sat.i16(i16 %x, i16 undef)
   ret i16 %tmp
 }
 
 ; fold (shlsat poison, x) -> 0
 define i16 @combine_shl_poison(i16 %x, i16 %y) nounwind {
 ; CHECK-LABEL: combine_shl_poison:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, wzr
-; CHECK-NEXT:    mov w9, #-2147483648
-; CHECK-NEXT:    cmp w8, #0
-; CHECK-NEXT:    cinv w9, w9, ge
-; CHECK-NEXT:    csel w8, w9, w8, ne
-; CHECK-NEXT:    asr w0, w8, #16
+; CHECK-NEXT:    mov w0, wzr
 ; CHECK-NEXT:    ret
   %tmp = call i16 @llvm.sshl.sat.i16(i16 poison, i16 %y)
   ret i16 %tmp
 }
 
 ; fold (shlsat x, poison) -> undef
 define i16 @combine_shl_by_poison(i16 %x, i16 %y) nounwind {
 ; CHECK-LABEL: combine_shl_by_poison:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    lsl w9, w0, #16
-; CHECK-NEXT:    mov w8, #-2147483648
-; CHECK-NEXT:    cmp w9, #0
-; CHECK-NEXT:    cinv w8, w8, ge
-; CHECK-NEXT:    cmp w9, w9
-; CHECK-NEXT:    csel w8, w8, w9, ne
-; CHECK-NEXT:    asr w0, w8, #16
 ; CHECK-NEXT:    ret
   %tmp = call i16 @llvm.sshl.sat.i16(i16 %x, i16 poison)
   ret i16 %tmp
 }
 
 ; fold (shlsat x, bitwidth) -> undef
 define i16 @combine_shl_by_bitwidth(i16 %x, i16 %y) nounwind {
 ; CHECK-LABEL: combine_shl_by_bitwidth:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    lsl w9, w0, #16
-; CHECK-NEXT:    mov w8, #-2147483648
-; CHECK-NEXT:    cmp w9, #0
-; CHECK-NEXT:    cinv w8, w8, ge
-; CHECK-NEXT:    csel w8, w8, wzr, ne
-; CHECK-NEXT:    asr w0, w8, #16
 ; CHECK-NEXT:    ret
   %tmp = call i16 @llvm.sshl.sat.i16(i16 %x, i16 16)
   ret i16 %tmp
 }
 
 ; fold (shlsat 0, x) -> 0
 define i16 @combine_shl_zero(i16 %x, i16 %y) nounwind {
 ; CHECK-LABEL: combine_shl_zero:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, wzr
-; CHECK-NEXT:    mov w9, #-2147483648
-; CHECK-NEXT:    cmp w8, #0
-; CHECK-NEXT:    cinv w9, w9, ge
-; CHECK-NEXT:    csel w8, w9, w8, ne
-; CHECK-NEXT:    asr w0, w8, #16
+; CHECK-NEXT:    mov w0, wzr
 ; CHECK-NEXT:    ret
   %tmp = call i16 @llvm.sshl.sat.i16(i16 0, i16 %y)
   ret i16 %tmp
 }
 
 ; fold (shlsat x, 0) -> x
 define i16 @combine_shlsat_by_zero(i16 %x, i16 %y) nounwind {
 ; CHECK-LABEL: combine_shlsat_by_zero:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    lsl w9, w0, #16
-; CHECK-NEXT:    mov w8, #-2147483648
-; CHECK-NEXT:    cmp w9, #0
-; CHECK-NEXT:    cinv w8, w8, ge
-; CHECK-NEXT:    cmp w9, w9
-; CHECK-NEXT:    csel w8, w8, w9, ne
-; CHECK-NEXT:    asr w0, w8, #16
 ; CHECK-NEXT:    ret
   %tmp = call i16 @llvm.sshl.sat.i16(i16 %x, i16 0)
   ret i16 %tmp
 }
 
 ; fold (shlsat c1, c2) -> c3
 define i16 @combine_shlsat_constfold(i16 %x, i16 %y) nounwind {
 ; CHECK-LABEL: combine_shlsat_constfold:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #524288
-; CHECK-NEXT:    mov w9, #-2147483648
-; CHECK-NEXT:    cmp w8, #0
-; CHECK-NEXT:    cinv w9, w9, ge
-; CHECK-NEXT:    cmp w8, #128, lsl #12 // =524288
-; CHECK-NEXT:    mov w8, #2097152
-; CHECK-NEXT:    csel w8, w9, w8, ne
-; CHECK-NEXT:    asr w0, w8, #16
+; CHECK-NEXT:    mov w0, #32
 ; CHECK-NEXT:    ret
   %tmp = call i16 @llvm.sshl.sat.i16(i16 8, i16 2)
   ret i16 %tmp
 }
 
 ; fold (shlsat c1, c2) -> sat max
 define i16 @combine_shlsat_satmax(i16 %x, i16 %y) nounwind {
 ; CHECK-LABEL: combine_shlsat_satmax:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #524288
-; CHECK-NEXT:    cmp w8, #0
-; CHECK-NEXT:    mov w8, #-2147483648
-; CHECK-NEXT:    cinv w8, w8, ge
-; CHECK-NEXT:    csel w8, w8, wzr, ne
-; CHECK-NEXT:    asr w0, w8, #16
+; CHECK-NEXT:    mov w0, #32767
 ; CHECK-NEXT:    ret
   %tmp = call i16 @llvm.sshl.sat.i16(i16 8, i16 15)
   ret i16 %tmp
 }
 
 ; fold (shlsat c1, c2) -> sat min
 define i16 @combine_shlsat_satmin(i16 %x, i16 %y) nounwind {
 ; CHECK-LABEL: combine_shlsat_satmin:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-524288
-; CHECK-NEXT:    cmp w8, #0
-; CHECK-NEXT:    mov w8, #-2147483648
-; CHECK-NEXT:    cinv w8, w8, ge
-; CHECK-NEXT:    csel w8, w8, wzr, ne
-; CHECK-NEXT:    asr w0, w8, #16
+; CHECK-NEXT:    mov w0, #32768
 ; CHECK-NEXT:    ret
   %tmp = call i16 @llvm.sshl.sat.i16(i16 -8, i16 15)
   ret i16 %tmp
 }
 
 declare void @sink4xi16(i16, i16, i16, i16)
 
 ; fold (shlsat c1, c2) -> c3 , c1/c2/c3 being vectors
 define void @combine_shlsat_vector() nounwind {
 ; CHECK-LABEL: combine_shlsat_vector:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT:    mov w8, #524288
-; CHECK-NEXT:    mov w9, #-2147483648
-; CHECK-NEXT:    cmp w8, #0
-; CHECK-NEXT:    cinv w10, w9, ge
-; CHECK-NEXT:    csel w11, w10, wzr, ne
-; CHECK-NEXT:    cmp w8, #128, lsl #12 // =524288
-; CHECK-NEXT:    mov w8, #2097152
-; CHECK-NEXT:    asr w11, w11, #16
-; CHECK-NEXT:    csel w8, w10, w8, ne
-; CHECK-NEXT:    mov w10, #-524288
-; CHECK-NEXT:    asr w8, w8, #16
-; CHECK-NEXT:    cmp w10, #0
-; CHECK-NEXT:    cinv w9, w9, ge
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    csel w8, w9, wzr, ne
-; CHECK-NEXT:    cmn w10, #128, lsl #12 // =524288
-; CHECK-NEXT:    mov w10, #-2097152
-; CHECK-NEXT:    csel w9, w9, w10, ne
-; CHECK-NEXT:    asr w8, w8, #16
-; CHECK-NEXT:    mov v0.h[1], w11
-; CHECK-NEXT:    asr w9, w9, #16
-; CHECK-NEXT:    mov v0.h[2], w9
-; CHECK-NEXT:    mov v0.h[3], w8
-; CHECK-NEXT:    umov w0, v0.h[0]
-; CHECK-NEXT:    umov w1, v0.h[1]
-; CHECK-NEXT:    umov w2, v0.h[2]
-; CHECK-NEXT:    umov w3, v0.h[3]
+; CHECK-NEXT:    mov w0, #32
+; CHECK-NEXT:    mov w1, #32767
+; CHECK-NEXT:    mov w2, #65504
+; CHECK-NEXT:    mov w3, #32768
 ; CHECK-NEXT:    bl sink4xi16
 ; CHECK-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %tmp = call <4 x i16> @llvm.sshl.sat.v4i16(
                           <4 x i16><i16 8, i16 8, i16 -8, i16 -8>,
                           <4 x i16><i16 2, i16 15, i16 2, i16 15>)
   ; Pass elements as arguments in a call to get CHECK statements that verify
   ; the constant folding.
   %e0 = extractelement <4 x i16> %tmp, i16 0
   %e1 = extractelement <4 x i16> %tmp, i16 1
   %e2 = extractelement <4 x i16> %tmp, i16 2
   %e3 = extractelement <4 x i16> %tmp, i16 3
   call void @sink4xi16(i16 %e0, i16 %e1, i16 %e2, i16 %e3)
   ret void
 }

llvm/test/CodeGen/AArch64/ushl_sat.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
 
 declare i16 @llvm.ushl.sat.i16(i16, i16)
 declare <2 x i16> @llvm.ushl.sat.v2i16(<2 x i16>, <2 x i16>)
 
 ; fold (shlsat undef, x) -> 0
 define i16 @combine_shl_undef(i16 %x, i16 %y) nounwind {
 ; CHECK-LABEL: combine_shl_undef:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, wzr
-; CHECK-NEXT:    cmp w8, #0
-; CHECK-NEXT:    csetm w8, ne
-; CHECK-NEXT:    lsr w0, w8, #16
+; CHECK-NEXT:    mov w0, wzr
 ; CHECK-NEXT:    ret
   %tmp = call i16 @llvm.ushl.sat.i16(i16 undef, i16 %y)
   ret i16 %tmp
 }
 
 ; fold (shlsat x, undef) -> undef
 define i16 @combine_shl_by_undef(i16 %x, i16 %y) nounwind {
 ; CHECK-LABEL: combine_shl_by_undef:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    lsl w8, w0, #16
-; CHECK-NEXT:    cmp w8, w8
-; CHECK-NEXT:    csinv w8, w8, wzr, eq
-; CHECK-NEXT:    lsr w0, w8, #16
 ; CHECK-NEXT:    ret
   %tmp = call i16 @llvm.ushl.sat.i16(i16 %x, i16 undef)
   ret i16 %tmp
 }
 
 ; fold (shlsat poison, x) -> 0
 define i16 @combine_shl_poison(i16 %x, i16 %y) nounwind {
 ; CHECK-LABEL: combine_shl_poison:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, wzr
-; CHECK-NEXT:    cmp w8, #0
-; CHECK-NEXT:    csetm w8, ne
-; CHECK-NEXT:    lsr w0, w8, #16
+; CHECK-NEXT:    mov w0, wzr
 ; CHECK-NEXT:    ret
   %tmp = call i16 @llvm.ushl.sat.i16(i16 poison, i16 %y)
   ret i16 %tmp
 }
 
 ; fold (shlsat x, poison) -> undef
 define i16 @combine_shl_by_poison(i16 %x, i16 %y) nounwind {
 ; CHECK-LABEL: combine_shl_by_poison:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    lsl w8, w0, #16
-; CHECK-NEXT:    cmp w8, w8
-; CHECK-NEXT:    csinv w8, w8, wzr, eq
-; CHECK-NEXT:    lsr w0, w8, #16
 ; CHECK-NEXT:    ret
   %tmp = call i16 @llvm.ushl.sat.i16(i16 %x, i16 poison)
   ret i16 %tmp
 }
 
 ; fold (shlsat x, bitwidth) -> undef
 define i16 @combine_shl_by_bitwidth(i16 %x, i16 %y) nounwind {
 ; CHECK-LABEL: combine_shl_by_bitwidth:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    lsl w8, w0, #16
-; CHECK-NEXT:    cmp w8, #0
-; CHECK-NEXT:    csetm w8, ne
-; CHECK-NEXT:    lsr w0, w8, #16
 ; CHECK-NEXT:    ret
   %tmp = call i16 @llvm.ushl.sat.i16(i16 %x, i16 16)
   ret i16 %tmp
 }
 
 ; fold (ushlsat 0, x) -> 0
 define i16 @combine_shl_zero(i16 %x, i16 %y) nounwind {
 ; CHECK-LABEL: combine_shl_zero:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, wzr
-; CHECK-NEXT:    cmp w8, #0
-; CHECK-NEXT:    csetm w8, ne
-; CHECK-NEXT:    lsr w0, w8, #16
+; CHECK-NEXT:    mov w0, wzr
 ; CHECK-NEXT:    ret
   %tmp = call i16 @llvm.ushl.sat.i16(i16 0, i16 %y)
   ret i16 %tmp
 }
 
 ; fold (ushlsat x, 0) -> x
 define i16 @combine_shlsat_by_zero(i16 %x, i16 %y) nounwind {
 ; CHECK-LABEL: combine_shlsat_by_zero:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    lsl w8, w0, #16
-; CHECK-NEXT:    cmp w8, w8
-; CHECK-NEXT:    csinv w8, w8, wzr, eq
-; CHECK-NEXT:    lsr w0, w8, #16
 ; CHECK-NEXT:    ret
   %tmp = call i16 @llvm.ushl.sat.i16(i16 %x, i16 0)
   ret i16 %tmp
 }
 
 ; fold (ushlsat c1, c2) -> c3
 define i16 @combine_shlsat_constfold(i16 %x, i16 %y) nounwind {
 ; CHECK-LABEL: combine_shlsat_constfold:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #524288
-; CHECK-NEXT:    cmp w8, #128, lsl #12 // =524288
-; CHECK-NEXT:    mov w8, #2097152
-; CHECK-NEXT:    csinv w8, w8, wzr, eq
-; CHECK-NEXT:    lsr w0, w8, #16
+; CHECK-NEXT:    mov w0, #32
 ; CHECK-NEXT:    ret
   %tmp = call i16 @llvm.ushl.sat.i16(i16 8, i16 2)
   ret i16 %tmp
 }
 
 ; fold (ushlsat c1, c2) -> sat max
 define i16 @combine_shlsat_satmax(i16 %x, i16 %y) nounwind {
 ; CHECK-LABEL: combine_shlsat_satmax:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #524288
-; CHECK-NEXT:    cmp w8, #0
-; CHECK-NEXT:    csetm w8, ne
-; CHECK-NEXT:    lsr w0, w8, #16
+; CHECK-NEXT:    mov w0, #65535
 ; CHECK-NEXT:    ret
   %tmp = call i16 @llvm.ushl.sat.i16(i16 8, i16 15)
   ret i16 %tmp
 }
 
 
 declare void @sink2xi16(i16, i16)
 
 ; fold (ushlsat c1, c2) -> c3 , c1/c2/c3 being vectors
 define void @combine_shlsat_vector() nounwind {
 ; CHECK-LABEL: combine_shlsat_vector:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT:    mov w8, #524288
-; CHECK-NEXT:    mov w9, #2097152
-; CHECK-NEXT:    cmp w8, #128, lsl #12 // =524288
-; CHECK-NEXT:    csinv w9, w9, wzr, eq
-; CHECK-NEXT:    cmp w8, #0
-; CHECK-NEXT:    csetm w8, ne
-; CHECK-NEXT:    fmov s0, w9
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    ushr v0.2s, v0.2s, #16
-; CHECK-NEXT:    mov w1, v0.s[1]
-; CHECK-NEXT:    fmov w0, s0
+; CHECK-NEXT:    mov w0, #32
+; CHECK-NEXT:    mov w1, #65535
 ; CHECK-NEXT:    bl sink2xi16
 ; CHECK-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %tmp = call <2 x i16> @llvm.ushl.sat.v2i16(<2 x i16><i16 8, i16 8>,
                                              <2 x i16><i16 2, i16 15>)
   ; Pass elements as arguments in a call to get CHECK statements that verify
   ; the constant folding.
   %e0 = extractelement <2 x i16> %tmp, i16 0
   %e1 = extractelement <2 x i16> %tmp, i16 1
   call void @sink2xi16(i16 %e0, i16 %e1)
   ret void
 }