[AMDGPU] Add test for a problem with noclobber metadata

[foad]

Summary

If AMDGPUAnnotateUniformValues finds a load from a uniform pointer with
no potentially clobbering stores between the kernel entry point and the
load instruction, it adds noclobber metadata to the *address*. This is
unsafe because it can get applied to other loads in the same which do
have aliasing stores.

[foad]

Found by inspection but I think this is a real bug isn't it? I guess the fix is to put the noclobber metadata on the load instruction, not on the pointer, but then how do you get at it during instruction selection?

[rampitec]

Ugh... These are different arguments which may alias. I guess you could do the same with a single gep being reused for loads and stores...

[foad]

In D118458#3280607, @rampitec wrote:

Ugh... These are different arguments which may alias. I guess you could do the same with a single gep being reused for loads and stores...

Right, but if a store is followed by a load from the exact same address, I thought some other pass might optimise the load away by replacing it with the value that was stored.

[rampitec]

In D118458#3283506, @foad wrote:

In D118458#3280607, @rampitec wrote:

Ugh... These are different arguments which may alias. I guess you could do the same with a single gep being reused for loads and stores...

Right, but if a store is followed by a load from the exact same address, I thought some other pass might optimise the load away by replacing it with the value that was stored.

That's a slippery ground. It should be better to find a way to attach it right to a load.

[rampitec]

We could implement TLI::getTargetMMOFlags() and set a target flag on the MMO.

[foad]

In D118458#3288991, @rampitec wrote:

We could implement TLI::getTargetMMOFlags() and set a target flag on the MMO.

Good idea! D118775.

llvm/test/CodeGen/AMDGPU/global_smrd.ll

bb:
   %tmp10 = getelementptr inbounds float, float addrspace(1)* %arg, i64 3
   %tmp11 = load float, float addrspace(1)* %tmp10, align 4, !tbaa !8
   %tmp12 = fadd float %tmp9, %tmp11
   %tmp13 = getelementptr inbounds float, float addrspace(1)* %arg1
   store float %tmp12, float addrspace(1)* %tmp13, align 4, !tbaa !8
   ret void
 }
 
+; uniform loads before and after an aliasing store
+; FIXME: The second load should not be converted to an SMEM load!
+; CHECK-LABEL: @uniform_load_store_load
+; CHECK: s_load_dwordx4
+; CHECK: s_load_dword
+; CHECK: flat_store_dword
+; CHECK: s_load_dword
+; CHECK: flat_store_dword
+
+define amdgpu_kernel void @uniform_load_store_load(float addrspace(1)* %arg0, float addrspace(1)* %arg1) {
+bb:
+  %tmp2 = load float, float addrspace(1)* %arg0, !tbaa !8
+  store float %tmp2, float addrspace(1)* %arg1, !tbaa !8
+  %tmp3 = load float, float addrspace(1)* %arg0, !tbaa !8
+  store float %tmp3, float addrspace(1)* %arg1, !tbaa !8
+  ret void
+}
+
 ; non-uniform loads
 ; CHECK-LABEL: @non-uniform_load
 ; CHECK: flat_load_dword
 ; CHECK-NOT: s_load_dwordx4
 
 define amdgpu_kernel void @non-uniform_load(float addrspace(1)* %arg, [8 x i32], float addrspace(1)* %arg1) #0 {
 bb:
   %tmp = call i32 @llvm.amdgcn.workitem.id.x() #1