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Differential D118045

[AArch64] Exclude optional features from HasV8_0rOps.
ClosedPublic

Authored by simon_tatham on Jan 24 2022, 7:23 AM.

Details

Reviewers
SjoerdMeijer
miyuki
dmgreen
MarkMurrayARM
pbarrio
chill
Commits
rGf302e0b5dd40: [AArch64] Exclude optional features from HasV8_0rOps.
Summary

The following SubtargetFeatures are removed from the definition of
HasV8_0rOps, on the grounds that they are optional in Armv8.4-A, and
therefore (by the definition of Armv8.0-R) also optional in v8.0-R:

  • performance monitoring: FeaturePerfMon
  • cryptography: FeatureSM4 and FeatureSHA3
  • half-precision FP: FeatureFullFP16, FeatureFP16FML
  • speculation control: FeatureSSBS, FeaturePredRes, FeatureSB, FeatureSpecRestrict

This isn't the full set of features that are listed as optional in the
spec. FeatureCCIDX and FeatureTRACEV8_4 are also optional. But LLVM
includes those in HasV8_3aOps and HasV8_4aOps respectively (I think on
the grounds that the system registers they enable are useful to be
able to access after a runtime check), and so for consistency, I've
left those in HasV8_0rOps too.

After this commit, HasV8_0rOps is a strict subset of HasV8_4aOps (but
missing features that are not in Armv8.0-R at all).

The definition of Cortex-R82 is correspondingly updated to add most of
the features that I've removed from base Armv8.0-R (with the exception
of the cryptography ones), since that particular implementation of
v8.0-R does have them.

Diff Detail

Unit TestsFailed

TimeTest
500 msx64 debian > Profile-x86_64.Linux::instrprof-debug-info-correlate.c
35,170 msx64 debian > libFuzzer.libFuzzer::fork.test
5,640 msx64 debian > libarcher.races::critical-unrelated.c
6,670 msx64 debian > libarcher.races::lock-nested-unrelated.c
6,210 msx64 debian > libarcher.races::lock-unrelated.c
View Full Test Results (11 Failed)

Event Timeline

simon_tatham created this revision.Jan 24 2022, 7:23 AM
Herald added subscribers: hiraditya, kristof.beyls. · View Herald TranscriptJan 24 2022, 7:23 AM
simon_tatham requested review of this revision.Jan 24 2022, 7:23 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 24 2022, 7:23 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
Harbormaster completed remote builds in B145233: Diff 402520.Jan 24 2022, 1:56 PM
dmgreen accepted this revision.Jan 25 2022, 2:02 AM

Sounds good to me. SHA3 and SM4 are not even present in Cortex-R82!

This revision is now accepted and ready to land.Jan 25 2022, 2:02 AM
This revision was landed with ongoing or failed builds.Jan 25 2022, 2:55 AM
Closed by commit rGf302e0b5dd40: [AArch64] Exclude optional features from HasV8_0rOps. (authored by simon_tatham). · Explain Why
This revision was automatically updated to reflect the committed changes.
simon_tatham added a commit: rGf302e0b5dd40: [AArch64] Exclude optional features from HasV8_0rOps..
simon_tatham mentioned this in D120830: [AArch64] Move FeatureSpecRestrict into core 8.0-R architecture..Mar 2 2022, 9:33 AM
simon_tatham mentioned this in rG54dafd38c5c6: [AArch64] Move FeatureSpecRestrict into core 8.0-R architecture..Mar 7 2022, 7:55 AM

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
13 lines
test/
MC/
AArch64/
3 lines
Disassembler/
AArch64/
3 lines
2 lines
2 lines
2 lines
1 line

Diff 402520

llvm/lib/Target/AArch64/AArch64.td

Show First 20 Lines • Show All 522 Lines • ▼ Show 20 Linesdef HasV9_3aOps : SubtargetFeature<
"v9.3a", "HasV9_3aOps", "true", "Support ARM v9.3a instructions", "v9.3a", "HasV9_3aOps", "true", "Support ARM v9.3a instructions",
[HasV8_8aOps, HasV9_2aOps]>; [HasV8_8aOps, HasV9_2aOps]>;
def HasV8_0rOps : SubtargetFeature< def HasV8_0rOps : SubtargetFeature<
"v8r", "HasV8_0rOps", "true", "Support ARM v8r instructions", "v8r", "HasV8_0rOps", "true", "Support ARM v8r instructions",
[//v8.1 [//v8.1
FeatureCRC, FeaturePAN, FeatureRDM, FeatureLSE, FeatureCONTEXTIDREL2, FeatureCRC, FeaturePAN, FeatureRDM, FeatureLSE, FeatureCONTEXTIDREL2,
//v8.2 //v8.2
FeaturePerfMon, FeatureRAS, FeaturePsUAO, FeatureSM4, FeatureRAS, FeaturePsUAO, FeatureCCPP, FeaturePAN_RWV,
FeatureSHA3, FeatureCCPP, FeatureFullFP16, FeaturePAN_RWV,
//v8.3 //v8.3
FeatureComplxNum, FeatureCCIDX, FeatureJS, FeatureComplxNum, FeatureCCIDX, FeatureJS,
FeaturePAuth, FeatureRCPC, FeaturePAuth, FeatureRCPC,
//v8.4 //v8.4
FeatureDotProd, FeatureFP16FML, FeatureTRACEV8_4, FeatureDotProd, FeatureTRACEV8_4, FeatureTLB_RMI,
FeatureTLB_RMI, FeatureFlagM, FeatureDIT, FeatureSEL2, FeatureRCPC_IMMO, FeatureFlagM, FeatureDIT, FeatureSEL2, FeatureRCPC_IMMO]>;
//v8.5
FeatureSSBS, FeaturePredRes, FeatureSB, FeatureSpecRestrict]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Register File Description // Register File Description
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
include "AArch64RegisterInfo.td" include "AArch64RegisterInfo.td"
include "AArch64RegisterBanks.td" include "AArch64RegisterBanks.td"
include "AArch64CallingConvention.td" include "AArch64CallingConvention.td"
▲ Show 20 Lines • Show All 415 Lines • ▼ Show 20 Linesdef ProcessorFeatures {
list<SubtargetFeature> A78C = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, list<SubtargetFeature> A78C = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
FeatureNEON, FeatureFullFP16, FeatureDotProd, FeatureNEON, FeatureFullFP16, FeatureDotProd,
FeatureFlagM, FeatureFP16FML, FeaturePAuth, FeatureFlagM, FeatureFP16FML, FeaturePAuth,
FeaturePerfMon, FeatureRCPC, FeatureSPE, FeaturePerfMon, FeatureRCPC, FeatureSPE,
FeatureSSBS]; FeatureSSBS];
list<SubtargetFeature> A710 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon, list<SubtargetFeature> A710 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon,
FeatureETE, FeatureMTE, FeatureFP16FML, FeatureETE, FeatureMTE, FeatureFP16FML,
FeatureSVE2BitPerm, FeatureBF16, FeatureMatMulInt8]; FeatureSVE2BitPerm, FeatureBF16, FeatureMatMulInt8];
list<SubtargetFeature> R82 = [HasV8_0rOps]; list<SubtargetFeature> R82 = [HasV8_0rOps, FeaturePerfMon, FeatureFullFP16,
FeatureFP16FML, FeatureSSBS, FeaturePredRes,
FeatureSB, FeatureSpecRestrict];
list<SubtargetFeature> X1 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, list<SubtargetFeature> X1 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
FeatureNEON, FeatureRCPC, FeaturePerfMon, FeatureNEON, FeatureRCPC, FeaturePerfMon,
FeatureSPE, FeatureFullFP16, FeatureDotProd]; FeatureSPE, FeatureFullFP16, FeatureDotProd];
list<SubtargetFeature> X2 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon, list<SubtargetFeature> X2 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon,
FeatureMatMulInt8, FeatureBF16, FeatureAM, FeatureMatMulInt8, FeatureBF16, FeatureAM,
FeatureMTE, FeatureETE, FeatureSVE2BitPerm, FeatureMTE, FeatureETE, FeatureSVE2BitPerm,
FeatureFP16FML]; FeatureFP16FML];
list<SubtargetFeature> A64FX = [HasV8_2aOps, FeatureFPARMv8, FeatureNEON, list<SubtargetFeature> A64FX = [HasV8_2aOps, FeatureFPARMv8, FeatureNEON,
▲ Show 20 Lines • Show All 248 Lines • Show Last 20 Lines

llvm/test/MC/AArch64/armv8.2a-crypto.s

// RUN: not llvm-mc -triple aarch64 -mattr=+sha3,-sm4 -show-encoding < %s 2> %t | FileCheck %s --check-prefix=CHECK-SHA // RUN: not llvm-mc -triple aarch64 -mattr=+sha3,-sm4 -show-encoding < %s 2> %t | FileCheck %s --check-prefix=CHECK-SHA
// RUN: FileCheck --check-prefix=CHECK-NO-SM < %t %s // RUN: FileCheck --check-prefix=CHECK-NO-SM < %t %s
// RUN: not llvm-mc -triple aarch64 -mattr=+sm4,-sha3 -show-encoding < %s 2> %t | FileCheck %s --check-prefix=CHECK-SM // RUN: not llvm-mc -triple aarch64 -mattr=+sm4,-sha3 -show-encoding < %s 2> %t | FileCheck %s --check-prefix=CHECK-SM
// RUN: FileCheck --check-prefix=CHECK-NO-SHA < %t %s // RUN: FileCheck --check-prefix=CHECK-NO-SHA < %t %s
// RUN: not llvm-mc -triple aarch64 -show-encoding < %s 2> %t // RUN: not llvm-mc -triple aarch64 -show-encoding < %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-NO-SHA --check-prefix=CHECK-NO-SM < %t %s // RUN: FileCheck --check-prefix=CHECK-NO-SHA --check-prefix=CHECK-NO-SM < %t %s
// RUN: llvm-mc -triple aarch64 -mattr=+v8r -show-encoding -o - %s | FileCheck %s --check-prefixes=CHECK-SM,CHECK-SHA // RUN: not llvm-mc -triple aarch64 -mattr=+v8r -show-encoding -o - %s < %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-NO-SHA --check-prefix=CHECK-NO-SM < %t %s
sha512h q0, q1, v2.2d sha512h q0, q1, v2.2d
sha512h2 q0, q1, v2.2d sha512h2 q0, q1, v2.2d
sha512su0 v11.2d, v12.2d sha512su0 v11.2d, v12.2d
sha512su1 v11.2d, v13.2d, v14.2d sha512su1 v11.2d, v13.2d, v14.2d
eor3 v25.16b, v12.16b, v7.16b, v2.16b eor3 v25.16b, v12.16b, v7.16b, v2.16b
rax1 v30.2d, v29.2d, v26.2d rax1 v30.2d, v29.2d, v26.2d
xar v26.2d, v21.2d, v27.2d, #63 xar v26.2d, v21.2d, v27.2d, #63
▲ Show 20 Lines • Show All 48 Lines • Show Last 20 Lines

llvm/test/MC/Disassembler/AArch64/armv8.3a-complex.txt

# RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.3a,-fullfp16 --disassemble < %s 2>%t | FileCheck %s --check-prefix=CHECK # RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.3a,-fullfp16 --disassemble < %s 2>%t | FileCheck %s --check-prefix=CHECK
# RUN: FileCheck %s < %t --check-prefix=NO-FP16 # RUN: FileCheck %s < %t --check-prefix=NO-FP16
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.3a,+fullfp16 --disassemble < %s 2>%t | FileCheck %s --check-prefix=CHECK --check-prefix=FP16 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.3a,+fullfp16 --disassemble < %s 2>%t | FileCheck %s --check-prefix=CHECK --check-prefix=FP16
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8r --disassemble < %s 2>%t | FileCheck %s --check-prefix=CHECK --check-prefix=FP16 # RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8r --disassemble < %s 2>%t | FileCheck %s --check-prefix=CHECK
# RUN: FileCheck %s < %t --check-prefix=NO-FP16
# RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=-v8.3a,+fullfp16 --disassemble < %s 2>&1 | FileCheck %s --check-prefix=NO-V83A # RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=-v8.3a,+fullfp16 --disassemble < %s 2>&1 | FileCheck %s --check-prefix=NO-V83A
###### FCMLA vector ###### FCMLA vector
[0x20,0xc4,0x42,0x2e] [0x20,0xc4,0x42,0x2e]
# FP16: fcmla v0.4h, v1.4h, v2.4h, #0 # FP16: fcmla v0.4h, v1.4h, v2.4h, #0
# NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: warning: invalid instruction encoding # NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: warning: invalid instruction encoding
# NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: warning: invalid instruction encoding # NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: warning: invalid instruction encoding
[0x20,0xc4,0x42,0x6e] [0x20,0xc4,0x42,0x6e]
▲ Show 20 Lines • Show All 90 Lines • Show Last 20 Lines

llvm/test/MC/Disassembler/AArch64/armv8.5a-predres.txt

# RUN: llvm-mc -triple=aarch64 -mattr=+predres -disassemble < %s | FileCheck %s # RUN: llvm-mc -triple=aarch64 -mattr=+predres -disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple=aarch64 -mattr=+v8.5a -disassemble < %s | FileCheck %s # RUN: llvm-mc -triple=aarch64 -mattr=+v8.5a -disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple=aarch64 -mattr=+v8r -disassemble < %s | FileCheck %s # RUN: llvm-mc -triple=aarch64 -mattr=+v8r -disassemble < %s | FileCheck %s --check-prefix=NOSB
# RUN: llvm-mc -triple=aarch64 -mattr=-predres -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOSB # RUN: llvm-mc -triple=aarch64 -mattr=-predres -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOSB
[0x80 0x73 0x0b 0xd5] [0x80 0x73 0x0b 0xd5]
[0xa1 0x73 0x0b 0xd5] [0xa1 0x73 0x0b 0xd5]
[0xe2 0x73 0x0b 0xd5] [0xe2 0x73 0x0b 0xd5]
# CHECK: cfp rctx, x0 # CHECK: cfp rctx, x0
# CHECK: dvp rctx, x1 # CHECK: dvp rctx, x1
# CHECK: cpp rctx, x2 # CHECK: cpp rctx, x2
# NOSB: sys #3, c7, c3, #4, x0 # NOSB: sys #3, c7, c3, #4, x0
# NOSB: sys #3, c7, c3, #5, x1 # NOSB: sys #3, c7, c3, #5, x1
# NOSB: sys #3, c7, c3, #7, x2 # NOSB: sys #3, c7, c3, #7, x2

llvm/test/MC/Disassembler/AArch64/armv8.5a-specrestrict.txt

# RUN: llvm-mc -triple=aarch64 -mattr=+specrestrict -disassemble < %s | FileCheck %s # RUN: llvm-mc -triple=aarch64 -mattr=+specrestrict -disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple=aarch64 -mattr=+v8.5a -disassemble < %s | FileCheck %s # RUN: llvm-mc -triple=aarch64 -mattr=+v8.5a -disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple=aarch64 -mattr=+v8r -disassemble < %s | FileCheck %s # RUN: llvm-mc -triple=aarch64 -mattr=+v8r -disassemble < %s | FileCheck %s --check-prefix=NOSPECID
# RUN: llvm-mc -triple=aarch64 -mattr=-specrestrict -disassemble < %s | FileCheck %s --check-prefix=NOSPECID # RUN: llvm-mc -triple=aarch64 -mattr=-specrestrict -disassemble < %s | FileCheck %s --check-prefix=NOSPECID
[0x81 0x03 0x38 0xd5] [0x81 0x03 0x38 0xd5]
# CHECK: mrs x1, {{id_pfr2_el1|ID_PFR2_EL1}} # CHECK: mrs x1, {{id_pfr2_el1|ID_PFR2_EL1}}
# NOSPECID: mrs x1, S3_0_C0_C3_4 # NOSPECID: mrs x1, S3_0_C0_C3_4
[0xe8 0xd0 0x3b 0xd5] [0xe8 0xd0 0x3b 0xd5]
Show All 32 Lines

llvm/test/MC/Disassembler/AArch64/armv8.5a-ssbs.txt

# RUN: llvm-mc -triple=aarch64 -mattr=+ssbs -disassemble < %s | FileCheck %s # RUN: llvm-mc -triple=aarch64 -mattr=+ssbs -disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple=aarch64 -mattr=+v8.5a -disassemble < %s | FileCheck %s # RUN: llvm-mc -triple=aarch64 -mattr=+v8.5a -disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple=aarch64 -mcpu=cortex-a76 -disassemble < %s | FileCheck %s # RUN: llvm-mc -triple=aarch64 -mcpu=cortex-a76 -disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple=aarch64 -mcpu=cortex-a76ae -disassemble < %s | FileCheck %s # RUN: llvm-mc -triple=aarch64 -mcpu=cortex-a76ae -disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple=aarch64 -mattr=+v8r -disassemble < %s | FileCheck %s # RUN: llvm-mc -triple=aarch64 -mattr=+v8r -disassemble < %s | FileCheck %s --check-prefix=NOSPECID
# RUN: llvm-mc -triple=aarch64 -mattr=-ssbs -disassemble < %s | FileCheck %s --check-prefix=NOSPECID # RUN: llvm-mc -triple=aarch64 -mattr=-ssbs -disassemble < %s | FileCheck %s --check-prefix=NOSPECID
[0x3f 0x41 0x03 0xd5] [0x3f 0x41 0x03 0xd5]
[0xc3 0x42 0x1b 0xd5] [0xc3 0x42 0x1b 0xd5]
[0xc2 0x42 0x3b 0xd5] [0xc2 0x42 0x3b 0xd5]
# CHECK: msr SSBS, #1 # CHECK: msr SSBS, #1
# CHECK: msr SSBS, x3 # CHECK: msr SSBS, x3
# CHECK: mrs x2, SSBS # CHECK: mrs x2, SSBS
# NOSPECID: msr S0_3_C4_C1_1, xzr # NOSPECID: msr S0_3_C4_C1_1, xzr
# NOSPECID: msr S3_3_C4_C2_6, x3 # NOSPECID: msr S3_3_C4_C2_6, x3
# NOSPECID: mrs x2, S3_3_C4_C2_6 # NOSPECID: mrs x2, S3_3_C4_C2_6

llvm/test/MC/Disassembler/AArch64/armv8a-fpmul.txt

# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+fp16fml --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,FP16 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+fp16fml --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,FP16
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=-fullfp16,+fp16fml --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,FP16 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=-fullfp16,+fp16fml --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,FP16
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8r --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,FP16
#A fullfp16 instruction, for testing the interaction of the features #A fullfp16 instruction, for testing the interaction of the features
[0x41,0x08,0xe3,0x1e] [0x41,0x08,0xe3,0x1e]
[0x20,0xec,0x22,0x0e] [0x20,0xec,0x22,0x0e]
[0x20,0xec,0xa2,0x0e] [0x20,0xec,0xa2,0x0e]
[0x20,0xec,0x22,0x4e] [0x20,0xec,0x22,0x4e]
[0x20,0xec,0xa2,0x4e] [0x20,0xec,0xa2,0x4e]
▲ Show 20 Lines • Show All 54 Lines • Show Last 20 Lines