This is an archive of the discontinued LLVM Phabricator instance.

Differential D117845

[AMDGPU][NFC] Update to AMDGPUUsage for default Code Object Version
ClosedPublic

Authored by cfang on Jan 20 2022, 3:56 PM.

Details

Reviewers
t-tye
kzhuravl
bcahoon
b-sumner
arsenm
lamb-j
msearles
Commits
rG4cfea311cb8e: [AMDGPU][NFC] Update to AMDGPUUsage for default Code Object Version
Summary

Update the documentation for default code object version (from v3 to v4).

Diff Detail

Event Timeline

cfang created this revision.Jan 20 2022, 3:56 PM
Herald added subscribers: kerbowa, tpr, dstuttard and 3 others. · View Herald TranscriptJan 20 2022, 3:56 PM
cfang requested review of this revision.Jan 20 2022, 3:56 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 20 2022, 3:56 PM
Herald added a subscriber: wdng. · View Herald Transcript
Harbormaster completed remote builds in B144706: Diff 401806.Jan 20 2022, 5:16 PM
cfang added reviewers: bcahoon, b-sumner, arsenm, lamb-j.Jan 24 2022, 10:38 AM
cfang added a reviewer: msearles.
kzhuravl added a comment.Jan 24 2022, 10:58 AM

Can you upload a diff with the context?

llvm/docs/AMDGPUUsage.rst
26

Why is this here?

1708–1710

Why is this here?

cfang updated this revision to Diff 402595.Jan 24 2022, 11:06 AM

Update diff with context

cfang added inline comments.Jan 24 2022, 11:08 AM
llvm/docs/AMDGPUUsage.rst
26

Why is this here?

Not clear why. Purely sync from another branch.

1708–1710

Why is this here?

Not clear why. Purely sync from another branch.

kzhuravl added a comment.Jan 24 2022, 11:09 AM

Any reason you are bringing in heterogeneous debugging bits in this change?

llvm/docs/AMDGPUUsage.rst
26

Can you remove it and the other one? It does not relate to this change.

cfang updated this revision to Diff 402603.Jan 24 2022, 11:14 AM

Remove irrelevant changes as suggested.

kzhuravl added a comment.Jan 24 2022, 11:16 AM

Can you also update summary to drop AMDGPULLVMExtensionsForHeterogeneousDebugging?

llvm/docs/AMDGPUUsage.rst
1707

Remove extra new line.

cfang updated this revision to Diff 402605.Jan 24 2022, 11:19 AM
cfang edited the summary of this revision. (Show Details)

Update the summary and remove a empty new line

kzhuravl accepted this revision.Jan 24 2022, 1:07 PM

lgtm

This revision is now accepted and ready to land.Jan 24 2022, 1:07 PM
This revision was landed with ongoing or failed builds.Jan 24 2022, 2:35 PM
Closed by commit rG4cfea311cb8e: [AMDGPU][NFC] Update to AMDGPUUsage for default Code Object Version (authored by cfang). · Explain Why
This revision was automatically updated to reflect the committed changes.
cfang added a commit: rG4cfea311cb8e: [AMDGPU][NFC] Update to AMDGPUUsage for default Code Object Version.
Harbormaster completed remote builds in B145287: Diff 402605.Jan 26 2022, 10:57 AM

Revision Contents

PathSize
llvm/
docs/
14 lines

Diff 402605

llvm/docs/AMDGPUUsage.rst

Context not available.
AMDGPUOperandSyntax AMDGPUOperandSyntax
AMDGPUInstructionSyntax AMDGPUInstructionSyntax
AMDGPUInstructionNotation AMDGPUInstructionNotation
AMDGPUDwarfExtensionsForHeterogeneousDebugging AMDGPUDwarfExtensionsForHeterogeneousDebugging
AMDGPUDwarfExtensionAllowLocationDescriptionOnTheDwarfExpressionStack/AMDGPUDwarfExtensionAllowLocationDescriptionOnTheDwarfExpressionStack AMDGPUDwarfExtensionAllowLocationDescriptionOnTheDwarfExpressionStack/AMDGPUDwarfExtensionAllowLocationDescriptionOnTheDwarfExpressionStack
kzhuravlUnsubmitted
Not Done
ReplyInline Actions

Why is this here?

kzhuravl: Why is this here?
cfangAuthorUnsubmitted
Done
ReplyInline Actions

Why is this here?

Not clear why. Purely sync from another branch.

cfang: > Why is this here? Not clear why. Purely sync from another branch.
kzhuravlUnsubmitted
Not Done
ReplyInline Actions

Can you remove it and the other one? It does not relate to this change.

kzhuravl: Can you remove it and the other one? It does not relate to this change.
Introduction Introduction
============ ============
The AMDGPU backend provides ISA code generation for AMD GPUs, starting with the The AMDGPU backend provides ISA code generation for AMD GPUs, starting with the
R600 family up until the current GCN families. It lives in the R600 family up until the current GCN families. It lives in the
``llvm/lib/Target/AMDGPU`` directory. ``llvm/lib/Target/AMDGPU`` directory.
▲ Show 20 Lines • Show All 978 Lines • ▼ Show 20 Lines
object conforms: object conforms:
* ``ELFABIVERSION_AMDGPU_HSA_V2`` is used to specify the version of AMD HSA * ``ELFABIVERSION_AMDGPU_HSA_V2`` is used to specify the version of AMD HSA
runtime ABI for code object V2. Specify using the Clang option runtime ABI for code object V2. Specify using the Clang option
``-mcode-object-version=2``. ``-mcode-object-version=2``.
* ``ELFABIVERSION_AMDGPU_HSA_V3`` is used to specify the version of AMD HSA * ``ELFABIVERSION_AMDGPU_HSA_V3`` is used to specify the version of AMD HSA
runtime ABI for code object V3. Specify using the Clang option runtime ABI for code object V3. Specify using the Clang option
``-mcode-object-version=3``. This is the default code object ``-mcode-object-version=3``.
version if not specified.
* ``ELFABIVERSION_AMDGPU_HSA_V4`` is used to specify the version of AMD HSA * ``ELFABIVERSION_AMDGPU_HSA_V4`` is used to specify the version of AMD HSA
runtime ABI for code object V4. Specify using the Clang option runtime ABI for code object V4. Specify using the Clang option
``-mcode-object-version=4``. ``-mcode-object-version=4``. This is the default code object
version if not specified.
* ``ELFABIVERSION_AMDGPU_PAL`` is used to specify the version of AMD PAL * ``ELFABIVERSION_AMDGPU_PAL`` is used to specify the version of AMD PAL
runtime ABI. runtime ABI.
* ``ELFABIVERSION_AMDGPU_MESA3D`` is used to specify the version of AMD MESA * ``ELFABIVERSION_AMDGPU_MESA3D`` is used to specify the version of AMD MESA
3D runtime ABI. 3D runtime ABI.
``e_type`` ``e_type``
▲ Show 20 Lines • Show All 664 Lines • ▼ Show 20 Lines
AMDGPU generates DWARF [DWARF]_ debugging information ELF sections (see AMDGPU generates DWARF [DWARF]_ debugging information ELF sections (see
:ref:`amdgpu-elf-code-object`) which contain information that maps the code :ref:`amdgpu-elf-code-object`) which contain information that maps the code
object executable code and data to the source language constructs. It can be object executable code and data to the source language constructs. It can be
used by tools such as debuggers and profilers. It uses features defined in used by tools such as debuggers and profilers. It uses features defined in
:doc:`AMDGPUDwarfExtensionsForHeterogeneousDebugging` that are made available in :doc:`AMDGPUDwarfExtensionsForHeterogeneousDebugging` that are made available in
DWARF Version 4 and DWARF Version 5 as an LLVM vendor extension. DWARF Version 4 and DWARF Version 5 as an LLVM vendor extension.
This section defines the AMDGPU target architecture specific DWARF mappings. This section defines the AMDGPU target architecture specific DWARF mappings.
kzhuravlUnsubmitted
Not Done
ReplyInline Actions

Remove extra new line.

kzhuravl: Remove extra new line.
.. _amdgpu-dwarf-register-identifier: .. _amdgpu-dwarf-register-identifier:
kzhuravlUnsubmitted
Not Done
ReplyInline Actions

Why is this here?

kzhuravl: Why is this here?
cfangAuthorUnsubmitted
Done
ReplyInline Actions

Why is this here?

Not clear why. Purely sync from another branch.

cfang: > Why is this here? Not clear why. Purely sync from another branch.
Register Identifier Register Identifier
------------------- -------------------
This section defines the AMDGPU target architecture register numbers used in This section defines the AMDGPU target architecture register numbers used in
DWARF operation expressions (see DWARF Version 5 section 2.5 and DWARF operation expressions (see DWARF Version 5 section 2.5 and
:ref:`amdgpu-dwarf-operation-expressions`) and Call Frame Information :ref:`amdgpu-dwarf-operation-expressions`) and Call Frame Information
instructions (see DWARF Version 5 section 6.4 and instructions (see DWARF Version 5 section 6.4 and
:ref:`amdgpu-dwarf-call-frame-information`). :ref:`amdgpu-dwarf-call-frame-information`).
▲ Show 20 Lines • Show All 1,266 Lines • ▼ Show 20 Lines
location. location.
============================ ============== ========= ===================== ============================ ============== ========= =====================
.. _amdgpu-amdhsa-code-object-metadata-v3: .. _amdgpu-amdhsa-code-object-metadata-v3:
Code Object V3 Metadata Code Object V3 Metadata
+++++++++++++++++++++++ +++++++++++++++++++++++
.. warning::
Code object V3 is not the default code object version emitted by this version
of LLVM.
Code object V3 to V4 metadata is specified by the ``NT_AMDGPU_METADATA`` note Code object V3 to V4 metadata is specified by the ``NT_AMDGPU_METADATA`` note
record (see :ref:`amdgpu-note-records-v3-v4`). record (see :ref:`amdgpu-note-records-v3-v4`).
The metadata is represented as Message Pack formatted binary data (see The metadata is represented as Message Pack formatted binary data (see
[MsgPack]_). The top level is a Message Pack map that includes the [MsgPack]_). The top level is a Message Pack map that includes the
keys defined in table keys defined in table
:ref:`amdgpu-amdhsa-code-object-metadata-map-table-v3` and referenced :ref:`amdgpu-amdhsa-code-object-metadata-map-table-v3` and referenced
tables. tables.
▲ Show 20 Lines • Show All 419 Lines • ▼ Show 20 Lines
====================== ============== ========= ================================ ====================== ============== ========= ================================
.. _amdgpu-amdhsa-code-object-metadata-v4: .. _amdgpu-amdhsa-code-object-metadata-v4:
Code Object V4 Metadata Code Object V4 Metadata
+++++++++++++++++++++++ +++++++++++++++++++++++
.. warning::
Code object V4 is not the default code object version emitted by this version
of LLVM.
Code object V4 metadata is the same as Code object V4 metadata is the same as
:ref:`amdgpu-amdhsa-code-object-metadata-v3` with the changes and additions :ref:`amdgpu-amdhsa-code-object-metadata-v3` with the changes and additions
defined in table :ref:`amdgpu-amdhsa-code-object-metadata-map-table-v3`. defined in table :ref:`amdgpu-amdhsa-code-object-metadata-map-table-v3`.
.. table:: AMDHSA Code Object V4 Metadata Map Changes from :ref:`amdgpu-amdhsa-code-object-metadata-v3` .. table:: AMDHSA Code Object V4 Metadata Map Changes from :ref:`amdgpu-amdhsa-code-object-metadata-v3`
:name: amdgpu-amdhsa-code-object-metadata-map-table-v4 :name: amdgpu-amdhsa-code-object-metadata-map-table-v4
================= ============== ========= ======================================= ================= ============== ========= =======================================
▲ Show 20 Lines • Show All 991 Lines • Show Last 20 Lines