[RISCV] Add instruction schedule for Zbe extension and Zbm extension

[Jimerlife]

Summary

Zbe extension
bdecompress/bcompress/bdecompressw/bcompressw, each instruction defined one schedule class

Zbm extension
bmator/bmatxor/bmatflip are grouped together, defined one schedule class

llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

 def CTZ  : RVBUnary<0b0110000, 0b00001, 0b001, OPC_OP_IMM, "ctz">,
            Sched<[WriteCTZ, ReadCTZ]>;
 def CPOP : RVBUnary<0b0110000, 0b00010, 0b001, OPC_OP_IMM, "cpop">,
            Sched<[WriteCPOP, ReadCPOP]>;
 } // Predicates = [HasStdExtZbb]
 
 let Predicates = [HasStdExtZbm, IsRV64] in
 def BMATFLIP : RVBUnary<0b0110000, 0b00011, 0b001, OPC_OP_IMM, "bmatflip">,
-               Sched<[]>;
+               Sched<[WriteBMatrix, ReadBMatrix]>;
 
 let Predicates = [HasStdExtZbb] in {
 def SEXTB : RVBUnary<0b0110000, 0b00100, 0b001, OPC_OP_IMM, "sext.b">,
             Sched<[WriteIALU, ReadIALU]>;
 def SEXTH : RVBUnary<0b0110000, 0b00101, 0b001, OPC_OP_IMM, "sext.h">,
             Sched<[WriteIALU, ReadIALU]>;
 } // Predicates = [HasStdExtZbb]
 

 let Predicates = [HasStdExtZbp] in {
 def SHFL   : ALU_rr<0b0000100, 0b001, "shfl">, Sched<[]>;
 def UNSHFL : ALU_rr<0b0000100, 0b101, "unshfl">, Sched<[]>;
 } // Predicates = [HasStdExtZbp]
 
 let Predicates = [HasStdExtZbe] in {
 // NOTE: These mnemonics are from the 0.94 spec. There is a name conflict with
 // bext in the 0.93 spec.
-def BDECOMPRESS : ALU_rr<0b0100100, 0b110, "bdecompress">, Sched<[]>;
-def BCOMPRESS   : ALU_rr<0b0000100, 0b110, "bcompress">, Sched<[]>;
+def BDECOMPRESS : ALU_rr<0b0100100, 0b110, "bdecompress">,
+                  Sched<[WriteDecompress, ReadDecompress, ReadDecompress]>;
+def BCOMPRESS   : ALU_rr<0b0000100, 0b110, "bcompress">,
+                  Sched<[WriteCompress, ReadCompress, ReadCompress]>;
 } // Predicates = [HasStdExtZbe]
 
 let Predicates = [HasStdExtZbp] in {
 def PACK  : ALU_rr<0b0000100, 0b100, "pack">, Sched<[]>;
 def PACKU : ALU_rr<0b0100100, 0b100, "packu">, Sched<[]>;
 def PACKH : ALU_rr<0b0000100, 0b111, "packh">, Sched<[]>;
 } // Predicates = [HasStdExtZbp]
 
 let Predicates = [HasStdExtZbm, IsRV64] in {
-def BMATOR   : ALU_rr<0b0000100, 0b011, "bmator">, Sched<[]>;
-def BMATXOR  : ALU_rr<0b0100100, 0b011, "bmatxor">, Sched<[]>;
+def BMATOR   : ALU_rr<0b0000100, 0b011, "bmator">,
+               Sched<[WriteBMatrix, ReadBMatrix, ReadBMatrix]>;
+def BMATXOR  : ALU_rr<0b0100100, 0b011, "bmatxor">,
+               Sched<[WriteBMatrix, ReadBMatrix, ReadBMatrix]>;
 } // Predicates = [HasStdExtZbm, IsRV64]
 
 let Predicates = [HasStdExtZbf] in
 def BFP : ALU_rr<0b0100100, 0b111, "bfp">,
           Sched<[WriteBFP, ReadBFP, ReadBFP]>;
 
 let Predicates = [HasStdExtZbp] in {
 def SHFLI   : RVBShfl_ri<0b0000100, 0b001, OPC_OP_IMM, "shfli">, Sched<[]>;

 let Predicates = [HasStdExtZbp, IsRV64] in {
 def SHFLW   : ALUW_rr<0b0000100, 0b001, "shflw">, Sched<[]>;
 def UNSHFLW : ALUW_rr<0b0000100, 0b101, "unshflw">, Sched<[]>;
 } // Predicates = [HasStdExtZbp, IsRV64]
 
 let Predicates = [HasStdExtZbe, IsRV64] in {
 // NOTE: These mnemonics are from the 0.94 spec. There is a name conflict with
 // bextw in the 0.93 spec.
-def BDECOMPRESSW : ALUW_rr<0b0100100, 0b110, "bdecompressw">, Sched<[]>;
-def BCOMPRESSW   : ALUW_rr<0b0000100, 0b110, "bcompressw">, Sched<[]>;
+def BDECOMPRESSW : ALUW_rr<0b0100100, 0b110, "bdecompressw">,
+                   Sched<[WriteDecompress32, ReadDecompress32,
+                          ReadDecompress32]>;
+def BCOMPRESSW   : ALUW_rr<0b0000100, 0b110, "bcompressw">,
+                   Sched<[WriteCompress32, ReadCompress32, ReadCompress32]>;
 } // Predicates = [HasStdExtZbe, IsRV64]
 
 let Predicates = [HasStdExtZbp, IsRV64] in {
 def PACKW  : ALUW_rr<0b0000100, 0b100, "packw">, Sched<[]>;
 def PACKUW : ALUW_rr<0b0100100, 0b100, "packuw">, Sched<[]>;
 } // Predicates = [HasStdExtZbp, IsRV64]
 
 let Predicates = [HasStdExtZbf, IsRV64] in

llvm/lib/Target/RISCV/RISCVSchedRocket.td

 
 //===----------------------------------------------------------------------===//
 // Unsupported extensions
 defm : UnsupportedSchedV;
 defm : UnsupportedSchedZba;
 defm : UnsupportedSchedZbb;
 defm : UnsupportedSchedZbc;
 defm : UnsupportedSchedZbs;
+defm : UnsupportedSchedZbe;
 defm : UnsupportedSchedZbf;
+defm : UnsupportedSchedZbm;
 defm : UnsupportedSchedZfh;
 }

llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

 
 //===----------------------------------------------------------------------===//
 // Unsupported extensions
 defm : UnsupportedSchedV;
 defm : UnsupportedSchedZba;
 defm : UnsupportedSchedZbb;
 defm : UnsupportedSchedZbc;
 defm : UnsupportedSchedZbs;
+defm : UnsupportedSchedZbe;
 defm : UnsupportedSchedZbf;
+defm : UnsupportedSchedZbm;
 defm : UnsupportedSchedZfh;
 }

llvm/lib/Target/RISCV/RISCVScheduleB.td

 
 // Zbc extension
 def WriteCLMUL       : SchedWrite; // CLMUL/CLMULR/CLMULH
 
 // Zbs extension
 def WriteSingleBit   : SchedWrite; // BCLR/BSET/BINV/BEXT
 def WriteSingleBitImm: SchedWrite; // BCLRI/BSETI/BINVI/BEXTI
 
+// Zbe extension
+def WriteDecompress  : SchedWrite; // bdecompress
+def WriteCompress    : SchedWrite; // bcompress
+def WriteDecompress32: SchedWrite; // bdecompressw
+def WriteCompress32  : SchedWrite; // bcompressw
+
 // Zbf extension
 def WriteBFP         : SchedWrite; // BFP
 def WriteBFP32       : SchedWrite; // BFPW
 
+// Zbm extension
+def WriteBMatrix     : SchedWrite; // bmator/bmatxor/bmatflip
+
 /// Define scheduler resources associated with use operands.
 
 // Zba extension
 def ReadSHXADD      : SchedRead; // sh1add/sh2add/sh3add
 def ReadSHXADD32    : SchedRead; // sh1add.uw/sh2add.uw/sh3add.uw
 
 // Zbb extension
 def ReadRotateImm   : SchedRead;

 
 // Zbc extension
 def ReadCLMUL       : SchedRead; // CLMUL/CLMULR/CLMULH
 
 // Zbs extension
 def ReadSingleBit   : SchedRead; // BCLR/BSET/BINV/BEXT
 def ReadSingleBitImm: SchedRead; // BCLRI/BSETI/BINVI/BEXTI
 
+// Zbe extension
+def ReadDecompress  : SchedRead; // bdecompress
+def ReadCompress    : SchedRead; // bcompress
+def ReadDecompress32: SchedRead; // bdecompressw
+def ReadCompress32  : SchedRead; // bcompressw
+
 // Zbf extension
 def ReadBFP         : SchedRead; // BFP
 def ReadBFP32       : SchedRead; // BFPW
 
+// Zbm extension
+def ReadBMatrix     : SchedRead; // bmator/bmatxor/bmatflip
+
 /// Define default scheduler resources for B.
 
 multiclass UnsupportedSchedZba {
 let Unsupported = true in {
 def : WriteRes<WriteSHXADD, []>;
 def : WriteRes<WriteSHXADD32, []>;
 
 def : ReadAdvance<ReadSHXADD, 0>;

 def : WriteRes<WriteSingleBit, []>;
 def : WriteRes<WriteSingleBitImm, []>;
 
 def : ReadAdvance<ReadSingleBit, 0>;
 def : ReadAdvance<ReadSingleBitImm, 0>;
 }
 }
 
+multiclass UnsupportedSchedZbe {
+let Unsupported = true in {
+def : WriteRes<WriteDecompress, []>;
+def : WriteRes<WriteCompress, []>;
+def : WriteRes<WriteDecompress32, []>;
+def : WriteRes<WriteCompress32, []>;
+
+def : ReadAdvance<ReadDecompress, 0>;
+def : ReadAdvance<ReadCompress, 0>;
+def : ReadAdvance<ReadDecompress32, 0>;
+def : ReadAdvance<ReadCompress32, 0>;
+}
+}
+
 multiclass UnsupportedSchedZbf {
 let Unsupported = true in {
 def : WriteRes<WriteBFP, []>;
 def : WriteRes<WriteBFP32, []>;
 
 def : ReadAdvance<ReadBFP, 0>;
 def : ReadAdvance<ReadBFP32, 0>;
 }
 }
+
+multiclass UnsupportedSchedZbm {
+let Unsupported = true in {
+def : WriteRes<WriteBMatrix, []>;
+
+def : ReadAdvance<ReadBMatrix, 0>;
+}
+}