[BOLT] Fix AARCH64 registers aliasing

[yota9]

Summary

The aarch64 platform has special registers like X0_X1_X2_X3_X4_X5_X6_X7.
Using the downwars propagation this register will become a super
register for all X0..X7 and its subregisters which is not right. This
patch replaces the downwars propagation with caching all the aliases using MCRegAliasIterator.

Vladislav Khmelevsky,
Advanced Software Technology Lab, Huawei

[fhahn]

Is it possible to add a test?

[yota9]

@fhahn This is very internal function of the BOLT, so I'm not sure hot to add such a testcase

[fhahn]

In D117394#3247843, @yota9 wrote:

@fhahn This is very internal function of the BOLT, so I'm not sure hot to add such a testcase

It fixes something, so there should be a way to test this change in behavior I assume, although I have no idea about how unit tests for bolt look like.

[yota9]

@fhahn The problem was not found during bolt usage, i.e. wrong output, but accidentally while I was investigating the aarch64 indirect branch support level. Currently the bolt uses tests like "input file" -> "output file", but I don't have an example of input file where the problem might occur and I don't know the way to test particular function from bolt internals. Maybe the reviewers will give me a hint on this

[yota9]

Very gentle ping to @maksfb @rafauler @Amir :))

[maksfb]

Thanks for the fix! Please spellcheck the summary before committing.

[fhahn]

In D117394#3265252, @maksfb wrote:

Thanks for the fix! Please spellcheck the summary before committing.

There remains the question of and how this can be tested I think.

[maksfb]

In D117394#3265334, @fhahn wrote:

In D117394#3265252, @maksfb wrote:

Thanks for the fix! Please spellcheck the summary before committing.

There remains the question of and how this can be tested I think.

That's a good point. @yota9, if the testing can only be done via unit tests, we should add it. Which means we also have to add necessary changes to /bolt, as we currently don't have unit tests setup.

[yota9]

Hello @maksfb I was able to add unit tests support and to test this particular function :)

[Amir]

@yota9
That's very impressive! But can you please split out adding the unit test infrastructure to a separate diff?

[maksfb]

That's fantastic. Thank you, @yota9.

[yota9]

Reabased patch, add x86 reg aliasing test

[yota9]

Test refactor

[yota9]

Add target-specific includes under ifdef

[yota9]

Gentle ping to reviewers :)

[maksfb]

Looks great!

[rafauler]

Looks good, thanks! What are the practical implications of this for AArch64? Which pass is relying on ::getAliases()?

[yota9]

In D117394#3277884, @rafauler wrote:

Looks good, thanks! What are the practical implications of this for AArch64? Which pass is relying on ::getAliases()?

Hello @rafaelauler ! I've found out the problem while investigating the analyzeIndirectBranchFragment for aarch64..

bolt/lib/Core/MCPlusBuilder.cpp

bool MCPlusBuilder::hasUseOfPhysReg(const MCInst &MI, unsigned Reg) const {
   return false;
 }
 
 const BitVector &MCPlusBuilder::getAliases(MCPhysReg Reg,
                                            bool OnlySmaller) const {
   // AliasMap caches a mapping of registers to the set of registers that
   // alias (are sub or superregs of itself, including itself).
   static std::vector<BitVector> AliasMap;
-  static std::vector<MCPhysReg> SuperReg;
+  static std::vector<BitVector> SmallerAliasMap;
 
   if (AliasMap.size() > 0) {
     if (OnlySmaller)
-      return AliasMap[Reg];
-    return AliasMap[SuperReg[Reg]];
+      return SmallerAliasMap[Reg];
   }
+
   // Build alias map
   for (MCPhysReg I = 0, E = RegInfo->getNumRegs(); I != E; ++I) {
     BitVector BV(RegInfo->getNumRegs(), false);
     BV.set(I);
-    AliasMap.emplace_back(std::move(BV));
-    SuperReg.emplace_back(I);
+    AliasMap.emplace_back(BV);
+    SmallerAliasMap.emplace_back(BV);
+  }
+
+  // Cache all aliases for each register
+  for (MCPhysReg I = 1, E = RegInfo->getNumRegs(); I != E; ++I) {
+    for (MCRegAliasIterator AI(I, RegInfo, true); AI.isValid(); ++AI)
+      AliasMap[I].set(*AI);
   }
+
+  // Propagate smaller alias info upwards. Skip reg 0 (mapped to NoRegister)
   std::queue<MCPhysReg> Worklist;
-  // Propagate alias info upwards. Skip reg 0 (mapped to NoRegister)
   for (MCPhysReg I = 1, E = RegInfo->getNumRegs(); I < E; ++I)
     Worklist.push(I);
   while (!Worklist.empty()) {
     MCPhysReg I = Worklist.front();
     Worklist.pop();
     for (MCSubRegIterator SI(I, RegInfo); SI.isValid(); ++SI)
-      AliasMap[I] |= AliasMap[*SI];
+      SmallerAliasMap[I] |= SmallerAliasMap[*SI];
     for (MCSuperRegIterator SI(I, RegInfo); SI.isValid(); ++SI)
       Worklist.push(*SI);
   }
-  // Propagate parent reg downwards
-  for (MCPhysReg I = 1, E = RegInfo->getNumRegs(); I < E; ++I)
-    Worklist.push(I);
-  while (!Worklist.empty()) {
-    MCPhysReg I = Worklist.front();
-    Worklist.pop();
-    for (MCSubRegIterator SI(I, RegInfo); SI.isValid(); ++SI) {
-      SuperReg[*SI] = SuperReg[I];
-      Worklist.push(*SI);
-    }
-  }
 
   LLVM_DEBUG({
     dbgs() << "Dumping reg alias table:\n";
     for (MCPhysReg I = 0, E = RegInfo->getNumRegs(); I != E; ++I) {
       dbgs() << "Reg " << I << ": ";
-      const BitVector &BV = AliasMap[SuperReg[I]];
+      const BitVector &BV = AliasMap[I];
       int Idx = BV.find_first();
       while (Idx != -1) {
         dbgs() << Idx << " ";
         Idx = BV.find_next(Idx);
       }
       dbgs() << "\n";
     }
   });
 
   if (OnlySmaller)
-    return AliasMap[Reg];
-  return AliasMap[SuperReg[Reg]];
+    return SmallerAliasMap[Reg];
 }
 
 uint8_t MCPlusBuilder::getRegSize(MCPhysReg Reg) const {
   // SizeMap caches a mapping of registers to their sizes
   static std::vector<uint8_t> SizeMap;
 
   if (SizeMap.size() > 0) {
     return SizeMap[Reg];