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[AArch64] Support for Ampere1 core
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Authored by philipp.tomsich on Jan 12 2022, 6:25 AM.

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Summary

Add support for the Ampere Computing Ampere1 core.
Ampere1 implements the AArch64 state and is compatible with ARMv8.6-A.

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Event Timeline

philipp.tomsich requested review of this revision.Jan 12 2022, 6:25 AM
Herald added projects: Restricted Project, Restricted Project. · View Herald TranscriptJan 12 2022, 6:25 AM

You could consider adding some scheduling tests, like those in llvm/test/tools/llvm-mca/AArch64/Cortex/A55-basic-instructions.s. In the past we have tended not to add them for schedules, so they are not necessary, but can be useful for checking the details are as you expect.

llvm/include/llvm/Support/AArch64TargetParser.def
295

I believe a lot of these (BF16, DotProd etc) are mandatory in armv8.6 and should already be included without needing to specify them here.

llvm/lib/Target/AArch64/AArch64.td
1224

The formatting here is a bit off, compared to all the others.

llvm/lib/Target/AArch64/AArch64SchedAmpere1.td
15

This line doesn't add a lot :)

17

an out-of-order micro-architecture

llvm/lib/Target/AArch64/AArch64SchedPredAmpere.td
18

I don't deal with these predicates a lot, but the formatting looks like it could be better. Is it using tabs?

llvm/lib/Target/AArch64/AArch64Subtarget.h
85

This list can be alphabetical.

stuij added a reviewer: stuij.Jan 13 2022, 2:07 AM

Update to reflect review results.

Herald added a project: Restricted Project. · View Herald TranscriptWed, Apr 27, 2:28 PM
dmgreen accepted this revision.Thu, Apr 28, 12:42 AM

I don't know the details of the scheduling latencies for the core, but this looks perfectly sensible. There are a few comments inline, but other than those this patch LGTM.

llvm/include/llvm/Support/AArch64TargetParser.def
296

The formatting is a bit off here.

llvm/lib/Target/AArch64/AArch64.td
1082

Should this include SSBS and MTE too, if they are included in the target parsing?

llvm/lib/Target/AArch64/AArch64Subtarget.h
85

This still needs to be alphabetical

This revision is now accepted and ready to land.Thu, Apr 28, 12:42 AM
  • additional tab -> space conversion (hopefully, I have emacs configured correctly now)
  • added SBSS and MTE to the SubtargetFeatures
  • inserted AMpere1 in the subtarget enum in alphabetical order

Adds two fixes for issues uncovered by the CI:

  • The update of NumAArch64CPUArchs had been lost in a "rebase gone wrong" (i.e., another target was added and the previously increased-by-1 value now was the already present upstream). This adjusts the value of NumAArch64CPUArchs to again account for the addition of an extra target.
  • Adjusts the ARMCPUTestParams for ampere1 to reflect that ARMv8.6 encodes the crypto extensions differently than lower architecture levels.
philipp.tomsich marked 4 inline comments as done.

Rebased to main.
The earlier base-regression was a precommitted test-case that caused
SimpleLoopUnswitch tests (not related to these changes) to fail.

This revision was landed with ongoing or failed builds.Tue, May 3, 7:54 AM
This revision was automatically updated to reflect the committed changes.