This is an archive of the discontinued LLVM Phabricator instance.

[RISCV] Block vmsgeu.vi with 0 immediate in Isel
ClosedPublic

Authored by Chenbing.Zheng on Jan 4 2022, 2:26 AM.

Details

Summary

For vmsgeu.vi with 0, we know this is always true,
so we can instead it with vmset.m (unmasked) or
vmset.m+vmand.mm (masked).

Diff Detail

Event Timeline

Chenbing.Zheng created this revision.Jan 4 2022, 2:26 AM
Chenbing.Zheng requested review of this revision.Jan 4 2022, 2:26 AM
Chenbing.Zheng updated this revision to Diff 397245.EditedJan 4 2022, 3:08 AM
  1. clang-format
  2. modify vmandn to vmand

Fix vmset generating error

Shouldn't you remove VPatCompareUnsignedZero from RISCVInstrInfoVPseudos.td?

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
817

This could be done by using a new version of simm5_plus1 that excludes 0 in VPatCompare_VI for the vmsltu case.

863

Same here.

Chenbing.Zheng added inline comments.Jan 4 2022, 7:44 PM
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
817

New simm5_plus1 excludes 0, and I Keep pattern "defm : VPatCompareUnsignedZero<"int_riscv_vmsltu", "PseudoVMSNE">" to match vmsltu 0,and del this two case. Understanding right ?

craig.topper added inline comments.Jan 4 2022, 7:56 PM
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
817

Remove the VPatCOmpareUnisignedZero. The vmsltu.vx will then be able to match. The 0 will select to X0.

Chenbing.Zheng retitled this revision from [RISCV] Block vmsleu.vx/vmsgeu.vi with 0 immediate in Isel to [RISCV] Block vmsltu.vx/vmsgeu.vi with 0 immediate in Isel.
Chenbing.Zheng edited the summary of this revision. (Show Details)

delete VPatCompareUnsignedZero

Chenbing.Zheng added inline comments.Jan 4 2022, 11:50 PM
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
817

I try it, but vmsleu.vi -1 still generate.
VPattern of vmsltu.vx is different from vmsltu.vi , it cause vmsltu.vx canot be match ?
So I keep these two cases, and delate VPatCompareUnsignedZero in my newest patch.

I posted an alternative version that handles vsltu.vi without RISCVISelDAGToDAG.cpp changes here https://reviews.llvm.org/D116723

I posted an alternative version that handles vsltu.vi without RISCVISelDAGToDAG.cpp changes here https://reviews.llvm.org/D116723

I read your patch, it is a good solution. I will rebase after for your patch merge into the main

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
817

This could be done by using a new version of simm5_plus1 that excludes 0 in VPatCompare_VI for the vmsltu case.

simm5_plus1 newest code in branch main. I thought is it define range -15 ~ 16 ? havn't excludes 0? or there are some new patch havn't push to main?

def simm5_plus1 : Operand<XLenVT>, ImmLeaf<XLenVT,

[{return (isInt<5>(Imm) && Imm != -16) || Imm == 16;}]> {
let ParserMatchClass = SImm5Plus1AsmOperand;
let MCOperandPredicate = [{
  int64_t Imm;
  if (MCOp.evaluateAsConstantImm(Imm))
    return (isInt<5>(Imm) && Imm != -16) || Imm == 16;
  return MCOp.isBareSymbolRef();
}];

}

Chenbing.Zheng retitled this revision from [RISCV] Block vmsltu.vx/vmsgeu.vi with 0 immediate in Isel to [RISCV] Block vmsgeu.vi with 0 immediate in Isel.
Chenbing.Zheng edited the summary of this revision. (Show Details)
craig.topper added inline comments.Jan 6 2022, 8:49 AM
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
840–841

This code was recently changed to use a macro for each case since they are only vary by instruction suffix. Please rebase.

Chenbing.Zheng marked 4 inline comments as done.Jan 6 2022, 6:48 PM
craig.topper added inline comments.Jan 6 2022, 10:22 PM
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
830
if (!IsUnsigned || CVal != 0)
  break;
IsCmpUnsignedZero = true;
890

Same

Refactor some code

Chenbing.Zheng marked 2 inline comments as done.Jan 6 2022, 10:35 PM
Chenbing.Zheng added inline comments.
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
830

done

Chenbing.Zheng marked an inline comment as done.
Chenbing.Zheng edited the summary of this revision. (Show Details)

clean code

This revision is now accepted and ready to land.Jan 10 2022, 6:11 PM
This revision was landed with ongoing or failed builds.Jan 10 2022, 7:04 PM
This revision was automatically updated to reflect the committed changes.