[RISCV] Block vmsgeu.vi with 0 immediate in Isel

[Chenbing.Zheng]

Summary

For vmsgeu.vi with 0, we know this is always true,
so we can instead it with vmset.m (unmasked) or
vmset.m+vmand.mm (masked).

[Chenbing.Zheng]

1. clang-format
2. modify vmandn to vmand

[Chenbing.Zheng]

Fix vmset generating error

[craig.topper]

Shouldn't you remove VPatCompareUnsignedZero from RISCVInstrInfoVPseudos.td?

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

817

This could be done by using a new version of simm5_plus1 that excludes 0 in VPatCompare_VI for the vmsltu case.

863

Same here.

[Chenbing.Zheng]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

817

New simm5_plus1 excludes 0, and I Keep pattern "defm : VPatCompareUnsignedZero<"int_riscv_vmsltu", "PseudoVMSNE">" to match vmsltu 0，and del this two case. Understanding right ?

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

817

Remove the VPatCOmpareUnisignedZero. The vmsltu.vx will then be able to match. The 0 will select to X0.

[Chenbing.Zheng]

delete VPatCompareUnsignedZero

[Chenbing.Zheng]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

817

I try it, but vmsleu.vi -1 still generate.
VPattern of vmsltu.vx is different from vmsltu.vi , it cause vmsltu.vx canot be match ?
So I keep these two cases, and delate VPatCompareUnsignedZero in my newest patch.

[craig.topper]

I posted an alternative version that handles vsltu.vi without RISCVISelDAGToDAG.cpp changes here https://reviews.llvm.org/D116723

[Chenbing.Zheng]

In D116584#3224373, @craig.topper wrote:

I posted an alternative version that handles vsltu.vi without RISCVISelDAGToDAG.cpp changes here https://reviews.llvm.org/D116723

I read your patch, it is a good solution. I will rebase after for your patch merge into the main

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

817

This could be done by using a new version of simm5_plus1 that excludes 0 in VPatCompare_VI for the vmsltu case.

simm5_plus1 newest code in branch main. I thought is it define range -15 ~ 16 ? havn't excludes 0? or there are some new patch havn't push to main?

def simm5_plus1 : Operand<XLenVT>, ImmLeaf<XLenVT,

[{return (isInt<5>(Imm) && Imm != -16) || Imm == 16;}]> {
let ParserMatchClass = SImm5Plus1AsmOperand;
let MCOperandPredicate = [{
  int64_t Imm;
  if (MCOp.evaluateAsConstantImm(Imm))
    return (isInt<5>(Imm) && Imm != -16) || Imm == 16;
  return MCOp.isBareSymbolRef();
}];

}

[Chenbing.Zheng]

rebase https://reviews.llvm.org/D116723

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

975

This code was recently changed to use a macro for each case since they are only vary by instruction suffix. Please rebase.

[Chenbing.Zheng]

rebase main

[Chenbing.Zheng]

clang-format

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

968

if (!IsUnsigned || CVal != 0)
  break;
IsCmpUnsignedZero = true;

1038

Same

[Chenbing.Zheng]

Refactor some code

[Chenbing.Zheng]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

968

done

[Chenbing.Zheng]

clean code

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

case ISD::MUL: {
     return;
   }
   case ISD::INTRINSIC_WO_CHAIN: {
     unsigned IntNo = Node->getConstantOperandVal(0);
     switch (IntNo) {
       // By default we do not custom select any intrinsic.
     default:
       break;
-    case Intrinsic::riscv_vmsgeu:
+    case Intrinsic::riscv_vmsltu: {
+      SDValue Src1 = Node->getOperand(1);
+      SDValue Src2 = Node->getOperand(2);
+      auto *C = dyn_cast<ConstantSDNode>(Src2);
+      if (!C || C->getSExtValue() != 0)
+        break;
+      // Only deal with vmsltu.vi v0, v1, 0
+      MVT Src1VT = Src1.getSimpleValueType();
+      unsigned VMSLEUOpcode;
+      switch (RISCVTargetLowering::getLMUL(Src1VT)) {
+      default:
+        llvm_unreachable("Unexpected LMUL!");
+      case RISCVII::VLMUL::LMUL_F8:
+        VMSLEUOpcode = RISCV::PseudoVMSLEU_VX_MF8;
+        break;
+      case RISCVII::VLMUL::LMUL_F4:
+        VMSLEUOpcode = RISCV::PseudoVMSLEU_VX_MF4;
+        break;
+      case RISCVII::VLMUL::LMUL_F2:
+        VMSLEUOpcode = RISCV::PseudoVMSLEU_VX_MF2;
+        break;
+      case RISCVII::VLMUL::LMUL_1:
+        VMSLEUOpcode = RISCV::PseudoVMSLEU_VX_M1;
+        break;
+      case RISCVII::VLMUL::LMUL_2:
+        VMSLEUOpcode = RISCV::PseudoVMSLEU_VX_M2;
+        break;
+      case RISCVII::VLMUL::LMUL_4:
+        VMSLEUOpcode = RISCV::PseudoVMSLEU_VX_M4;
+        break;
+      case RISCVII::VLMUL::LMUL_8:
+        VMSLEUOpcode = RISCV::PseudoVMSLEU_VX_M8;
+        break;
+      }
+
+      SDValue SEW = CurDAG->getTargetConstant(
+          Log2_32(Src1VT.getScalarSizeInBits()), DL, XLenVT);
+      SDValue VL;
+      selectVLOp(Node->getOperand(3), VL);
+      SDValue VLOperand = CurDAG->getRegister(RISCV::X0, XLenVT);
+
+      // Expand to vmsleu.vv v0, v1, X0
+      ReplaceNode(Node, CurDAG->getMachineNode(VMSLEUOpcode, DL, VT,
+                                               {Src1, VLOperand, VL, SEW}));
+      return;
+    }
+    case Intrinsic::riscv_vmsltu_mask: {
+      SDValue Src1 = Node->getOperand(2);
+      SDValue Src2 = Node->getOperand(3);
+      auto *C = dyn_cast<ConstantSDNode>(Src2);
+      if (!C || C->getSExtValue() != 0)
+        break;
+      // Only deal with vmsltu.vi v1, v2, 0, v0.t
+      MVT Src1VT = Src1.getSimpleValueType();
+      unsigned VMSLEUOpcode;
+      switch (RISCVTargetLowering::getLMUL(Src1VT)) {
+      default:
+        llvm_unreachable("Unexpected LMUL!");
+      case RISCVII::VLMUL::LMUL_F8:
+        VMSLEUOpcode = RISCV::PseudoVMSLEU_VX_MF8_MASK;
+        break;
+      case RISCVII::VLMUL::LMUL_F4:
+        VMSLEUOpcode = RISCV::PseudoVMSLEU_VX_MF4_MASK;
+        break;
+      case RISCVII::VLMUL::LMUL_F2:
+        VMSLEUOpcode = RISCV::PseudoVMSLEU_VX_MF2_MASK;
+        break;
+      case RISCVII::VLMUL::LMUL_1:
+        VMSLEUOpcode = RISCV::PseudoVMSLEU_VX_M1_MASK;
+        break;
+      case RISCVII::VLMUL::LMUL_2:
+        VMSLEUOpcode = RISCV::PseudoVMSLEU_VX_M2_MASK;
+        break;
+      case RISCVII::VLMUL::LMUL_4:
+        VMSLEUOpcode = RISCV::PseudoVMSLEU_VX_M4_MASK;
+        break;
+      case RISCVII::VLMUL::LMUL_8:
+        VMSLEUOpcode = RISCV::PseudoVMSLEU_VX_M8_MASK;
+        break;
+      }
+
+      SDValue SEW = CurDAG->getTargetConstant(
+          Log2_32(Src1VT.getScalarSizeInBits()), DL, XLenVT);
+      SDValue VL;
+      selectVLOp(Node->getOperand(5), VL);
+      SDValue MaskedOff = Node->getOperand(1);
+      SDValue Mask = Node->getOperand(4);
+
+      // Expand to vmsleu.vv v1, v2, X0, v0.t
+      ReplaceNode(
+          Node, CurDAG->getMachineNode(VMSLEUOpcode, DL, VT,
+                                       {MaskedOff, Src1, Src2, Mask, VL, SEW}));
+      return;
+    }
+    case Intrinsic::riscv_vmsgeu: {
+      SDValue Src1 = Node->getOperand(1);
+      SDValue Src2 = Node->getOperand(2);
+      auto *C = dyn_cast<ConstantSDNode>(Src2);
+      // Only solve vmsgeu.vi v0, v1, 0
+      if (C && C->getSExtValue() == 0) {
+        MVT Src1VT = Src1.getSimpleValueType();
+        unsigned VMSetOpcode;
+        switch (RISCVTargetLowering::getLMUL(Src1VT)) {
+        default:
+          llvm_unreachable("Unexpected LMUL!");
+        case RISCVII::VLMUL::LMUL_F8:
+          VMSetOpcode = RISCV::PseudoVMSET_M_B64;
+          break;
+        case RISCVII::VLMUL::LMUL_F4:
+          VMSetOpcode = RISCV::PseudoVMSET_M_B32;
+          break;
+        case RISCVII::VLMUL::LMUL_F2:
+          VMSetOpcode = RISCV::PseudoVMSET_M_B16;
+          break;
+        case RISCVII::VLMUL::LMUL_1:
+          VMSetOpcode = RISCV::PseudoVMSET_M_B8;
+          break;
+        case RISCVII::VLMUL::LMUL_2:
+          VMSetOpcode = RISCV::PseudoVMSET_M_B4;
+          break;
+        case RISCVII::VLMUL::LMUL_4:
+          VMSetOpcode = RISCV::PseudoVMSET_M_B2;
+          break;
+        case RISCVII::VLMUL::LMUL_8:
+          VMSetOpcode = RISCV::PseudoVMSET_M_B1;
+          break;
+        }
+
+        SDValue SEW = CurDAG->getTargetConstant(
+            Log2_32(Src1VT.getScalarSizeInBits()), DL, XLenVT);
+        SDValue VL;
+        selectVLOp(Node->getOperand(3), VL);
+
+        // Expand to vmset.m v0
+        ReplaceNode(Node, CurDAG->getMachineNode(VMSetOpcode, DL, VT, VL, SEW));
+        return;
+      }
+      // FALL THROUGH.
+      LLVM_FALLTHROUGH;
+    }
     case Intrinsic::riscv_vmsge: {
       SDValue Src1 = Node->getOperand(1);
       SDValue Src2 = Node->getOperand(2);
       // Only custom select scalar second operand.
       if (Src2.getValueType() != XLenVT)
         break;
       // Small constants are handled with patterns.
       if (auto *C = dyn_cast<ConstantSDNode>(Src2)) {
         int64_t CVal = C->getSExtValue();
         if (CVal >= -15 && CVal <= 16)
           break;
       }
       bool IsUnsigned = IntNo == Intrinsic::riscv_vmsgeu;
       MVT Src1VT = Src1.getSimpleValueType();
       unsigned VMSLTOpcode, VMNANDOpcode;
       switch (RISCVTargetLowering::getLMUL(Src1VT)) {
       default:
         llvm_unreachable("Unexpected LMUL!");
       case RISCVII::VLMUL::LMUL_F8:
         VMSLTOpcode =
             IsUnsigned ? RISCV::PseudoVMSLTU_VX_MF8 : RISCV::PseudoVMSLT_VX_MF8;
         VMNANDOpcode = RISCV::PseudoVMNAND_MM_MF8;
         break;
       case RISCVII::VLMUL::LMUL_F4:
         VMSLTOpcode =
             IsUnsigned ? RISCV::PseudoVMSLTU_VX_MF4 : RISCV::PseudoVMSLT_VX_MF4;
         VMNANDOpcode = RISCV::PseudoVMNAND_MM_MF4;
case Intrinsic::riscv_vmsge: {
       ReplaceNode(Node, CurDAG->getMachineNode(VMNANDOpcode, DL, VT,
                                                {Cmp, Cmp, VL, SEW}));
       return;
     }
     case Intrinsic::riscv_vmsgeu_mask:
     case Intrinsic::riscv_vmsge_mask: {
       SDValue Src1 = Node->getOperand(2);
       SDValue Src2 = Node->getOperand(3);
+      bool IsUnsigned = IntNo == Intrinsic::riscv_vmsgeu_mask;
+      bool IsCmpUnsignedZero = false;
       // Only custom select scalar second operand.
       if (Src2.getValueType() != XLenVT)
         break;
       // Small constants are handled with patterns.
       if (auto *C = dyn_cast<ConstantSDNode>(Src2)) {
         int64_t CVal = C->getSExtValue();
-        if (CVal >= -15 && CVal <= 16)
+        if (CVal >= -15 && CVal <= 16) {
+          if (IsUnsigned && CVal == 0)
+            IsCmpUnsignedZero = true;
+          else
             break;
         }
-      bool IsUnsigned = IntNo == Intrinsic::riscv_vmsgeu_mask;
+      }
       MVT Src1VT = Src1.getSimpleValueType();
-      unsigned VMSLTOpcode, VMSLTMaskOpcode, VMXOROpcode, VMANDNOpcode;
+      unsigned VMSLTOpcode, VMSLTMaskOpcode, VMXOROpcode, VMANDNOpcode,
+          VMSetOpcode, VMANDOpcode;
       switch (RISCVTargetLowering::getLMUL(Src1VT)) {
       default:
         llvm_unreachable("Unexpected LMUL!");
       case RISCVII::VLMUL::LMUL_F8:
         VMSLTOpcode =
             IsUnsigned ? RISCV::PseudoVMSLTU_VX_MF8 : RISCV::PseudoVMSLT_VX_MF8;
         VMSLTMaskOpcode = IsUnsigned ? RISCV::PseudoVMSLTU_VX_MF8_MASK
                                      : RISCV::PseudoVMSLT_VX_MF8_MASK;
+        VMSetOpcode = RISCV::PseudoVMSET_M_B64;
         break;
       case RISCVII::VLMUL::LMUL_F4:
         VMSLTOpcode =
             IsUnsigned ? RISCV::PseudoVMSLTU_VX_MF4 : RISCV::PseudoVMSLT_VX_MF4;
         VMSLTMaskOpcode = IsUnsigned ? RISCV::PseudoVMSLTU_VX_MF4_MASK
                                      : RISCV::PseudoVMSLT_VX_MF4_MASK;
+        VMSetOpcode = RISCV::PseudoVMSET_M_B32;
         break;
       case RISCVII::VLMUL::LMUL_F2:
         VMSLTOpcode =
             IsUnsigned ? RISCV::PseudoVMSLTU_VX_MF2 : RISCV::PseudoVMSLT_VX_MF2;
         VMSLTMaskOpcode = IsUnsigned ? RISCV::PseudoVMSLTU_VX_MF2_MASK
                                      : RISCV::PseudoVMSLT_VX_MF2_MASK;
+        VMSetOpcode = RISCV::PseudoVMSET_M_B16;
         break;
       case RISCVII::VLMUL::LMUL_1:
         VMSLTOpcode =
             IsUnsigned ? RISCV::PseudoVMSLTU_VX_M1 : RISCV::PseudoVMSLT_VX_M1;
         VMSLTMaskOpcode = IsUnsigned ? RISCV::PseudoVMSLTU_VX_M1_MASK
                                      : RISCV::PseudoVMSLT_VX_M1_MASK;
+        VMSetOpcode = RISCV::PseudoVMSET_M_B8;
         break;
       case RISCVII::VLMUL::LMUL_2:
         VMSLTOpcode =
             IsUnsigned ? RISCV::PseudoVMSLTU_VX_M2 : RISCV::PseudoVMSLT_VX_M2;
         VMSLTMaskOpcode = IsUnsigned ? RISCV::PseudoVMSLTU_VX_M2_MASK
                                      : RISCV::PseudoVMSLT_VX_M2_MASK;
+        VMSetOpcode = RISCV::PseudoVMSET_M_B4;
         break;
       case RISCVII::VLMUL::LMUL_4:
         VMSLTOpcode =
             IsUnsigned ? RISCV::PseudoVMSLTU_VX_M4 : RISCV::PseudoVMSLT_VX_M4;
         VMSLTMaskOpcode = IsUnsigned ? RISCV::PseudoVMSLTU_VX_M4_MASK
                                      : RISCV::PseudoVMSLT_VX_M4_MASK;
+        VMSetOpcode = RISCV::PseudoVMSET_M_B2;
         break;
       case RISCVII::VLMUL::LMUL_8:
         VMSLTOpcode =
             IsUnsigned ? RISCV::PseudoVMSLTU_VX_M8 : RISCV::PseudoVMSLT_VX_M8;
         VMSLTMaskOpcode = IsUnsigned ? RISCV::PseudoVMSLTU_VX_M8_MASK
                                      : RISCV::PseudoVMSLT_VX_M8_MASK;
+        VMSetOpcode = RISCV::PseudoVMSET_M_B1;
         break;
       }
       // Mask operations use the LMUL from the mask type.
       switch (RISCVTargetLowering::getLMUL(VT)) {
       default:
         llvm_unreachable("Unexpected LMUL!");
       case RISCVII::VLMUL::LMUL_F8:
         VMXOROpcode = RISCV::PseudoVMXOR_MM_MF8;
         VMANDNOpcode = RISCV::PseudoVMANDN_MM_MF8;
+        VMANDOpcode = RISCV::PseudoVMAND_MM_MF8;
         break;
       case RISCVII::VLMUL::LMUL_F4:
         VMXOROpcode = RISCV::PseudoVMXOR_MM_MF4;
         VMANDNOpcode = RISCV::PseudoVMANDN_MM_MF4;
+        VMANDOpcode = RISCV::PseudoVMAND_MM_MF4;
         break;
       case RISCVII::VLMUL::LMUL_F2:
         VMXOROpcode = RISCV::PseudoVMXOR_MM_MF2;
         VMANDNOpcode = RISCV::PseudoVMANDN_MM_MF2;
+        VMANDOpcode = RISCV::PseudoVMAND_MM_MF2;
         break;
       case RISCVII::VLMUL::LMUL_1:
         VMXOROpcode = RISCV::PseudoVMXOR_MM_M1;
         VMANDNOpcode = RISCV::PseudoVMANDN_MM_M1;
+        VMANDOpcode = RISCV::PseudoVMAND_MM_M1;
         break;
       case RISCVII::VLMUL::LMUL_2:
         VMXOROpcode = RISCV::PseudoVMXOR_MM_M2;
         VMANDNOpcode = RISCV::PseudoVMANDN_MM_M2;
+        VMANDOpcode = RISCV::PseudoVMAND_MM_M2;
         break;
       case RISCVII::VLMUL::LMUL_4:
         VMXOROpcode = RISCV::PseudoVMXOR_MM_M4;
         VMANDNOpcode = RISCV::PseudoVMANDN_MM_M4;
+        VMANDOpcode = RISCV::PseudoVMAND_MM_M4;
         break;
       case RISCVII::VLMUL::LMUL_8:
         VMXOROpcode = RISCV::PseudoVMXOR_MM_M8;
         VMANDNOpcode = RISCV::PseudoVMANDN_MM_M8;
+        VMANDOpcode = RISCV::PseudoVMAND_MM_M8;
         break;
       }
       SDValue SEW = CurDAG->getTargetConstant(
           Log2_32(Src1VT.getScalarSizeInBits()), DL, XLenVT);
       SDValue MaskSEW = CurDAG->getTargetConstant(0, DL, XLenVT);
       SDValue VL;
       selectVLOp(Node->getOperand(5), VL);
       SDValue MaskedOff = Node->getOperand(1);
       SDValue Mask = Node->getOperand(4);
+      // Expand vmsgeu.vi v1, v2, 0, v0.t to vmset v1, vmand v0, v1, v3
+      if (IsCmpUnsignedZero) {
+        SDValue VmSet =
+            SDValue(CurDAG->getMachineNode(VMSetOpcode, DL, VT, VL, SEW), 0);
+        ReplaceNode(Node, CurDAG->getMachineNode(VMANDOpcode, DL, VT,
+                                                 {Mask, VmSet, VL, MaskSEW}));
+        return;
+      }
       // If the MaskedOff value and the Mask are the same value use
       // vmslt{u}.vx vt, va, x;  vmandn.mm vd, vd, vt
       // This avoids needing to copy v0 to vd before starting the next sequence.
       if (Mask == MaskedOff) {
         SDValue Cmp = SDValue(
             CurDAG->getMachineNode(VMSLTOpcode, DL, VT, {Src1, Src2, VL, SEW}),
             0);
         ReplaceNode(Node, CurDAG->getMachineNode(VMANDNOpcode, DL, VT,

llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll

%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i16.i16(
     i32 %1)
 
   ret <vscale x 2 x i1> %a
 }
 
 define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
 ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i16_i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v10, v0
-; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT:    vmv1r.v v0, v9
-; CHECK-NEXT:    vmseq.vv v10, v8, v8, v0.t
-; CHECK-NEXT:    vmv1r.v v0, v10
+; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, mu
+; CHECK-NEXT:    vmset.m v8
+; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, mu
+; CHECK-NEXT:    vmand.mm v0, v9, v8
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16(
     <vscale x 2 x i1> %0,
     <vscale x 2 x i16> %1,
     i16 0,
     <vscale x 2 x i1> %2,
     i32 %3)
 
   ret <vscale x 2 x i1> %a
 }
 
 define <vscale x 4 x i1> @intrinsic_vmsgeu_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind {
 ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv4i16_i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT:    vmseq.vv v0, v8, v8
+; CHECK-NEXT:    vmset.m v0
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i16.i16(
     <vscale x 4 x i16> %0,
     i16 0,
     i32 %1)
 
   ret <vscale x 4 x i1> %a

llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll

%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i16.i16(
     i64 %1)
 
   ret <vscale x 2 x i1> %a
 }
 
 define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
 ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i16_i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v10, v0
-; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT:    vmv1r.v v0, v9
-; CHECK-NEXT:    vmseq.vv v10, v8, v8, v0.t
-; CHECK-NEXT:    vmv1r.v v0, v10
+; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, mu
+; CHECK-NEXT:    vmset.m v8
+; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, mu
+; CHECK-NEXT:    vmand.mm v0, v9, v8
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16(
     <vscale x 2 x i1> %0,
     <vscale x 2 x i16> %1,
     i16 0,
     <vscale x 2 x i1> %2,
     i64 %3)
 
   ret <vscale x 2 x i1> %a
 }
 
 define <vscale x 4 x i1> @intrinsic_vmsgeu_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind {
 ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv4i16_i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT:    vmseq.vv v0, v8, v8
+; CHECK-NEXT:    vmset.m v0
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i16.i16(
     <vscale x 4 x i16> %0,
     i16 0,
     i64 %1)
 
   ret <vscale x 4 x i1> %a

llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll

 }
 
 define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
 ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i16_i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v10, v0
 ; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, mu
 ; CHECK-NEXT:    vmv1r.v v0, v9
-; CHECK-NEXT:    vmsne.vv v10, v8, v8, v0.t
+; CHECK-NEXT:    vmsleu.vx v10, v8, zero, v0.t
 ; CHECK-NEXT:    vmv1r.v v0, v10
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16.i16(
     <vscale x 2 x i1> %0,
     <vscale x 2 x i16> %1,
     i16 0,
     <vscale x 2 x i1> %2,
     i32 %3)
 
   ret <vscale x 2 x i1> %a
 }
 
 define <vscale x 4 x i1> @intrinsic_vmsltu_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind {
 ; CHECK-LABEL: intrinsic_vmsltu_vi_nxv4i16_i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT:    vmsne.vv v0, v8, v8
+; CHECK-NEXT:    vmsleu.vx v0, v8, zero
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i16.i16(
     <vscale x 4 x i16> %0,
     i16 0,
     i32 %1)
 
   ret <vscale x 4 x i1> %a

llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll

 }
 
 define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
 ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i16_i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v10, v0
 ; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, mu
 ; CHECK-NEXT:    vmv1r.v v0, v9
-; CHECK-NEXT:    vmsne.vv v10, v8, v8, v0.t
+; CHECK-NEXT:    vmsleu.vx v10, v8, zero, v0.t
 ; CHECK-NEXT:    vmv1r.v v0, v10
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16.i16(
     <vscale x 2 x i1> %0,
     <vscale x 2 x i16> %1,
     i16 0,
     <vscale x 2 x i1> %2,
     i64 %3)
 
   ret <vscale x 2 x i1> %a
 }
 
 define <vscale x 4 x i1> @intrinsic_vmsltu_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind {
 ; CHECK-LABEL: intrinsic_vmsltu_vi_nxv4i16_i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT:    vmsne.vv v0, v8, v8
+; CHECK-NEXT:    vmsleu.vx v0, v8, zero
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i16.i16(
     <vscale x 4 x i16> %0,
     i16 0,
     i64 %1)
 
   ret <vscale x 4 x i1> %a