[MIPS] Add FPU Delay Slot for MIPS1/2/3

[overdrivenpotato]

Summary

MIPS I, II, and III have delay slots for floating point comparisons and floating point register transfers (mtc1, mfc1). Currently, these are not taken into account and thus broken code may be generated on these targets. This patch inserts nops as necessary, while attempting to leave the current instruction if it is safe to stay.

The tests in this patch were updated by @sajattack

Sources:

https://gcc.gnu.org/legacy-ml/gcc-patches/2003-05/msg01601.html
https://gcc.gnu.org/legacy-ml/gcc-patches/2003-05/msg01605.html
https://github.com/gcc-mirror/gcc/blob/16e2427f50c208dfe07d07f18009969502c25dc8/gcc/config/mips/mips.h#L1282
"See MIPS Run" Textbook: https://user-images.githubusercontent.com/1562711/144544253-de268f41-d808-4076-a500-e2cdba7f4294.png
MIPS R4000 Manual: https://user-images.githubusercontent.com/1562711/144544877-8896b4e9-3127-45a6-99d7-48b53a9b35e6.png

[atanasyan]

LGTM with some nits.

llvm/lib/Target/Mips/MipsInstrInfo.cpp

576

Remove curly brackets here.

590

You can use std::tie here and provide meaningful names instead of Rw.first and Rw.second.

593

Remove curly brackets here.

[overdrivenpotato]

Fixed requested nits

[djtodoro]

llvm/lib/Target/Mips/MipsBranchExpansion.cpp

866

This code is being copied from handleForbiddenSlot() (most of it, actually). Can we factor/move the common code into a function/predicate?

llvm/lib/Target/Mips/MipsInstrInfo.cpp

588

an early exit here?

if (!Op.isReg())
  continue;

[overdrivenpotato]

Fixed remaining nits and also added support for double precision FPU delay slots.

[djtodoro]

lgtm, thanks

[djtodoro]

Please let me know if you need help with committing this (If you don't have the permission, I can do it for you).

[overdrivenpotato]

Yes please, I don’t have commit access. Can you commit as Marko Mijalkovic <[e-mail]>?

[djtodoro]

In D115127#3176007, @overdrivenpotato wrote:

Yes please, I don’t have commit access. Can you commit as Marko Mijalkovic <[e-mail]>?

We usually add "Patch by " at the end of the commit message.

[jrtc27]

In D115127#3176039, @djtodoro wrote:

In D115127#3176007, @overdrivenpotato wrote:

Yes please, I don’t have commit access. Can you commit as Marko Mijalkovic <[e-mail]>?

We usually add "Patch by " at the end of the commit message.

That's not the official way to do it since we migrated to Git; see https://llvm.org/docs/DeveloperPolicy.html#attribution-of-changes which says to set the author field to the actual author.

[djtodoro]

In D115127#3176306, @jrtc27 wrote:

In D115127#3176039, @djtodoro wrote:

In D115127#3176007, @overdrivenpotato wrote:

Yes please, I don’t have commit access. Can you commit as Marko Mijalkovic <[e-mail]>?

We usually add "Patch by " at the end of the commit message.

That's not the official way to do it since we migrated to Git; see https://llvm.org/docs/DeveloperPolicy.html#attribution-of-changes which says to set the author field to the actual author.

Thanks for pointing that out!

llvm/lib/Target/Mips/MipsBranchExpansion.cpp

 /// to fit into its immediate field, it has to be expanded to another
 /// instruction or series of instructions.
 ///
 /// FIXME: Fix pc-region jump instructions which cross 256MB segment boundaries.
 /// TODO: Handle out of range bc, b (pseudo) instructions.
 ///
 /// Regarding compact branch hazard prevention:
 ///
-/// Hazards handled: forbidden slots for MIPSR6.
+/// Hazards handled: forbidden slots for MIPSR6, FPU slots for MIPS3 and below.
 ///
 /// A forbidden slot hazard occurs when a compact branch instruction is executed
 /// and the adjacent instruction in memory is a control transfer instruction
 /// such as a branch or jump, ERET, ERETNC, DERET, WAIT and PAUSE.
 ///
 /// For example:
 ///
 /// 0x8004      bnec    a1,v0,<P+0x18>
private:
   void initMBBInfo();
   int64_t computeOffset(const MachineInstr *Br);
   uint64_t computeOffsetFromTheBeginning(int MBB);
   void replaceBranch(MachineBasicBlock &MBB, Iter Br, const DebugLoc &DL,
                      MachineBasicBlock *MBBOpnd);
   bool buildProperJumpMI(MachineBasicBlock *MBB,
                          MachineBasicBlock::iterator Pos, DebugLoc DL);
   void expandToLongBranch(MBBInfo &Info);
+  template <typename Pred, typename Safe>
+  bool handleSlot(Pred Predicate, Safe SafeInSlot);
   bool handleForbiddenSlot();
+  bool handleFPUDelaySlot();
   bool handlePossibleLongBranch();
 
   const MipsSubtarget *STI;
   const MipsInstrInfo *TII;
 
   MachineFunction *MFp;
   SmallVector<MBBInfo, 16> MBBInfos;
   bool IsPIC;
static void emitGPDisp(MachineFunction &F, const MipsInstrInfo *TII) {
   BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::V0)
       .addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI);
   BuildMI(MBB, I, DL, TII->get(Mips::ADDiu), Mips::V0)
       .addReg(Mips::V0)
       .addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO);
   MBB.removeLiveIn(Mips::V0);
 }
 
-bool MipsBranchExpansion::handleForbiddenSlot() {
-  // Forbidden slot hazards are only defined for MIPSR6 but not microMIPSR6.
-  if (!STI->hasMips32r6() || STI->inMicroMipsMode())
-    return false;
-
+template <typename Pred, typename Safe>
+bool MipsBranchExpansion::handleSlot(Pred Predicate, Safe SafeInSlot) {
   bool Changed = false;
 
   for (MachineFunction::iterator FI = MFp->begin(); FI != MFp->end(); ++FI) {
     for (Iter I = FI->begin(); I != FI->end(); ++I) {
 
-      // Forbidden slot hazard handling. Use lookahead over state.
-      if (!TII->HasForbiddenSlot(*I))
+      // Delay slot hazard handling. Use lookahead over state.
+      if (!Predicate(*I))
         continue;
 
-      Iter Inst;
+      Iter IInSlot;
       bool LastInstInFunction =
           std::next(I) == FI->end() && std::next(FI) == MFp->end();
       if (!LastInstInFunction) {
         std::pair<Iter, bool> Res = getNextMachineInstr(std::next(I), &*FI);
         LastInstInFunction |= Res.second;
-        Inst = Res.first;
+        IInSlot = Res.first;
       }
 
-      if (LastInstInFunction || !TII->SafeInForbiddenSlot(*Inst)) {
+      if (LastInstInFunction || !SafeInSlot(*IInSlot, *I)) {
 
         MachineBasicBlock::instr_iterator Iit = I->getIterator();
         if (std::next(Iit) == FI->end() ||
             std::next(Iit)->getOpcode() != Mips::NOP) {
           Changed = true;
           MIBundleBuilder(&*I).append(
               BuildMI(*MFp, I->getDebugLoc(), TII->get(Mips::NOP)));
           NumInsertedNops++;
         }
       }
     }
   }
 
   return Changed;
 }
 
+bool MipsBranchExpansion::handleForbiddenSlot() {
+  // Forbidden slot hazards are only defined for MIPSR6 but not microMIPSR6.
+  if (!STI->hasMips32r6() || STI->inMicroMipsMode())
+    return false;
+
+  return handleSlot(
+      [this](auto &I) -> bool { return TII->HasForbiddenSlot(I); },
+      [this](auto &IInSlot, auto &I) -> bool {
+        return TII->SafeInForbiddenSlot(IInSlot);
+      });
+}
+
+bool MipsBranchExpansion::handleFPUDelaySlot() {
+  // FPU delay slots are only defined for MIPS3 and below.
+  if (STI->hasMips32() || STI->hasMips4())
+    return false;
+
+  return handleSlot([this](auto &I) -> bool { return TII->HasFPUDelaySlot(I); },
+                    [this](auto &IInSlot, auto &I) -> bool {
+                      return TII->SafeInFPUDelaySlot(IInSlot, I);
+                    });
+}
+
 bool MipsBranchExpansion::handlePossibleLongBranch() {
   if (STI->inMips16Mode() || !STI->enableLongBranchPass())
     return false;
 
   if (SkipLongBranch)
     return false;
 
   bool EverMadeChange = false, MadeChange = true;
while (MadeChange) {
     }
 
     MFp->RenumberBlocks();
   }
 
   return EverMadeChange;
 }
 
 bool MipsBranchExpansion::runOnMachineFunction(MachineFunction &MF) {
   const TargetMachine &TM = MF.getTarget();
   IsPIC = TM.isPositionIndependent();
   ABI = static_cast<const MipsTargetMachine &>(TM).getABI();
   STI = &static_cast<const MipsSubtarget &>(MF.getSubtarget());
   TII = static_cast<const MipsInstrInfo *>(STI->getInstrInfo());
 
   if (IsPIC && ABI.IsO32() &&
       MF.getInfo<MipsFunctionInfo>()->globalBaseRegSet())
     emitGPDisp(MF, TII);
 
   MFp = &MF;
 
   ForceLongBranchFirstPass = ForceLongBranch;
   // Run these two at least once
   bool longBranchChanged = handlePossibleLongBranch();
   bool forbiddenSlotChanged = handleForbiddenSlot();
+  bool fpuDelaySlotChanged = handleFPUDelaySlot();
 
-  bool Changed = longBranchChanged || forbiddenSlotChanged;
+  bool Changed =
+      longBranchChanged || forbiddenSlotChanged || fpuDelaySlotChanged;
 
   // Then run them alternatively while there are changes
   while (forbiddenSlotChanged) {
     longBranchChanged = handlePossibleLongBranch();
-    if (!longBranchChanged)
+    fpuDelaySlotChanged = handleFPUDelaySlot();
+    if (!longBranchChanged && !fpuDelaySlotChanged)
       break;
     forbiddenSlotChanged = handleForbiddenSlot();
   }
 
   return Changed;
 }

llvm/lib/Target/Mips/MipsInstrInfo.h

public:
 
   /// Determine if the branch target is in range.
   bool isBranchOffsetInRange(unsigned BranchOpc,
                              int64_t BrOffset) const override;
 
   /// Predicate to determine if an instruction can go in a forbidden slot.
   bool SafeInForbiddenSlot(const MachineInstr &MI) const;
 
+  /// Predicate to determine if an instruction can go in an FPU delay slot.
+  bool SafeInFPUDelaySlot(const MachineInstr &MIInSlot,
+                          const MachineInstr &FPUMI) const;
+
   /// Predicate to determine if an instruction has a forbidden slot.
   bool HasForbiddenSlot(const MachineInstr &MI) const;
 
+  /// Predicate to determine if an instruction has an FPU delay slot.
+  bool HasFPUDelaySlot(const MachineInstr &MI) const;
+
   /// Insert nop instruction when hazard condition is found
   void insertNoop(MachineBasicBlock &MBB,
                   MachineBasicBlock::iterator MI) const override;
 
   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
   /// such, whenever a client has an instance of instruction info, it should
   /// always be able to get register info as well (through this method).
   virtual const MipsRegisterInfo &getRegisterInfo() const = 0;

llvm/lib/Target/Mips/MipsInstrInfo.cpp

 /// as unsafe as well.
 bool MipsInstrInfo::SafeInForbiddenSlot(const MachineInstr &MI) const {
   if (MI.isInlineAsm())
     return false;
 
   return (MI.getDesc().TSFlags & MipsII::IsCTI) == 0;
 }
 
+bool MipsInstrInfo::SafeInFPUDelaySlot(const MachineInstr &MIInSlot,
+                                       const MachineInstr &FPUMI) const {
+  if (MIInSlot.isInlineAsm())
+    return false;
+
+  if (HasFPUDelaySlot(MIInSlot))
+    return false;
+
+  switch (MIInSlot.getOpcode()) {
+  case Mips::BC1F:
+  case Mips::BC1FL:
+  case Mips::BC1T:
+  case Mips::BC1TL:
+    return false;
+  }
+
+  for (const MachineOperand &Op : FPUMI.defs()) {
+    if (!Op.isReg())
+      continue;
+
+    bool Reads, Writes;
+    std::tie(Reads, Writes) = MIInSlot.readsWritesVirtualRegister(Op.getReg());
+
+    if (Reads || Writes)
+      return false;
+  }
+
+  return true;
+}
+
 /// Predicate for distingushing instructions that have forbidden slots.
 bool MipsInstrInfo::HasForbiddenSlot(const MachineInstr &MI) const {
   return (MI.getDesc().TSFlags & MipsII::HasForbiddenSlot) != 0;
 }
 
+/// Predicate for distingushing instructions that have FPU delay slots.
+bool MipsInstrInfo::HasFPUDelaySlot(const MachineInstr &MI) const {
+  switch (MI.getOpcode()) {
+  case Mips::MTC1:
+  case Mips::MFC1:
+  case Mips::MTC1_D64:
+  case Mips::MFC1_D64:
+  case Mips::DMTC1:
+  case Mips::DMFC1:
+  case Mips::FCMP_S32:
+  case Mips::FCMP_D32:
+  case Mips::FCMP_D64:
+    return true;
+
+  default:
+    return false;
+  }
+}
+
 /// Return the number of bytes of code the specified instruction may be.
 unsigned MipsInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
   switch (MI.getOpcode()) {
   default:
     return MI.getDesc().getSize();
   case  TargetOpcode::INLINEASM:
   case  TargetOpcode::INLINEASM_BR: {       // Inline Asm: Variable size.
     const MachineFunction *MF = MI.getParent()->getParent();

llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll

entry:
   %r = select i1 %s, double %x, double %y
   ret double %r
 }
 
 define double @tst_select_fcmp_olt_double(double %x, double %y) {
 ; M2-LABEL: tst_select_fcmp_olt_double:
 ; M2:       # %bb.0: # %entry
 ; M2-NEXT:    c.olt.d $f12, $f14
+; M2-NEXT:    nop
 ; M2-NEXT:    bc1t $BB2_2
 ; M2-NEXT:    mov.d $f0, $f12
 ; M2-NEXT:  # %bb.1: # %entry
 ; M2-NEXT:    mov.d $f0, $f14
 ; M2-NEXT:  $BB2_2: # %entry
 ; M2-NEXT:    jr $ra
 ; M2-NEXT:    nop
 ;

 ; 32R6-NEXT:    mfc1 $1, $f0
 ; 32R6-NEXT:    mtc1 $1, $f0
 ; 32R6-NEXT:    jr $ra
 ; 32R6-NEXT:    sel.d $f0, $f14, $f12
 ;
 ; M3-LABEL: tst_select_fcmp_olt_double:
 ; M3:       # %bb.0: # %entry
 ; M3-NEXT:    c.olt.d $f12, $f13
+; M3-NEXT:    nop
 ; M3-NEXT:    bc1t .LBB2_2
 ; M3-NEXT:    mov.d $f0, $f12
 ; M3-NEXT:  # %bb.1: # %entry
 ; M3-NEXT:    mov.d $f0, $f13
 ; M3-NEXT:  .LBB2_2: # %entry
 ; M3-NEXT:    jr $ra
 ; M3-NEXT:    nop
 ;
entry:
   %r = select i1 %s, double %x, double %y
   ret double %r
 }
 
 define double @tst_select_fcmp_ole_double(double %x, double %y) {
 ; M2-LABEL: tst_select_fcmp_ole_double:
 ; M2:       # %bb.0: # %entry
 ; M2-NEXT:    c.ole.d $f12, $f14
+; M2-NEXT:    nop
 ; M2-NEXT:    bc1t $BB3_2
 ; M2-NEXT:    mov.d $f0, $f12
 ; M2-NEXT:  # %bb.1: # %entry
 ; M2-NEXT:    mov.d $f0, $f14
 ; M2-NEXT:  $BB3_2: # %entry
 ; M2-NEXT:    jr $ra
 ; M2-NEXT:    nop
 ;

 ; 32R6-NEXT:    mfc1 $1, $f0
 ; 32R6-NEXT:    mtc1 $1, $f0
 ; 32R6-NEXT:    jr $ra
 ; 32R6-NEXT:    sel.d $f0, $f14, $f12
 ;
 ; M3-LABEL: tst_select_fcmp_ole_double:
 ; M3:       # %bb.0: # %entry
 ; M3-NEXT:    c.ole.d $f12, $f13
+; M3-NEXT:    nop
 ; M3-NEXT:    bc1t .LBB3_2
 ; M3-NEXT:    mov.d $f0, $f12
 ; M3-NEXT:  # %bb.1: # %entry
 ; M3-NEXT:    mov.d $f0, $f13
 ; M3-NEXT:  .LBB3_2: # %entry
 ; M3-NEXT:    jr $ra
 ; M3-NEXT:    nop
 ;
entry:
   %r = select i1 %s, double %x, double %y
   ret double %r
 }
 
 define double @tst_select_fcmp_ogt_double(double %x, double %y) {
 ; M2-LABEL: tst_select_fcmp_ogt_double:
 ; M2:       # %bb.0: # %entry
 ; M2-NEXT:    c.ule.d $f12, $f14
+; M2-NEXT:    nop
 ; M2-NEXT:    bc1f $BB4_2
 ; M2-NEXT:    mov.d $f0, $f12
 ; M2-NEXT:  # %bb.1: # %entry
 ; M2-NEXT:    mov.d $f0, $f14
 ; M2-NEXT:  $BB4_2: # %entry
 ; M2-NEXT:    jr $ra
 ; M2-NEXT:    nop
 ;

 ; 32R6-NEXT:    mfc1 $1, $f0
 ; 32R6-NEXT:    mtc1 $1, $f0
 ; 32R6-NEXT:    jr $ra
 ; 32R6-NEXT:    sel.d $f0, $f14, $f12
 ;
 ; M3-LABEL: tst_select_fcmp_ogt_double:
 ; M3:       # %bb.0: # %entry
 ; M3-NEXT:    c.ule.d $f12, $f13
+; M3-NEXT:    nop
 ; M3-NEXT:    bc1f .LBB4_2
 ; M3-NEXT:    mov.d $f0, $f12
 ; M3-NEXT:  # %bb.1: # %entry
 ; M3-NEXT:    mov.d $f0, $f13
 ; M3-NEXT:  .LBB4_2: # %entry
 ; M3-NEXT:    jr $ra
 ; M3-NEXT:    nop
 ;
entry:
   %r = select i1 %s, double %x, double %y
   ret double %r
 }
 
 define double @tst_select_fcmp_oge_double(double %x, double %y) {
 ; M2-LABEL: tst_select_fcmp_oge_double:
 ; M2:       # %bb.0: # %entry
 ; M2-NEXT:    c.ult.d $f12, $f14
+; M2-NEXT:    nop
 ; M2-NEXT:    bc1f $BB5_2
 ; M2-NEXT:    mov.d $f0, $f12
 ; M2-NEXT:  # %bb.1: # %entry
 ; M2-NEXT:    mov.d $f0, $f14
 ; M2-NEXT:  $BB5_2: # %entry
 ; M2-NEXT:    jr $ra
 ; M2-NEXT:    nop
 ;

 ; 32R6-NEXT:    mfc1 $1, $f0
 ; 32R6-NEXT:    mtc1 $1, $f0
 ; 32R6-NEXT:    jr $ra
 ; 32R6-NEXT:    sel.d $f0, $f14, $f12
 ;
 ; M3-LABEL: tst_select_fcmp_oge_double:
 ; M3:       # %bb.0: # %entry
 ; M3-NEXT:    c.ult.d $f12, $f13
+; M3-NEXT:    nop
 ; M3-NEXT:    bc1f .LBB5_2
 ; M3-NEXT:    mov.d $f0, $f12
 ; M3-NEXT:  # %bb.1: # %entry
 ; M3-NEXT:    mov.d $f0, $f13
 ; M3-NEXT:  .LBB5_2: # %entry
 ; M3-NEXT:    jr $ra
 ; M3-NEXT:    nop
 ;
entry:
   %r = select i1 %s, double %x, double %y
   ret double %r
 }
 
 define double @tst_select_fcmp_oeq_double(double %x, double %y) {
 ; M2-LABEL: tst_select_fcmp_oeq_double:
 ; M2:       # %bb.0: # %entry
 ; M2-NEXT:    c.eq.d $f12, $f14
+; M2-NEXT:    nop
 ; M2-NEXT:    bc1t $BB6_2
 ; M2-NEXT:    mov.d $f0, $f12
 ; M2-NEXT:  # %bb.1: # %entry
 ; M2-NEXT:    mov.d $f0, $f14
 ; M2-NEXT:  $BB6_2: # %entry
 ; M2-NEXT:    jr $ra
 ; M2-NEXT:    nop
 ;

 ; 32R6-NEXT:    mfc1 $1, $f0
 ; 32R6-NEXT:    mtc1 $1, $f0
 ; 32R6-NEXT:    jr $ra
 ; 32R6-NEXT:    sel.d $f0, $f14, $f12
 ;
 ; M3-LABEL: tst_select_fcmp_oeq_double:
 ; M3:       # %bb.0: # %entry
 ; M3-NEXT:    c.eq.d $f12, $f13
+; M3-NEXT:    nop
 ; M3-NEXT:    bc1t .LBB6_2
 ; M3-NEXT:    mov.d $f0, $f12
 ; M3-NEXT:  # %bb.1: # %entry
 ; M3-NEXT:    mov.d $f0, $f13
 ; M3-NEXT:  .LBB6_2: # %entry
 ; M3-NEXT:    jr $ra
 ; M3-NEXT:    nop
 ;
entry:
   %r = select i1 %s, double %x, double %y
   ret double %r
 }
 
 define double @tst_select_fcmp_one_double(double %x, double %y) {
 ; M2-LABEL: tst_select_fcmp_one_double:
 ; M2:       # %bb.0: # %entry
 ; M2-NEXT:    c.ueq.d $f12, $f14
+; M2-NEXT:    nop
 ; M2-NEXT:    bc1f $BB7_2
 ; M2-NEXT:    mov.d $f0, $f12
 ; M2-NEXT:  # %bb.1: # %entry
 ; M2-NEXT:    mov.d $f0, $f14
 ; M2-NEXT:  $BB7_2: # %entry
 ; M2-NEXT:    jr $ra
 ; M2-NEXT:    nop
 ;

 ; 32R6-NEXT:    not $1, $1
 ; 32R6-NEXT:    mtc1 $1, $f0
 ; 32R6-NEXT:    jr $ra
 ; 32R6-NEXT:    sel.d $f0, $f14, $f12
 ;
 ; M3-LABEL: tst_select_fcmp_one_double:
 ; M3:       # %bb.0: # %entry
 ; M3-NEXT:    c.ueq.d $f12, $f13
+; M3-NEXT:    nop
 ; M3-NEXT:    bc1f .LBB7_2
 ; M3-NEXT:    mov.d $f0, $f12
 ; M3-NEXT:  # %bb.1: # %entry
 ; M3-NEXT:    mov.d $f0, $f13
 ; M3-NEXT:  .LBB7_2: # %entry
 ; M3-NEXT:    jr $ra
 ; M3-NEXT:    nop
 ;

llvm/test/CodeGen/Mips/llvm-ir/select-flt.ll

entry:
   %r = select i1 %s, float %x, float %y
   ret float %r
 }
 
 define float @tst_select_fcmp_olt_float(float %x, float %y) {
 ; M2-LABEL: tst_select_fcmp_olt_float:
 ; M2:       # %bb.0: # %entry
 ; M2-NEXT:    c.olt.s $f12, $f14
+; M2-NEXT:    nop
 ; M2-NEXT:    bc1t $BB2_2
 ; M2-NEXT:    mov.s $f0, $f12
 ; M2-NEXT:  # %bb.1: # %entry
 ; M2-NEXT:    mov.s $f0, $f14
 ; M2-NEXT:  $BB2_2: # %entry
 ; M2-NEXT:    jr $ra
 ; M2-NEXT:    nop
 ;

 ; 32R6:       # %bb.0: # %entry
 ; 32R6-NEXT:    cmp.lt.s $f0, $f12, $f14
 ; 32R6-NEXT:    jr $ra
 ; 32R6-NEXT:    sel.s $f0, $f14, $f12
 ;
 ; M3-LABEL: tst_select_fcmp_olt_float:
 ; M3:       # %bb.0: # %entry
 ; M3-NEXT:    c.olt.s $f12, $f13
+; M3-NEXT:    nop
 ; M3-NEXT:    bc1t .LBB2_2
 ; M3-NEXT:    mov.s $f0, $f12
 ; M3-NEXT:  # %bb.1: # %entry
 ; M3-NEXT:    mov.s $f0, $f13
 ; M3-NEXT:  .LBB2_2: # %entry
 ; M3-NEXT:    jr $ra
 ; M3-NEXT:    nop
 ;
entry:
   %r = select i1 %s, float %x, float %y
   ret float %r
 }
 
 define float @tst_select_fcmp_ole_float(float %x, float %y) {
 ; M2-LABEL: tst_select_fcmp_ole_float:
 ; M2:       # %bb.0: # %entry
 ; M2-NEXT:    c.ole.s $f12, $f14
+; M2-NEXT:    nop
 ; M2-NEXT:    bc1t $BB3_2
 ; M2-NEXT:    mov.s $f0, $f12
 ; M2-NEXT:  # %bb.1: # %entry
 ; M2-NEXT:    mov.s $f0, $f14
 ; M2-NEXT:  $BB3_2: # %entry
 ; M2-NEXT:    jr $ra
 ; M2-NEXT:    nop
 ;

 ; 32R6:       # %bb.0: # %entry
 ; 32R6-NEXT:    cmp.le.s $f0, $f12, $f14
 ; 32R6-NEXT:    jr $ra
 ; 32R6-NEXT:    sel.s $f0, $f14, $f12
 ;
 ; M3-LABEL: tst_select_fcmp_ole_float:
 ; M3:       # %bb.0: # %entry
 ; M3-NEXT:    c.ole.s $f12, $f13
+; M3-NEXT:    nop
 ; M3-NEXT:    bc1t .LBB3_2
 ; M3-NEXT:    mov.s $f0, $f12
 ; M3-NEXT:  # %bb.1: # %entry
 ; M3-NEXT:    mov.s $f0, $f13
 ; M3-NEXT:  .LBB3_2: # %entry
 ; M3-NEXT:    jr $ra
 ; M3-NEXT:    nop
 ;
entry:
   %r = select i1 %s, float %x, float %y
   ret float %r
 }
 
 define float @tst_select_fcmp_ogt_float(float %x, float %y) {
 ; M2-LABEL: tst_select_fcmp_ogt_float:
 ; M2:       # %bb.0: # %entry
 ; M2-NEXT:    c.ule.s $f12, $f14
+; M2-NEXT:    nop
 ; M2-NEXT:    bc1f $BB4_2
 ; M2-NEXT:    mov.s $f0, $f12
 ; M2-NEXT:  # %bb.1: # %entry
 ; M2-NEXT:    mov.s $f0, $f14
 ; M2-NEXT:  $BB4_2: # %entry
 ; M2-NEXT:    jr $ra
 ; M2-NEXT:    nop
 ;

 ; 32R6:       # %bb.0: # %entry
 ; 32R6-NEXT:    cmp.lt.s $f0, $f14, $f12
 ; 32R6-NEXT:    jr $ra
 ; 32R6-NEXT:    sel.s $f0, $f14, $f12
 ;
 ; M3-LABEL: tst_select_fcmp_ogt_float:
 ; M3:       # %bb.0: # %entry
 ; M3-NEXT:    c.ule.s $f12, $f13
+; M3-NEXT:    nop
 ; M3-NEXT:    bc1f .LBB4_2
 ; M3-NEXT:    mov.s $f0, $f12
 ; M3-NEXT:  # %bb.1: # %entry
 ; M3-NEXT:    mov.s $f0, $f13
 ; M3-NEXT:  .LBB4_2: # %entry
 ; M3-NEXT:    jr $ra
 ; M3-NEXT:    nop
 ;
entry:
   %r = select i1 %s, float %x, float %y
   ret float %r
 }
 
 define float @tst_select_fcmp_oge_float(float %x, float %y) {
 ; M2-LABEL: tst_select_fcmp_oge_float:
 ; M2:       # %bb.0: # %entry
 ; M2-NEXT:    c.ult.s $f12, $f14
+; M2-NEXT:    nop
 ; M2-NEXT:    bc1f $BB5_2
 ; M2-NEXT:    mov.s $f0, $f12
 ; M2-NEXT:  # %bb.1: # %entry
 ; M2-NEXT:    mov.s $f0, $f14
 ; M2-NEXT:  $BB5_2: # %entry
 ; M2-NEXT:    jr $ra
 ; M2-NEXT:    nop
 ;

 ; 32R6:       # %bb.0: # %entry
 ; 32R6-NEXT:    cmp.le.s $f0, $f14, $f12
 ; 32R6-NEXT:    jr $ra
 ; 32R6-NEXT:    sel.s $f0, $f14, $f12
 ;
 ; M3-LABEL: tst_select_fcmp_oge_float:
 ; M3:       # %bb.0: # %entry
 ; M3-NEXT:    c.ult.s $f12, $f13
+; M3-NEXT:    nop
 ; M3-NEXT:    bc1f .LBB5_2
 ; M3-NEXT:    mov.s $f0, $f12
 ; M3-NEXT:  # %bb.1: # %entry
 ; M3-NEXT:    mov.s $f0, $f13
 ; M3-NEXT:  .LBB5_2: # %entry
 ; M3-NEXT:    jr $ra
 ; M3-NEXT:    nop
 ;
entry:
   %r = select i1 %s, float %x, float %y
   ret float %r
 }
 
 define float @tst_select_fcmp_oeq_float(float %x, float %y) {
 ; M2-LABEL: tst_select_fcmp_oeq_float:
 ; M2:       # %bb.0: # %entry
 ; M2-NEXT:    c.eq.s $f12, $f14
+; M2-NEXT:    nop
 ; M2-NEXT:    bc1t $BB6_2
 ; M2-NEXT:    mov.s $f0, $f12
 ; M2-NEXT:  # %bb.1: # %entry
 ; M2-NEXT:    mov.s $f0, $f14
 ; M2-NEXT:  $BB6_2: # %entry
 ; M2-NEXT:    jr $ra
 ; M2-NEXT:    nop
 ;

 ; 32R6:       # %bb.0: # %entry
 ; 32R6-NEXT:    cmp.eq.s $f0, $f12, $f14
 ; 32R6-NEXT:    jr $ra
 ; 32R6-NEXT:    sel.s $f0, $f14, $f12
 ;
 ; M3-LABEL: tst_select_fcmp_oeq_float:
 ; M3:       # %bb.0: # %entry
 ; M3-NEXT:    c.eq.s $f12, $f13
+; M3-NEXT:    nop
 ; M3-NEXT:    bc1t .LBB6_2
 ; M3-NEXT:    mov.s $f0, $f12
 ; M3-NEXT:  # %bb.1: # %entry
 ; M3-NEXT:    mov.s $f0, $f13
 ; M3-NEXT:  .LBB6_2: # %entry
 ; M3-NEXT:    jr $ra
 ; M3-NEXT:    nop
 ;
entry:
   %r = select i1 %s, float %x, float %y
   ret float %r
 }
 
 define float @tst_select_fcmp_one_float(float %x, float %y) {
 ; M2-LABEL: tst_select_fcmp_one_float:
 ; M2:       # %bb.0: # %entry
 ; M2-NEXT:    c.ueq.s $f12, $f14
+; M2-NEXT:    nop
 ; M2-NEXT:    bc1f $BB7_2
 ; M2-NEXT:    mov.s $f0, $f12
 ; M2-NEXT:  # %bb.1: # %entry
 ; M2-NEXT:    mov.s $f0, $f14
 ; M2-NEXT:  $BB7_2: # %entry
 ; M2-NEXT:    jr $ra
 ; M2-NEXT:    nop
 ;

 ; 32R6-NEXT:    not $1, $1
 ; 32R6-NEXT:    mtc1 $1, $f0
 ; 32R6-NEXT:    jr $ra
 ; 32R6-NEXT:    sel.s $f0, $f14, $f12
 ;
 ; M3-LABEL: tst_select_fcmp_one_float:
 ; M3:       # %bb.0: # %entry
 ; M3-NEXT:    c.ueq.s $f12, $f13
+; M3-NEXT:    nop
 ; M3-NEXT:    bc1f .LBB7_2
 ; M3-NEXT:    mov.s $f0, $f12
 ; M3-NEXT:  # %bb.1: # %entry
 ; M3-NEXT:    mov.s $f0, $f13
 ; M3-NEXT:  .LBB7_2: # %entry
 ; M3-NEXT:    jr $ra
 ; M3-NEXT:    nop
 ;