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[MachineVerifier] Make TiedOpsRewritten computable in MIRParser
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Authored by lkail on Nov 24 2021, 10:36 PM.

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Summary

This patch is to address post-commit comment https://reviews.llvm.org/D80538#anchor-inline-1091625, which make the constraint stronger based on what https://reviews.llvm.org/D80538 does, i.e., "TiedOpsRewritten is set iff leave-ssa and all tied operands share the same register".

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Event Timeline

lkail created this revision.Nov 24 2021, 10:36 PM
lkail requested review of this revision.Nov 24 2021, 10:36 PM
Herald added a project: Restricted Project. · View Herald TranscriptNov 24 2021, 10:36 PM
lkail edited the summary of this revision. (Show Details)Nov 24 2021, 10:43 PM
lkail updated this revision to Diff 389664.Nov 24 2021, 11:24 PM
lkail edited the summary of this revision. (Show Details)

Add unittests.

lkail retitled this revision from [MachineVerifier][RFC] Make TiedOpsRewritten computable in MIRParser to [MachineVerifier] Make TiedOpsRewritten computable in MIRParser.Nov 28 2021, 10:22 PM
lkail edited the summary of this revision. (Show Details)
MatzeB accepted this revision.Dec 2 2021, 11:38 AM

LGTM, thanks!

llvm/lib/CodeGen/MIRParser/MIRParser.cpp
377–381

Could we just handle the value independently from SSA to make the code more uniform? Should make the code slightly easier to understand (even though techically it can indeed never be true in SSA).

This revision is now accepted and ready to land.Dec 2 2021, 11:38 AM
MatzeB added inline comments.Dec 2 2021, 11:39 AM
llvm/lib/CodeGen/MIRParser/MIRParser.cpp
361–365

Move variable decl closer to use

lkail updated this revision to Diff 391543.Dec 2 2021, 9:24 PM

Address comment.