[MachineVerifier] Make TiedOpsRewritten computable in MIRParser

[lkail]

Summary

This patch is to address post-commit comment https://reviews.llvm.org/D80538#anchor-inline-1091625, which make the constraint stronger based on what https://reviews.llvm.org/D80538 does, i.e., "TiedOpsRewritten is set iff leave-ssa and all tied operands share the same register".

[lkail]

Add unittests.

[MatzeB]

LGTM, thanks!

llvm/lib/CodeGen/MIRParser/MIRParser.cpp

382–384

Could we just handle the value independently from SSA to make the code more uniform? Should make the code slightly easier to understand (even though techically it can indeed never be true in SSA).

[MatzeB]

llvm/lib/CodeGen/MIRParser/MIRParser.cpp

361–365

Move variable decl closer to use

[lkail]

Address comment.

llvm/lib/CodeGen/MIRParser/MIRParser.cpp

static bool isSSA(const MachineFunction &MF) {
   return true;
 }
 
 void MIRParserImpl::computeFunctionProperties(MachineFunction &MF) {
   MachineFunctionProperties &Properties = MF.getProperties();
 
   bool HasPHI = false;
   bool HasInlineAsm = false;
+  bool AllTiedOpsRewritten = true, HasTiedOps = false;
   for (const MachineBasicBlock &MBB : MF) {
     for (const MachineInstr &MI : MBB) {
       if (MI.isPHI())
         HasPHI = true;
       if (MI.isInlineAsm())
         HasInlineAsm = true;
+      for (unsigned I = 0; I < MI.getNumOperands(); ++I) {
+        const MachineOperand &MO = MI.getOperand(I);
+        if (!MO.isReg() || !MO.getReg())
+          continue;
+        unsigned DefIdx;
+        if (MO.isUse() && MI.isRegTiedToDefOperand(I, &DefIdx)) {
+          HasTiedOps = true;
+          if (MO.getReg() != MI.getOperand(DefIdx).getReg())
+            AllTiedOpsRewritten = false;
+        }
+      }
     }
   }
   if (!HasPHI)
     Properties.set(MachineFunctionProperties::Property::NoPHIs);
   MF.setHasInlineAsm(HasInlineAsm);
 
+  if (HasTiedOps && AllTiedOpsRewritten)
+    Properties.set(MachineFunctionProperties::Property::TiedOpsRewritten);
+
   if (isSSA(MF))
     Properties.set(MachineFunctionProperties::Property::IsSSA);
   else
     Properties.reset(MachineFunctionProperties::Property::IsSSA);
 
   const MachineRegisterInfo &MRI = MF.getRegInfo();
   if (MRI.getNumVirtRegs() == 0)
     Properties.set(MachineFunctionProperties::Property::NoVRegs);
 }
 
 bool MIRParserImpl::initializeCallSiteInfo(
     PerFunctionMIParsingState &PFS, const yaml::MachineFunction &YamlMF) {
   MachineFunction &MF = PFS.MF;

llvm/unittests/MIR/MachineMetadata.cpp

 CHECK-DAG: ![[MMSCOPE1:[0-9]+]] = distinct !{!{{[0-9]+}}, ![[MMDOMAIN]], !"scope1"}
 CHECK-DAG: ![[MMSET0:[0-9]+]] = !{![[MMSCOPE0]]}
 CHECK-DAG: ![[MMSET1:[0-9]+]] = !{![[MMSCOPE1]]}
 CHECK: body:
 CHECK: %5:vgpr_32 = FLAT_LOAD_DWORD killed %4, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %ir.p, !alias.scope ![[MMSET0]], !noalias ![[MMSET1]])
 )";
   EXPECT_TRUE(checkOutput(CheckString, Output));
 }
+
+TEST_F(MachineMetadataTest, TiedOpsRewritten) {
+  auto TM = createTargetMachine(Triple::normalize("powerpc64--"), "", "");
+  if (!TM)
+    GTEST_SKIP();
+  StringRef MIRString = R"MIR(
+---
+name:            foo
+alignment:       16
+tracksRegLiveness: true
+frameInfo:
+  maxAlignment:    16
+machineFunctionInfo: {}
+body:             |
+  bb.0:
+    liveins: $r3
+    %0:gprc = COPY $r3
+    %0 = RLWIMI killed %0, $r3, 1, 0, 30
+    $r3 = COPY %0
+    BLR8 implicit $r3, implicit $lr8, implicit $rm
+
+...
+)MIR";
+  MachineModuleInfo MMI(TM.get());
+  M = parseMIR(*TM, MIRString, "foo", MMI);
+  ASSERT_TRUE(M);
+  auto *MF = MMI.getMachineFunction(*M->getFunction("foo"));
+  MachineFunctionProperties &Properties = MF->getProperties();
+  ASSERT_TRUE(Properties.hasProperty(
+      MachineFunctionProperties::Property::TiedOpsRewritten));
+}
+
+TEST_F(MachineMetadataTest, NoTiedOpsRewritten) {
+  auto TM = createTargetMachine(Triple::normalize("powerpc64--"), "", "");
+  if (!TM)
+    GTEST_SKIP();
+  StringRef MIRString = R"MIR(
+---
+name:            foo
+alignment:       16
+tracksRegLiveness: true
+frameInfo:
+  maxAlignment:    16
+machineFunctionInfo: {}
+body:             |
+  bb.0:
+    liveins: $r3
+    %0:gprc = COPY $r3
+    %1:gprc = RLWIMI killed %0, $r3, 1, 0, 30
+    $r3 = COPY %1
+    BLR8 implicit $r3, implicit $lr8, implicit $rm
+
+...
+)MIR";
+  MachineModuleInfo MMI(TM.get());
+  M = parseMIR(*TM, MIRString, "foo", MMI);
+  ASSERT_TRUE(M);
+  auto *MF = MMI.getMachineFunction(*M->getFunction("foo"));
+  MachineFunctionProperties &Properties = MF->getProperties();
+  ASSERT_FALSE(Properties.hasProperty(
+      MachineFunctionProperties::Property::TiedOpsRewritten));
+}