[AMDGPU] Make getInstSizeInBytes more generic

[Joe_Nash]

Summary

NFC. This check mainly handles size affecting literals. Make it check all
explicit operands instead of a few by name. Also make the isLiteral
check handle the KIMM operands, see https://reviews.llvm.org/D111067

Change-Id: I1a362d55b2a10f5c74d445272e8b7829a8b77597

[foad]

Looks good to me if it passes an LLVM_ENABLE_EXPENSIVE_CHECKS build.

[Joe_Nash]

In D113318#3114951, @foad wrote:

Looks good to me if it passes an LLVM_ENABLE_EXPENSIVE_CHECKS build.

Yes, it does.

[arsenm]

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

7319–7320

This change broke the handling of source modifiers. we're now treating any source modifier operand as a literal

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

case AMDGPU::OPERAND_REG_INLINE_AC_FP16: {
     return false;
   }
   case AMDGPU::OPERAND_REG_IMM_V2FP16:
   case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
   case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16: {
     uint32_t Trunc = static_cast<uint32_t>(Imm);
     return AMDGPU::isInlinableLiteralV216(Trunc, ST.hasInv2PiInlineImm());
   }
+  case AMDGPU::OPERAND_KIMM32:
+  case AMDGPU::OPERAND_KIMM16:
+    return false;
   default:
     llvm_unreachable("invalid bitwidth");
   }
 }
 
 bool SIInstrInfo::isLiteralConstantLike(const MachineOperand &MO,
                                         const MCOperandInfo &OpInfo) const {
   switch (MO.getType()) {
if (isFixedSize(MI)) {
     // If we hit the buggy offset, an extra nop will be inserted in MC so
     // estimate the worst case.
     if (MI.isBranch() && ST.hasOffset3fBug())
       Size += 4;
 
     return Size;
   }
 
-  // 4-byte instructions may have a 32-bit literal encoded after them. Check
-  // operands that coud ever be literals.
+  // Instructions may have a 32-bit literal encoded after them. Check
+  // operands that could ever be literals.
   if (isVALU(MI) || isSALU(MI)) {
-    int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
-    if (Src0Idx == -1)
-      return DescSize; // No operands.
-
-    if (isLiteralConstantLike(MI.getOperand(Src0Idx), Desc.OpInfo[Src0Idx]))
-      return isVOP3(MI) ? 12 : (DescSize + 4);
-
-    int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
-    if (Src1Idx == -1)
-      return DescSize;
-
-    if (isLiteralConstantLike(MI.getOperand(Src1Idx), Desc.OpInfo[Src1Idx]))
-      return isVOP3(MI) ? 12 : (DescSize + 4);
-
-    int Src2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2);
-    if (Src2Idx == -1)
-      return DescSize;
-
-    if (isLiteralConstantLike(MI.getOperand(Src2Idx), Desc.OpInfo[Src2Idx]))
-      return isVOP3(MI) ? 12 : (DescSize + 4);
-
+    if (isDPP(MI))
       return DescSize;
+    bool HasLiteral = false;
+    for (int I = 0, E = MI.getNumExplicitOperands(); I != E; ++I) {
+      if (isLiteralConstant(MI, I)) {
+        HasLiteral = true;
+        break;
+      }
+    }
+    return HasLiteral ? DescSize + 4 : DescSize;
   }
 
   // Check whether we have extra NSA words.
   if (isMIMG(MI)) {
     int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0);
     if (VAddr0Idx < 0)
       return 8;