[AArch64] Fix a bug from a pattern for uaddv(uaddlp(x)) ==> uaddlv

[jaykang10]

Summary

A pattern has selected wrong uaddlv MI from https://reviews.llvm.org/D104236.

It should be as below.

uaddv(uaddlp(v8i8)) ==> uaddlv(v8i8)

[LemonBoy]

LGTM.
My only suggestion would be to drop the popcount test as the bug affects uaddlv4h_from_v8i8, but that's only a minor nit.

[jaykang10]

In D113263#3111307, @LemonBoy wrote:

LGTM.
My only suggestion would be to drop the popcount test as the bug affects uaddlv4h_from_v8i8, but that's only a minor nit.

Yep, let me remove it.

Thanks for bug report and reviewing this patch.

llvm/lib/Target/AArch64/AArch64InstrInfo.td

 defm FMINNMV : SIMDFPAcrossLanes<0b01100, 1, "fminnmv", int_aarch64_neon_fminnmv>;
 defm FMINV   : SIMDFPAcrossLanes<0b01111, 1, "fminv", int_aarch64_neon_fminv>;
 
 // Patterns for uaddv(uaddlp(x)) ==> uaddlv
 def : Pat<(i32 (vector_extract (v8i16 (insert_subvector undef,
             (v4i16 (AArch64uaddv (v4i16 (AArch64uaddlp (v8i8 V64:$op))))),
             (i64 0))), (i64 0))),
           (EXTRACT_SUBREG (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
-           (UADDLVv4i16v V64:$op), ssub), ssub)>;
+           (UADDLVv8i8v V64:$op), hsub), ssub)>;
 def : Pat<(i32 (vector_extract (v8i16 (AArch64uaddv (v8i16 (AArch64uaddlp
            (v16i8 V128:$op))))), (i64 0))),
           (EXTRACT_SUBREG (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
            (UADDLVv16i8v V128:$op), hsub), ssub)>;
 def : Pat<(v4i32 (AArch64uaddv (v4i32 (AArch64uaddlp (v8i16 V128:$op))))),
           (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), (UADDLVv8i16v V128:$op), ssub)>;
 
 // Patterns for addp(uaddlp(x))) ==> uaddlv

llvm/test/CodeGen/AArch64/neon-uaddlv.ll

 declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>) nounwind readnone
 declare i64 @llvm.vector.reduce.add.v2i64(<2 x i64>) nounwind readnone
 declare i32 @llvm.vector.reduce.add.v2i32(<2 x i32>) nounwind readnone
 
 define i16 @uaddlv4h_from_v8i8(<8 x i8>* %A) nounwind {
 ; CHECK-LABEL: uaddlv4h_from_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr d0, [x0]
-; CHECK-NEXT:    uaddlv s0, v0.4h
+; CHECK-NEXT:    uaddlv h0, v0.8b
 ; CHECK-NEXT:    fmov w0, s0
 ; CHECK-NEXT:    ret
   %tmp1 = load <8 x i8>, <8 x i8>* %A
   %tmp3 = call <4 x i16> @llvm.aarch64.neon.uaddlp.v4i16.v8i8(<8 x i8> %tmp1)
   %tmp5 = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> %tmp3)
   ret i16 %tmp5
 }