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Differential D112323

GlobalISel/Utils: Use incoming regbank while constraining the superclasses
ClosedPublic

Authored by cdevadas on Oct 22 2021, 9:09 AM.

Details

Reviewers
aemerson
dsanders
aditya_nandakumar
arsenm
foad
Commits
rGaa2d3b59ce75: GlobalISel/Utils: Use incoming regbank while constraining the superclasses
Summary

Register operands with superclasses can possibly have multiple regBanks
if they have different register types. The regBank ambiguity resolved
during regbankselect should be used to constrain the operand regclass
instead of obtaining one from the MCInstrDesc.

This is a prerequisite patch for D109300 that introduces allocatable AV_*
Superclasses for AMDGPU by combining both VGPRs and AGPRs and we want to
restrain the regclass to either A or V based on the incoming regbank.

Diff Detail

Event Timeline

cdevadas created this revision.Oct 22 2021, 9:09 AM
Herald added subscribers: kerbowa, hiraditya, tpr and 3 others. · View Herald TranscriptOct 22 2021, 9:09 AM
cdevadas requested review of this revision.Oct 22 2021, 9:09 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 22 2021, 9:09 AM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
cdevadas added a child revision: D109300: [AMDGPU] Make vector superclasses allocatable.Oct 22 2021, 9:09 AM
Harbormaster completed remote builds in B130157: Diff 381566.Oct 22 2021, 9:17 AM
cdevadas mentioned this in D109300: [AMDGPU] Make vector superclasses allocatable.Oct 22 2021, 9:49 AM
arsenm added a comment.Oct 22 2021, 10:00 AM

It's not accurate to say it would lead to incorrect codegen, we would just prefer to pick the classes beforehand rather than let the allocator decide until it needs to split live ranges

llvm/lib/CodeGen/GlobalISel/Utils.cpp
119

I'm not sure there's any case where this shoudl be called where MRI.getRegBankOrNull(Reg) can be null?

124

I would expect this to just directly assign getCommonSubClass's result without the comparison

cdevadas added a comment.Oct 22 2021, 11:17 AM
In D112323#3081078, @arsenm wrote:

It's not accurate to say it would lead to incorrect codegen, we would just prefer to pick the classes beforehand rather than let the allocator decide until it needs to split live ranges

Yes, I was referring to the case when we fail to adjust the opcode for MOV/COPY to AV_* classes if we let regalloc to choose the register without fixing the class beforehand.
I will modify the description.

llvm/lib/CodeGen/GlobalISel/Utils.cpp
119

It's been called from SelectionDAG too.

124

Will do.

cdevadas updated this revision to Diff 381619.Oct 22 2021, 11:59 AM
cdevadas edited the summary of this revision. (Show Details)

Comments addressed.

Harbormaster completed remote builds in B130186: Diff 381619.Oct 22 2021, 12:03 PM
arsenm added inline comments.Oct 26 2021, 1:14 PM
llvm/lib/CodeGen/GlobalISel/Utils.cpp
120–121

Can this actually fail?

122–123

Why not just call getAllocatableClass on it, like how InstrEmitter does it?

cdevadas updated this revision to Diff 383475.Oct 29 2021, 1:05 PM

Addressed review comments.
(Used getAllocatableClass + a fix in getConstrainedRegClassForOperand to avoid a crash if regbank is not yet selected)

Harbormaster completed remote builds in B131504: Diff 383475.Oct 29 2021, 2:04 PM
arsenm accepted this revision.Oct 29 2021, 2:04 PM
arsenm added inline comments.
llvm/lib/CodeGen/GlobalISel/Utils.cpp
116

Typo overriden

This revision is now accepted and ready to land.Oct 29 2021, 2:04 PM
Closed by commit rGaa2d3b59ce75: GlobalISel/Utils: Use incoming regbank while constraining the superclasses (authored by cdevadas). · Explain WhyOct 30 2021, 4:22 AM
This revision was automatically updated to reflect the committed changes.
cdevadas added a commit: rGaa2d3b59ce75: GlobalISel/Utils: Use incoming regbank while constraining the superclasses.

Revision Contents

PathSize
llvm/
lib/
CodeGen/
GlobalISel/
24 lines
Target/
AMDGPU/
6 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
24 lines
12 lines
47 lines
16 lines
8 lines
112 lines
56 lines
32 lines
47 lines
47 lines

Diff 383573

llvm/lib/CodeGen/GlobalISel/Utils.cpp

Show First 20 Lines • Show All 56 Lines • ▼ Show 20 LinesRegister llvm::constrainOperandRegClass(
assert(Register::isVirtualRegister(Reg) && "PhysReg not implemented"); assert(Register::isVirtualRegister(Reg) && "PhysReg not implemented");
Register ConstrainedReg = constrainRegToClass(MRI, TII, RBI, Reg, RegClass); Register ConstrainedReg = constrainRegToClass(MRI, TII, RBI, Reg, RegClass);
// If we created a new virtual register because the class is not compatible // If we created a new virtual register because the class is not compatible
// then create a copy between the new and the old register. // then create a copy between the new and the old register.
if (ConstrainedReg != Reg) { if (ConstrainedReg != Reg) {
MachineBasicBlock::iterator InsertIt(&InsertPt); MachineBasicBlock::iterator InsertIt(&InsertPt);
MachineBasicBlock &MBB = *InsertPt.getParent(); MachineBasicBlock &MBB = *InsertPt.getParent();
// FIXME: The copy needs to have the classes constrained for its operands.
// Use operand's regbank to get the class for old register (Reg).
if (RegMO.isUse()) { if (RegMO.isUse()) {
BuildMI(MBB, InsertIt, InsertPt.getDebugLoc(), BuildMI(MBB, InsertIt, InsertPt.getDebugLoc(),
TII.get(TargetOpcode::COPY), ConstrainedReg) TII.get(TargetOpcode::COPY), ConstrainedReg)
.addReg(Reg); .addReg(Reg);
} else { } else {
assert(RegMO.isDef() && "Must be a definition"); assert(RegMO.isDef() && "Must be a definition");
BuildMI(MBB, std::next(InsertIt), InsertPt.getDebugLoc(), BuildMI(MBB, std::next(InsertIt), InsertPt.getDebugLoc(),
TII.get(TargetOpcode::COPY), Reg) TII.get(TargetOpcode::COPY), Reg)
Show All 23 LinesRegister llvm::constrainOperandRegClass(
const MachineFunction &MF, const TargetRegisterInfo &TRI, const MachineFunction &MF, const TargetRegisterInfo &TRI,
MachineRegisterInfo &MRI, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetInstrInfo &TII,
const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II,
MachineOperand &RegMO, unsigned OpIdx) { MachineOperand &RegMO, unsigned OpIdx) {
Register Reg = RegMO.getReg(); Register Reg = RegMO.getReg();
// Assume physical registers are properly constrained. // Assume physical registers are properly constrained.
assert(Register::isVirtualRegister(Reg) && "PhysReg not implemented"); assert(Register::isVirtualRegister(Reg) && "PhysReg not implemented");
const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF); const TargetRegisterClass *OpRC = TII.getRegClass(II, OpIdx, &TRI, MF);
// Some of the target independent instructions, like COPY, may not impose any // Some of the target independent instructions, like COPY, may not impose any
// register class constraints on some of their operands: If it's a use, we can // register class constraints on some of their operands: If it's a use, we can
// skip constraining as the instruction defining the register would constrain // skip constraining as the instruction defining the register would constrain
// it. // it.
// We can't constrain unallocatable register classes, because we can't create if (OpRC) {
// virtual registers for these classes, so we need to let targets handled this // Obtain the RC from incoming regbank if it is a proper sub-class. Operands
// case. // can have multiple regbanks for a superclass that combine different
if (RegClass && !RegClass->isAllocatable()) // register types (E.g., AMDGPU's VGPR and AGPR). The regbank ambiguity
RegClass = TRI.getConstrainedRegClassForOperand(RegMO, MRI); // resolved by targets during regbankselect should not be overridden.
arsenmUnsubmitted
Not Done
ReplyInline Actions

Typo overriden

arsenm: Typo overriden
if (const auto *SubRC = TRI.getCommonSubClass(
OpRC, TRI.getConstrainedRegClassForOperand(RegMO, MRI)))
OpRC = SubRC;
arsenmUnsubmitted
Not Done
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I'm not sure there's any case where this shoudl be called where MRI.getRegBankOrNull(Reg) can be null?

arsenm: I'm not sure there's any case where this shoudl be called where MRI.getRegBankOrNull(Reg) can…
cdevadasAuthorUnsubmitted
Done
ReplyInline Actions

It's been called from SelectionDAG too.

cdevadas: It's been called from SelectionDAG too.
if (!RegClass) { OpRC = TRI.getAllocatableClass(OpRC);
arsenmUnsubmitted
Not Done
ReplyInline Actions

Can this actually fail?

arsenm: Can this actually fail?
}
arsenmUnsubmitted
Not Done
ReplyInline Actions

Why not just call getAllocatableClass on it, like how InstrEmitter does it?

arsenm: Why not just call getAllocatableClass on it, like how InstrEmitter does it?
if (!OpRC) {
arsenmUnsubmitted
Not Done
ReplyInline Actions

I would expect this to just directly assign getCommonSubClass's result without the comparison

arsenm: I would expect this to just directly assign getCommonSubClass's result without the comparison
cdevadasAuthorUnsubmitted
Done
ReplyInline Actions

Will do.

cdevadas: Will do.
assert((!isTargetSpecificOpcode(II.getOpcode()) || RegMO.isUse()) && assert((!isTargetSpecificOpcode(II.getOpcode()) || RegMO.isUse()) &&
"Register class constraint is required unless either the " "Register class constraint is required unless either the "
"instruction is target independent or the operand is a use"); "instruction is target independent or the operand is a use");
// FIXME: Just bailing out like this here could be not enough, unless we // FIXME: Just bailing out like this here could be not enough, unless we
// expect the users of this function to do the right thing for PHIs and // expect the users of this function to do the right thing for PHIs and
// COPY: // COPY:
// v1 = COPY v0 // v1 = COPY v0
// v2 = COPY v1 // v2 = COPY v1
// v1 here may end up not being constrained at all. Please notice that to // v1 here may end up not being constrained at all. Please notice that to
// reproduce the issue we likely need a destination pattern of a selection // reproduce the issue we likely need a destination pattern of a selection
// rule producing such extra copies, not just an input GMIR with them as // rule producing such extra copies, not just an input GMIR with them as
// every existing target using selectImpl handles copies before calling it // every existing target using selectImpl handles copies before calling it
// and they never reach this function. // and they never reach this function.
return Reg; return Reg;
} }
return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *RegClass, return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *OpRC,
RegMO); RegMO);
} }
bool llvm::constrainSelectedInstRegOperands(MachineInstr &I, bool llvm::constrainSelectedInstRegOperands(MachineInstr &I,
const TargetInstrInfo &TII, const TargetInstrInfo &TII,
const TargetRegisterInfo &TRI, const TargetRegisterInfo &TRI,
const RegisterBankInfo &RBI) { const RegisterBankInfo &RBI) {
assert(!isPreISelGenericOpcode(I.getOpcode()) && assert(!isPreISelGenericOpcode(I.getOpcode()) &&
▲ Show 20 Lines • Show All 1,088 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

Show First 20 Lines • Show All 2,508 Lines • ▼ Show 20 Lines
const TargetRegisterClass * const TargetRegisterClass *
SIRegisterInfo::getConstrainedRegClassForOperand(const MachineOperand &MO, SIRegisterInfo::getConstrainedRegClassForOperand(const MachineOperand &MO,
const MachineRegisterInfo &MRI) const { const MachineRegisterInfo &MRI) const {
const RegClassOrRegBank &RCOrRB = MRI.getRegClassOrRegBank(MO.getReg()); const RegClassOrRegBank &RCOrRB = MRI.getRegClassOrRegBank(MO.getReg());
if (const RegisterBank *RB = RCOrRB.dyn_cast<const RegisterBank*>()) if (const RegisterBank *RB = RCOrRB.dyn_cast<const RegisterBank*>())
return getRegClassForTypeOnBank(MRI.getType(MO.getReg()), *RB, MRI); return getRegClassForTypeOnBank(MRI.getType(MO.getReg()), *RB, MRI);
const TargetRegisterClass *RC = RCOrRB.get<const TargetRegisterClass*>(); if (const auto *RC = RCOrRB.dyn_cast<const TargetRegisterClass *>())
return getAllocatableClass(RC); return getAllocatableClass(RC);
return nullptr;
} }
MCRegister SIRegisterInfo::getVCC() const { MCRegister SIRegisterInfo::getVCC() const {
return isWave32 ? AMDGPU::VCC_LO : AMDGPU::VCC; return isWave32 ? AMDGPU::VCC_LO : AMDGPU::VCC;
} }
const TargetRegisterClass *SIRegisterInfo::getVGPR64Class() const { const TargetRegisterClass *SIRegisterInfo::getVGPR64Class() const {
// VGPR tuples have an alignment requirement on gfx90a variants. // VGPR tuples have an alignment requirement on gfx90a variants.
▲ Show 20 Lines • Show All 132 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.mir

Show All 9 Lines
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $vgpr0 liveins: $sgpr0, $vgpr0
; WAVE64-LABEL: name: class_s32_vcc_sv ; WAVE64-LABEL: name: class_s32_vcc_sv
; WAVE64: liveins: $sgpr0, $vgpr0 ; WAVE64: liveins: $sgpr0, $vgpr0
; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec ; WAVE64: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]] ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
; WAVE32-LABEL: name: class_s32_vcc_sv ; WAVE32-LABEL: name: class_s32_vcc_sv
; WAVE32: liveins: $sgpr0, $vgpr0 ; WAVE32: liveins: $sgpr0, $vgpr0
; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec ; WAVE32: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]] ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0 %1:vgpr(s32) = COPY $vgpr0
%2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1 %2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: class_s32_vcc_vs name: class_s32_vcc_vs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $vgpr0 liveins: $sgpr0, $vgpr0
; WAVE64-LABEL: name: class_s32_vcc_vs ; WAVE64-LABEL: name: class_s32_vcc_vs
; WAVE64: liveins: $sgpr0, $vgpr0 ; WAVE64: liveins: $sgpr0, $vgpr0
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE64: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec ; WAVE64: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]] ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
; WAVE32-LABEL: name: class_s32_vcc_vs ; WAVE32-LABEL: name: class_s32_vcc_vs
; WAVE32: liveins: $sgpr0, $vgpr0 ; WAVE32: liveins: $sgpr0, $vgpr0
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE32: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec ; WAVE32: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]] ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:sgpr(s32) = COPY $sgpr0 %1:sgpr(s32) = COPY $sgpr0
%2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1 %2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: class_s32_vcc_vv name: class_s32_vcc_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: class_s32_vcc_vv ; WAVE64-LABEL: name: class_s32_vcc_vv
; WAVE64: liveins: $vgpr0, $vgpr1 ; WAVE64: liveins: $vgpr0, $vgpr1
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec ; WAVE64: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]] ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
; WAVE32-LABEL: name: class_s32_vcc_vv ; WAVE32-LABEL: name: class_s32_vcc_vv
; WAVE32: liveins: $vgpr0, $vgpr1 ; WAVE32: liveins: $vgpr0, $vgpr1
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec ; WAVE32: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]] ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1 %2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: class_s64_vcc_sv name: class_s64_vcc_sv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1, $vgpr0 liveins: $sgpr0_sgpr1, $vgpr0
; WAVE64-LABEL: name: class_s64_vcc_sv ; WAVE64-LABEL: name: class_s64_vcc_sv
; WAVE64: liveins: $sgpr0_sgpr1, $vgpr0 ; WAVE64: liveins: $sgpr0_sgpr1, $vgpr0
; WAVE64: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 ; WAVE64: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec ; WAVE64: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]] ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
; WAVE32-LABEL: name: class_s64_vcc_sv ; WAVE32-LABEL: name: class_s64_vcc_sv
; WAVE32: liveins: $sgpr0_sgpr1, $vgpr0 ; WAVE32: liveins: $sgpr0_sgpr1, $vgpr0
; WAVE32: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 ; WAVE32: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec ; WAVE32: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]] ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
%0:sgpr(s64) = COPY $sgpr0_sgpr1 %0:sgpr(s64) = COPY $sgpr0_sgpr1
%1:vgpr(s32) = COPY $vgpr0 %1:vgpr(s32) = COPY $vgpr0
%2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1 %2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: class_s64_vcc_vs name: class_s64_vcc_vs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1, $vgpr0 liveins: $sgpr0_sgpr1, $vgpr0
; WAVE64-LABEL: name: class_s64_vcc_vs ; WAVE64-LABEL: name: class_s64_vcc_vs
; WAVE64: liveins: $sgpr0_sgpr1, $vgpr0 ; WAVE64: liveins: $sgpr0_sgpr1, $vgpr0
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE64: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec ; WAVE64: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]] ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
; WAVE32-LABEL: name: class_s64_vcc_vs ; WAVE32-LABEL: name: class_s64_vcc_vs
; WAVE32: liveins: $sgpr0_sgpr1, $vgpr0 ; WAVE32: liveins: $sgpr0_sgpr1, $vgpr0
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE32: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec ; WAVE32: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]] ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:sgpr(s32) = COPY $sgpr0 %1:sgpr(s32) = COPY $sgpr0
%2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1 %2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: class_s64_vcc_vv name: class_s64_vcc_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2 liveins: $vgpr0_vgpr1, $vgpr2
; WAVE64-LABEL: name: class_s64_vcc_vv ; WAVE64-LABEL: name: class_s64_vcc_vv
; WAVE64: liveins: $vgpr0_vgpr1, $vgpr2 ; WAVE64: liveins: $vgpr0_vgpr1, $vgpr2
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; WAVE64: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec ; WAVE64: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]] ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
; WAVE32-LABEL: name: class_s64_vcc_vv ; WAVE32-LABEL: name: class_s64_vcc_vv
; WAVE32: liveins: $vgpr0_vgpr1, $vgpr2 ; WAVE32: liveins: $vgpr0_vgpr1, $vgpr2
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; WAVE32: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec ; WAVE32: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]] ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s32) = COPY $vgpr2 %1:vgpr(s32) = COPY $vgpr2
%2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1 %2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.s16.mir

Show All 17 Lines
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $vgpr0 liveins: $sgpr0, $vgpr0
; WAVE32-LABEL: name: class_s16_vcc_sv ; WAVE32-LABEL: name: class_s16_vcc_sv
; WAVE32: liveins: $sgpr0, $vgpr0 ; WAVE32: liveins: $sgpr0, $vgpr0
; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec ; WAVE32: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]] ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]
; WAVE64-LABEL: name: class_s16_vcc_sv ; WAVE64-LABEL: name: class_s16_vcc_sv
; WAVE64: liveins: $sgpr0, $vgpr0 ; WAVE64: liveins: $sgpr0, $vgpr0
; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec ; WAVE64: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]] ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0 %1:vgpr(s32) = COPY $vgpr0
%2:sgpr(s16) = G_TRUNC %0 %2:sgpr(s16) = G_TRUNC %0
%4:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2, %1 %4:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2, %1
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: class_s16_vcc_vs name: class_s16_vcc_vs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $vgpr0 liveins: $sgpr0, $vgpr0
; WAVE32-LABEL: name: class_s16_vcc_vs ; WAVE32-LABEL: name: class_s16_vcc_vs
; WAVE32: liveins: $sgpr0, $vgpr0 ; WAVE32: liveins: $sgpr0, $vgpr0
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE32: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec ; WAVE32: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]] ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]
; WAVE64-LABEL: name: class_s16_vcc_vs ; WAVE64-LABEL: name: class_s16_vcc_vs
; WAVE64: liveins: $sgpr0, $vgpr0 ; WAVE64: liveins: $sgpr0, $vgpr0
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE64: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec ; WAVE64: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]] ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:sgpr(s32) = COPY $sgpr0 %1:sgpr(s32) = COPY $sgpr0
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%4:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2, %1 %4:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2, %1
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: class_s16_vcc_vv name: class_s16_vcc_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE32-LABEL: name: class_s16_vcc_vv ; WAVE32-LABEL: name: class_s16_vcc_vv
; WAVE32: liveins: $vgpr0, $vgpr1 ; WAVE32: liveins: $vgpr0, $vgpr1
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec ; WAVE32: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]] ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]
; WAVE64-LABEL: name: class_s16_vcc_vv ; WAVE64-LABEL: name: class_s16_vcc_vv
; WAVE64: liveins: $vgpr0, $vgpr1 ; WAVE64: liveins: $vgpr0, $vgpr1
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec ; WAVE64: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]] ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%4:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2, %1 %4:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2, %1
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir

Show All 12 Lines
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: and_s1_vcc_vcc_vcc ; WAVE64-LABEL: name: and_s1_vcc_vcc_vcc
; WAVE64: liveins: $vgpr0, $vgpr1 ; WAVE64: liveins: $vgpr0, $vgpr1
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec ; WAVE64: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; WAVE64: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec ; WAVE64: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
; WAVE64: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec ; WAVE64: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
; WAVE64: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]], implicit-def dead $scc ; WAVE64: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]], implicit-def dead $scc
; WAVE64: S_ENDPGM 0, implicit [[S_AND_B64_]] ; WAVE64: S_ENDPGM 0, implicit [[S_AND_B64_]]
; WAVE32-LABEL: name: and_s1_vcc_vcc_vcc ; WAVE32-LABEL: name: and_s1_vcc_vcc_vcc
; WAVE32: liveins: $vgpr0, $vgpr1 ; WAVE32: liveins: $vgpr0, $vgpr1
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec ; WAVE32: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; WAVE32: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec ; WAVE32: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
; WAVE32: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_EQ_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec ; WAVE32: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]], implicit-def dead $scc ; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]], implicit-def dead $scc
; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]] ; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]]
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s32) = G_CONSTANT i32 0 %2:vgpr(s32) = G_CONSTANT i32 0
%3:vcc(s1) = G_ICMP intpred(eq), %0, %2 %3:vcc(s1) = G_ICMP intpred(eq), %0, %2
%4:vcc(s1) = G_ICMP intpred(eq), %1, %2 %4:vcc(s1) = G_ICMP intpred(eq), %1, %2
%5:vcc(s1) = G_AND %3, %4 %5:vcc(s1) = G_AND %3, %4
S_ENDPGM 0, implicit %5 S_ENDPGM 0, implicit %5
▲ Show 20 Lines • Show All 326 Lines • ▼ Show 20 Lines
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: and_s1_vcc_copy_to_vcc ; WAVE64-LABEL: name: and_s1_vcc_copy_to_vcc
; WAVE64: liveins: $vgpr0, $vgpr1 ; WAVE64: liveins: $vgpr0, $vgpr1
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec ; WAVE64: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec ; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
; WAVE64: [[V_AND_B32_e32_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY1]], implicit $exec ; WAVE64: [[V_AND_B32_e32_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY1]], implicit $exec
; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_1]], implicit $exec ; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_1]], implicit $exec
; WAVE64: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc ; WAVE64: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
; WAVE64: S_ENDPGM 0, implicit [[S_AND_B64_]] ; WAVE64: S_ENDPGM 0, implicit [[S_AND_B64_]]
; WAVE32-LABEL: name: and_s1_vcc_copy_to_vcc ; WAVE32-LABEL: name: and_s1_vcc_copy_to_vcc
; WAVE32: liveins: $vgpr0, $vgpr1 ; WAVE32: liveins: $vgpr0, $vgpr1
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec ; WAVE32: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec ; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
; WAVE32: [[V_AND_B32_e32_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY1]], implicit $exec ; WAVE32: [[V_AND_B32_e32_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY1]], implicit $exec
; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_1]], implicit $exec ; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_1]], implicit $exec
; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc ; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]] ; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]]
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s1) = G_TRUNC %0 %2:vgpr(s1) = G_TRUNC %0
%3:vgpr(s1) = G_TRUNC %1 %3:vgpr(s1) = G_TRUNC %1
%4:vcc(s1) = COPY %2 %4:vcc(s1) = COPY %2
%5:vcc(s1) = COPY %3 %5:vcc(s1) = COPY %3
%6:vcc(s1) = G_AND %4, %5 %6:vcc(s1) = G_AND %4, %5
Show All 13 Linesbody: |
bb.0: bb.0:
liveins: $vgpr0, $sgpr0 liveins: $vgpr0, $sgpr0
; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave32 ; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
; WAVE64: liveins: $vgpr0, $sgpr0 ; WAVE64: liveins: $vgpr0, $sgpr0
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: %sgpr0:sreg_32 = COPY $sgpr0 ; WAVE64: %sgpr0:sreg_32 = COPY $sgpr0
; WAVE64: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec ; WAVE64: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec ; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def $scc ; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def $scc
; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec ; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
; WAVE64: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc ; WAVE64: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
; WAVE64: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_AND_B64_]] ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_AND_B64_]]
; WAVE64: S_ENDPGM 0, implicit [[COPY1]] ; WAVE64: S_ENDPGM 0, implicit [[COPY1]]
; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave32 ; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
; WAVE32: liveins: $vgpr0, $sgpr0 ; WAVE32: liveins: $vgpr0, $sgpr0
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: %sgpr0:sreg_32 = COPY $sgpr0 ; WAVE32: %sgpr0:sreg_32 = COPY $sgpr0
; WAVE32: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec ; WAVE32: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec ; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def $scc ; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def $scc
; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec ; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
; WAVE32: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc ; WAVE32: [[S_AND_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_AND_B32_1]] ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_AND_B32_1]]
; WAVE32: S_ENDPGM 0, implicit [[COPY1]] ; WAVE32: S_ENDPGM 0, implicit [[COPY1]]
%1:vgpr(s32) = COPY $vgpr0 %1:vgpr(s32) = COPY $vgpr0
%0:vgpr(s1) = G_TRUNC %1(s32) %0:vgpr(s1) = G_TRUNC %1(s32)
%sgpr0:sgpr(s32) = COPY $sgpr0 %sgpr0:sgpr(s32) = COPY $sgpr0
%2:sgpr(s1) = G_TRUNC %sgpr0 %2:sgpr(s1) = G_TRUNC %sgpr0
%6:sgpr(s32) = G_CONSTANT i32 0 %6:sgpr(s32) = G_CONSTANT i32 0
%7:sgpr(p1) = G_IMPLICIT_DEF %7:sgpr(p1) = G_IMPLICIT_DEF
Show All 15 Linesbody: |
bb.0: bb.0:
liveins: $vgpr0, $sgpr0 liveins: $vgpr0, $sgpr0
; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave64 ; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave64
; WAVE64: liveins: $vgpr0, $sgpr0 ; WAVE64: liveins: $vgpr0, $sgpr0
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: %sgpr0:sreg_32 = COPY $sgpr0 ; WAVE64: %sgpr0:sreg_32 = COPY $sgpr0
; WAVE64: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec ; WAVE64: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec ; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def $scc ; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def $scc
; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec ; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
; WAVE64: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc ; WAVE64: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
; WAVE64: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[S_AND_B64_]] ; WAVE64: S_ENDPGM 0, implicit [[S_AND_B64_]]
; WAVE64: S_ENDPGM 0, implicit [[COPY1]]
; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave64 ; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave64
; WAVE32: liveins: $vgpr0, $sgpr0 ; WAVE32: liveins: $vgpr0, $sgpr0
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: %sgpr0:sreg_32 = COPY $sgpr0 ; WAVE32: %sgpr0:sreg_32 = COPY $sgpr0
; WAVE32: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec ; WAVE32: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec ; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def $scc ; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def $scc
; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec ; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
; WAVE32: [[S_AND_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc ; WAVE32: [[S_AND_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
; WAVE32: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[S_AND_B32_1]] ; WAVE32: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[S_AND_B32_1]]
; WAVE32: S_ENDPGM 0, implicit [[COPY1]] ; WAVE32: S_ENDPGM 0, implicit [[COPY1]]
%1:vgpr(s32) = COPY $vgpr0 %1:vgpr(s32) = COPY $vgpr0
%0:vgpr(s1) = G_TRUNC %1(s32) %0:vgpr(s1) = G_TRUNC %1(s32)
%sgpr0:sgpr(s32) = COPY $sgpr0 %sgpr0:sgpr(s32) = COPY $sgpr0
%2:sgpr(s1) = G_TRUNC %sgpr0 %2:sgpr(s1) = G_TRUNC %sgpr0
%6:sgpr(s32) = G_CONSTANT i32 0 %6:sgpr(s32) = G_CONSTANT i32 0
Show All 36 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir

Show First 20 Lines • Show All 211 Lines • ▼ Show 20 Lines
body: | body: |
; GCN-LABEL: name: brcond_cmp_logic ; GCN-LABEL: name: brcond_cmp_logic
; GCN: bb.0: ; GCN: bb.0:
; GCN: successors: %bb.1(0x80000000) ; GCN: successors: %bb.1(0x80000000)
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
; GCN: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[COPY]], [[COPY1]], implicit $exec ; GCN: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[COPY1]], implicit $exec
; GCN: %5:sreg_64 = nofpexcept V_CMP_EQ_F32_e64 0, [[COPY2]], 0, [[COPY3]], 0, implicit $mode, implicit $exec ; GCN: %5:sreg_64_xexec = nofpexcept V_CMP_EQ_F32_e64 0, [[COPY2]], 0, [[COPY3]], 0, implicit $mode, implicit $exec
; GCN: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[V_CMP_EQ_U32_e64_]], %5, implicit-def dead $scc ; GCN: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[V_CMP_EQ_U32_e64_]], %5, implicit-def dead $scc
; GCN: $vcc = COPY [[S_AND_B64_]] ; GCN: $vcc = COPY [[S_AND_B64_]]
; GCN: S_CBRANCH_VCCNZ %bb.1, implicit $vcc ; GCN: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
; GCN: bb.1: ; GCN: bb.1:
bb.0: bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
Show All 18 Lines
body: | body: |
; GCN-LABEL: name: brcond_logic ; GCN-LABEL: name: brcond_logic
; GCN: bb.0: ; GCN: bb.0:
; GCN: successors: %bb.1(0x80000000) ; GCN: successors: %bb.1(0x80000000)
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, [[COPY2]], implicit-def $scc ; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, [[COPY2]], implicit-def $scc
; GCN: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec ; GCN: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
; GCN: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[COPY]], [[COPY1]], implicit $exec ; GCN: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[COPY1]], implicit $exec
; GCN: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[V_CMP_EQ_U32_e64_]], [[V_CMP_NE_U32_e64_]], implicit-def dead $scc ; GCN: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U32_e64_]], [[V_CMP_NE_U32_e64_]], implicit-def dead $scc
; GCN: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[S_AND_B64_]], $exec, implicit-def $scc ; GCN: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[S_AND_B64_]], $exec, implicit-def $scc
; GCN: $vcc = COPY [[S_AND_B64_1]] ; GCN: $vcc = COPY [[S_AND_B64_1]]
; GCN: S_CBRANCH_VCCNZ %bb.1, implicit $vcc ; GCN: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
; GCN: bb.1: ; GCN: bb.1:
bb.0: bb.0:
liveins: $sgpr0, $vgpr0, $vgpr1 liveins: $sgpr0, $vgpr0, $vgpr1
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
Show All 16 Lines
regBankSelected: true regBankSelected: true
body: | body: |
; GCN-LABEL: name: brcond_logic_const ; GCN-LABEL: name: brcond_logic_const
; GCN: bb.0: ; GCN: bb.0:
; GCN: successors: %bb.1(0x80000000) ; GCN: successors: %bb.1(0x80000000)
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[COPY]], [[COPY1]], implicit $exec ; GCN: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[COPY1]], implicit $exec
; GCN: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 -1 ; GCN: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 -1
; GCN: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[V_CMP_EQ_U32_e64_]], [[S_MOV_B64_]], implicit-def dead $scc ; GCN: [[S_XOR_B64_:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[V_CMP_EQ_U32_e64_]], [[S_MOV_B64_]], implicit-def dead $scc
; GCN: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[S_XOR_B64_]], $exec, implicit-def $scc ; GCN: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[S_XOR_B64_]], $exec, implicit-def $scc
; GCN: $vcc = COPY [[S_AND_B64_]] ; GCN: $vcc = COPY [[S_AND_B64_]]
; GCN: S_CBRANCH_VCCNZ %bb.1, implicit $vcc ; GCN: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
; GCN: bb.1: ; GCN: bb.1:
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
Show All 10 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir

Show First 20 Lines • Show All 252 Lines • ▼ Show 20 Lines
name: constant_i1_vcc name: constant_i1_vcc
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
; WAVE64-LABEL: name: constant_i1_vcc ; WAVE64-LABEL: name: constant_i1_vcc
; WAVE64: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 -1 ; WAVE64: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 -1
; WAVE64: [[S_MOV_B64_1:%[0-9]+]]:sreg_64 = S_MOV_B64 0 ; WAVE64: [[S_MOV_B64_1:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 0
; WAVE64: S_ENDPGM 0, implicit [[S_MOV_B64_]], implicit [[S_MOV_B64_1]] ; WAVE64: S_ENDPGM 0, implicit [[S_MOV_B64_]], implicit [[S_MOV_B64_1]]
; WAVE32-LABEL: name: constant_i1_vcc ; WAVE32-LABEL: name: constant_i1_vcc
; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1 ; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 -1
; WAVE32: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0 ; WAVE32: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 0
; WAVE32: S_ENDPGM 0, implicit [[S_MOV_B32_]], implicit [[S_MOV_B32_1]] ; WAVE32: S_ENDPGM 0, implicit [[S_MOV_B32_]], implicit [[S_MOV_B32_1]]
%0:vcc(s1) = G_CONSTANT i1 true %0:vcc(s1) = G_CONSTANT i1 true
%1:vcc(s1) = G_CONSTANT i1 false %1:vcc(s1) = G_CONSTANT i1 false
S_ENDPGM 0 , implicit %0 , implicit %1 S_ENDPGM 0 , implicit %0 , implicit %1
... ...
--- ---
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llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.mir

Show All 31 Lines
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_oeq_s32_vv ; WAVE64-LABEL: name: fcmp_oeq_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_EQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64_xexec = nofpexcept V_CMP_EQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2 ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_oeq_s32_vv ; WAVE32-LABEL: name: fcmp_oeq_s32_vv
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_EQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32_xm0_xexec = nofpexcept V_CMP_EQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2 ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(oeq), %0, %1 %2:vcc(s1) = G_FCMP floatpred(oeq), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_ogt_s32_vv name: fcmp_ogt_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_ogt_s32_vv ; WAVE64-LABEL: name: fcmp_ogt_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_GT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64_xexec = nofpexcept V_CMP_GT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2 ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_ogt_s32_vv ; WAVE32-LABEL: name: fcmp_ogt_s32_vv
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_GT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32_xm0_xexec = nofpexcept V_CMP_GT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2 ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(ogt), %0, %1 %2:vcc(s1) = G_FCMP floatpred(ogt), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_oge_s32_vv name: fcmp_oge_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_oge_s32_vv ; WAVE64-LABEL: name: fcmp_oge_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_GE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64_xexec = nofpexcept V_CMP_GE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2 ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_oge_s32_vv ; WAVE32-LABEL: name: fcmp_oge_s32_vv
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_GE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32_xm0_xexec = nofpexcept V_CMP_GE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2 ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(oge), %0, %1 %2:vcc(s1) = G_FCMP floatpred(oge), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_olt_s32_vv name: fcmp_olt_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_olt_s32_vv ; WAVE64-LABEL: name: fcmp_olt_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_LT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64_xexec = nofpexcept V_CMP_LT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2 ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_olt_s32_vv ; WAVE32-LABEL: name: fcmp_olt_s32_vv
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_LT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32_xm0_xexec = nofpexcept V_CMP_LT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2 ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(olt), %0, %1 %2:vcc(s1) = G_FCMP floatpred(olt), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_ole_s32_vv name: fcmp_ole_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_ole_s32_vv ; WAVE64-LABEL: name: fcmp_ole_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_LE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64_xexec = nofpexcept V_CMP_LE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2 ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_ole_s32_vv ; WAVE32-LABEL: name: fcmp_ole_s32_vv
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_LE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32_xm0_xexec = nofpexcept V_CMP_LE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2 ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(ole), %0, %1 %2:vcc(s1) = G_FCMP floatpred(ole), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_one_s32_vv name: fcmp_one_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_one_s32_vv ; WAVE64-LABEL: name: fcmp_one_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_LG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64_xexec = nofpexcept V_CMP_LG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2 ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_one_s32_vv ; WAVE32-LABEL: name: fcmp_one_s32_vv
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_LG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32_xm0_xexec = nofpexcept V_CMP_LG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2 ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(one), %0, %1 %2:vcc(s1) = G_FCMP floatpred(one), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_ord_s32_vv name: fcmp_ord_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_ord_s32_vv ; WAVE64-LABEL: name: fcmp_ord_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_O_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64_xexec = nofpexcept V_CMP_O_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2 ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_ord_s32_vv ; WAVE32-LABEL: name: fcmp_ord_s32_vv
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_O_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32_xm0_xexec = nofpexcept V_CMP_O_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2 ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(ord), %0, %1 %2:vcc(s1) = G_FCMP floatpred(ord), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_uno_s32_vv name: fcmp_uno_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_uno_s32_vv ; WAVE64-LABEL: name: fcmp_uno_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_U_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64_xexec = nofpexcept V_CMP_U_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2 ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_uno_s32_vv ; WAVE32-LABEL: name: fcmp_uno_s32_vv
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_U_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32_xm0_xexec = nofpexcept V_CMP_U_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2 ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(uno), %0, %1 %2:vcc(s1) = G_FCMP floatpred(uno), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_ueq_s32_vv name: fcmp_ueq_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_ueq_s32_vv ; WAVE64-LABEL: name: fcmp_ueq_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_NLG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64_xexec = nofpexcept V_CMP_NLG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2 ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_ueq_s32_vv ; WAVE32-LABEL: name: fcmp_ueq_s32_vv
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_NLG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32_xm0_xexec = nofpexcept V_CMP_NLG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2 ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(ueq), %0, %1 %2:vcc(s1) = G_FCMP floatpred(ueq), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_ugt_s32_vv name: fcmp_ugt_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_ugt_s32_vv ; WAVE64-LABEL: name: fcmp_ugt_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_NLE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64_xexec = nofpexcept V_CMP_NLE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2 ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_ugt_s32_vv ; WAVE32-LABEL: name: fcmp_ugt_s32_vv
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_NLE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32_xm0_xexec = nofpexcept V_CMP_NLE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2 ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(ugt), %0, %1 %2:vcc(s1) = G_FCMP floatpred(ugt), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_uge_s32_vv name: fcmp_uge_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_uge_s32_vv ; WAVE64-LABEL: name: fcmp_uge_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_NLT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64_xexec = nofpexcept V_CMP_NLT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2 ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_uge_s32_vv ; WAVE32-LABEL: name: fcmp_uge_s32_vv
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_NLT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32_xm0_xexec = nofpexcept V_CMP_NLT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2 ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(uge), %0, %1 %2:vcc(s1) = G_FCMP floatpred(uge), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_ult_s32_vv name: fcmp_ult_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_ult_s32_vv ; WAVE64-LABEL: name: fcmp_ult_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_NGE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64_xexec = nofpexcept V_CMP_NGE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2 ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_ult_s32_vv ; WAVE32-LABEL: name: fcmp_ult_s32_vv
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_NGE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32_xm0_xexec = nofpexcept V_CMP_NGE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2 ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(ult), %0, %1 %2:vcc(s1) = G_FCMP floatpred(ult), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_ule_s32_vv name: fcmp_ule_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_ule_s32_vv ; WAVE64-LABEL: name: fcmp_ule_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_NGT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64_xexec = nofpexcept V_CMP_NGT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2 ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_ule_s32_vv ; WAVE32-LABEL: name: fcmp_ule_s32_vv
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_NGT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32_xm0_xexec = nofpexcept V_CMP_NGT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2 ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(ule), %0, %1 %2:vcc(s1) = G_FCMP floatpred(ule), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_une_s32_vv name: fcmp_une_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_une_s32_vv ; WAVE64-LABEL: name: fcmp_une_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_NEQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64_xexec = nofpexcept V_CMP_NEQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2 ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_une_s32_vv ; WAVE32-LABEL: name: fcmp_une_s32_vv
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_NEQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32_xm0_xexec = nofpexcept V_CMP_NEQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2 ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(une), %0, %1 %2:vcc(s1) = G_FCMP floatpred(une), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_oeq_s64_vv ; WAVE64-LABEL: name: fcmp_oeq_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_EQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64_xexec = nofpexcept V_CMP_EQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2 ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_oeq_s64_vv ; WAVE32-LABEL: name: fcmp_oeq_s64_vv
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_EQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32_xm0_xexec = nofpexcept V_CMP_EQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2 ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3 %1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(oeq), %0, %1 %2:vcc(s1) = G_FCMP floatpred(oeq), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_ogt_s64_vv name: fcmp_ogt_s64_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_ogt_s64_vv ; WAVE64-LABEL: name: fcmp_ogt_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_GT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64_xexec = nofpexcept V_CMP_GT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2 ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_ogt_s64_vv ; WAVE32-LABEL: name: fcmp_ogt_s64_vv
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_GT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32_xm0_xexec = nofpexcept V_CMP_GT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2 ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3 %1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(ogt), %0, %1 %2:vcc(s1) = G_FCMP floatpred(ogt), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_oge_s64_vv name: fcmp_oge_s64_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_oge_s64_vv ; WAVE64-LABEL: name: fcmp_oge_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_GE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64_xexec = nofpexcept V_CMP_GE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2 ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_oge_s64_vv ; WAVE32-LABEL: name: fcmp_oge_s64_vv
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_GE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32_xm0_xexec = nofpexcept V_CMP_GE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2 ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3 %1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(oge), %0, %1 %2:vcc(s1) = G_FCMP floatpred(oge), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_olt_s64_vv name: fcmp_olt_s64_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_olt_s64_vv ; WAVE64-LABEL: name: fcmp_olt_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_LT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64_xexec = nofpexcept V_CMP_LT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2 ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_olt_s64_vv ; WAVE32-LABEL: name: fcmp_olt_s64_vv
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_LT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32_xm0_xexec = nofpexcept V_CMP_LT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2 ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3 %1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(olt), %0, %1 %2:vcc(s1) = G_FCMP floatpred(olt), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_ole_s64_vv name: fcmp_ole_s64_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_ole_s64_vv ; WAVE64-LABEL: name: fcmp_ole_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_LE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64_xexec = nofpexcept V_CMP_LE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2 ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_ole_s64_vv ; WAVE32-LABEL: name: fcmp_ole_s64_vv
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_LE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32_xm0_xexec = nofpexcept V_CMP_LE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2 ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3 %1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(ole), %0, %1 %2:vcc(s1) = G_FCMP floatpred(ole), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_one_s64_vv name: fcmp_one_s64_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_one_s64_vv ; WAVE64-LABEL: name: fcmp_one_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_LG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64_xexec = nofpexcept V_CMP_LG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2 ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_one_s64_vv ; WAVE32-LABEL: name: fcmp_one_s64_vv
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_LG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32_xm0_xexec = nofpexcept V_CMP_LG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2 ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3 %1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(one), %0, %1 %2:vcc(s1) = G_FCMP floatpred(one), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_ord_s64_vv name: fcmp_ord_s64_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_ord_s64_vv ; WAVE64-LABEL: name: fcmp_ord_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_O_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64_xexec = nofpexcept V_CMP_O_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2 ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_ord_s64_vv ; WAVE32-LABEL: name: fcmp_ord_s64_vv
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_O_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32_xm0_xexec = nofpexcept V_CMP_O_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2 ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3 %1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(ord), %0, %1 %2:vcc(s1) = G_FCMP floatpred(ord), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_uno_s64_vv name: fcmp_uno_s64_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_uno_s64_vv ; WAVE64-LABEL: name: fcmp_uno_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_U_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64_xexec = nofpexcept V_CMP_U_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2 ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_uno_s64_vv ; WAVE32-LABEL: name: fcmp_uno_s64_vv
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_U_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32_xm0_xexec = nofpexcept V_CMP_U_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2 ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3 %1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(uno), %0, %1 %2:vcc(s1) = G_FCMP floatpred(uno), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_ueq_s64_vv name: fcmp_ueq_s64_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_ueq_s64_vv ; WAVE64-LABEL: name: fcmp_ueq_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_NLG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64_xexec = nofpexcept V_CMP_NLG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2 ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_ueq_s64_vv ; WAVE32-LABEL: name: fcmp_ueq_s64_vv
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_NLG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32_xm0_xexec = nofpexcept V_CMP_NLG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2 ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3 %1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(ueq), %0, %1 %2:vcc(s1) = G_FCMP floatpred(ueq), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_ugt_s64_vv name: fcmp_ugt_s64_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_ugt_s64_vv ; WAVE64-LABEL: name: fcmp_ugt_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_NLE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64_xexec = nofpexcept V_CMP_NLE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2 ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_ugt_s64_vv ; WAVE32-LABEL: name: fcmp_ugt_s64_vv
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_NLE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32_xm0_xexec = nofpexcept V_CMP_NLE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2 ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3 %1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(ugt), %0, %1 %2:vcc(s1) = G_FCMP floatpred(ugt), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_uge_s64_vv name: fcmp_uge_s64_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_uge_s64_vv ; WAVE64-LABEL: name: fcmp_uge_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_NLT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64_xexec = nofpexcept V_CMP_NLT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2 ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_uge_s64_vv ; WAVE32-LABEL: name: fcmp_uge_s64_vv
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_NLT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32_xm0_xexec = nofpexcept V_CMP_NLT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2 ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3 %1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(uge), %0, %1 %2:vcc(s1) = G_FCMP floatpred(uge), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_ult_s64_vv name: fcmp_ult_s64_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_ult_s64_vv ; WAVE64-LABEL: name: fcmp_ult_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_NGE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64_xexec = nofpexcept V_CMP_NGE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2 ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_ult_s64_vv ; WAVE32-LABEL: name: fcmp_ult_s64_vv
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_NGE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32_xm0_xexec = nofpexcept V_CMP_NGE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2 ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3 %1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(ult), %0, %1 %2:vcc(s1) = G_FCMP floatpred(ult), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_ule_s64_vv name: fcmp_ule_s64_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_ule_s64_vv ; WAVE64-LABEL: name: fcmp_ule_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_NGT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64_xexec = nofpexcept V_CMP_NGT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2 ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_ule_s64_vv ; WAVE32-LABEL: name: fcmp_ule_s64_vv
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_NGT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32_xm0_xexec = nofpexcept V_CMP_NGT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2 ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3 %1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(ule), %0, %1 %2:vcc(s1) = G_FCMP floatpred(ule), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_une_s64_vv name: fcmp_une_s64_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_une_s64_vv ; WAVE64-LABEL: name: fcmp_une_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_NEQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64_xexec = nofpexcept V_CMP_NEQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2 ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_une_s64_vv ; WAVE32-LABEL: name: fcmp_une_s64_vv
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_NEQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32_xm0_xexec = nofpexcept V_CMP_NEQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2 ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3 %1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(une), %0, %1 %2:vcc(s1) = G_FCMP floatpred(une), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
▲ Show 20 Lines • Show All 49 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir

Show All 37 Lines
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_oeq_s16_vv ; WAVE64-LABEL: name: fcmp_oeq_s16_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: %4:sreg_64 = nofpexcept V_CMP_EQ_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %4:sreg_64_xexec = nofpexcept V_CMP_EQ_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %4 ; WAVE64: S_ENDPGM 0, implicit %4
; WAVE32-LABEL: name: fcmp_oeq_s16_vv ; WAVE32-LABEL: name: fcmp_oeq_s16_vv
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: %4:sreg_32 = nofpexcept V_CMP_EQ_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %4:sreg_32_xm0_xexec = nofpexcept V_CMP_EQ_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %4 ; WAVE32: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_FCMP floatpred(oeq), %2, %3 %4:vcc(s1) = G_FCMP floatpred(oeq), %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: fcmp_ogt_s16_vv name: fcmp_ogt_s16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_ogt_s16_vv ; WAVE64-LABEL: name: fcmp_ogt_s16_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: %4:sreg_64 = nofpexcept V_CMP_GT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %4:sreg_64_xexec = nofpexcept V_CMP_GT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %4 ; WAVE64: S_ENDPGM 0, implicit %4
; WAVE32-LABEL: name: fcmp_ogt_s16_vv ; WAVE32-LABEL: name: fcmp_ogt_s16_vv
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: %4:sreg_32 = nofpexcept V_CMP_GT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %4:sreg_32_xm0_xexec = nofpexcept V_CMP_GT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %4 ; WAVE32: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_FCMP floatpred(ogt), %2, %3 %4:vcc(s1) = G_FCMP floatpred(ogt), %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: fcmp_oge_s16_vv name: fcmp_oge_s16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_oge_s16_vv ; WAVE64-LABEL: name: fcmp_oge_s16_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: %4:sreg_64 = nofpexcept V_CMP_GE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %4:sreg_64_xexec = nofpexcept V_CMP_GE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %4 ; WAVE64: S_ENDPGM 0, implicit %4
; WAVE32-LABEL: name: fcmp_oge_s16_vv ; WAVE32-LABEL: name: fcmp_oge_s16_vv
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: %4:sreg_32 = nofpexcept V_CMP_GE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %4:sreg_32_xm0_xexec = nofpexcept V_CMP_GE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %4 ; WAVE32: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_FCMP floatpred(oge), %2, %3 %4:vcc(s1) = G_FCMP floatpred(oge), %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: fcmp_olt_s16_vv name: fcmp_olt_s16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_olt_s16_vv ; WAVE64-LABEL: name: fcmp_olt_s16_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: %4:sreg_64 = nofpexcept V_CMP_LT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %4:sreg_64_xexec = nofpexcept V_CMP_LT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %4 ; WAVE64: S_ENDPGM 0, implicit %4
; WAVE32-LABEL: name: fcmp_olt_s16_vv ; WAVE32-LABEL: name: fcmp_olt_s16_vv
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: %4:sreg_32 = nofpexcept V_CMP_LT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %4:sreg_32_xm0_xexec = nofpexcept V_CMP_LT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %4 ; WAVE32: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_FCMP floatpred(olt), %2, %3 %4:vcc(s1) = G_FCMP floatpred(olt), %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: fcmp_ole_s16_vv name: fcmp_ole_s16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_ole_s16_vv ; WAVE64-LABEL: name: fcmp_ole_s16_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: %4:sreg_64 = nofpexcept V_CMP_LE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %4:sreg_64_xexec = nofpexcept V_CMP_LE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %4 ; WAVE64: S_ENDPGM 0, implicit %4
; WAVE32-LABEL: name: fcmp_ole_s16_vv ; WAVE32-LABEL: name: fcmp_ole_s16_vv
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: %4:sreg_32 = nofpexcept V_CMP_LE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %4:sreg_32_xm0_xexec = nofpexcept V_CMP_LE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %4 ; WAVE32: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_FCMP floatpred(ole), %2, %3 %4:vcc(s1) = G_FCMP floatpred(ole), %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: fcmp_one_s16_vv name: fcmp_one_s16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_one_s16_vv ; WAVE64-LABEL: name: fcmp_one_s16_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: %4:sreg_64 = nofpexcept V_CMP_LG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %4:sreg_64_xexec = nofpexcept V_CMP_LG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %4 ; WAVE64: S_ENDPGM 0, implicit %4
; WAVE32-LABEL: name: fcmp_one_s16_vv ; WAVE32-LABEL: name: fcmp_one_s16_vv
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: %4:sreg_32 = nofpexcept V_CMP_LG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %4:sreg_32_xm0_xexec = nofpexcept V_CMP_LG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %4 ; WAVE32: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_FCMP floatpred(one), %2, %3 %4:vcc(s1) = G_FCMP floatpred(one), %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: fcmp_ord_s16_vv name: fcmp_ord_s16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_ord_s16_vv ; WAVE64-LABEL: name: fcmp_ord_s16_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: %4:sreg_64 = nofpexcept V_CMP_LG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %4:sreg_64_xexec = nofpexcept V_CMP_LG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %4 ; WAVE64: S_ENDPGM 0, implicit %4
; WAVE32-LABEL: name: fcmp_ord_s16_vv ; WAVE32-LABEL: name: fcmp_ord_s16_vv
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: %4:sreg_32 = nofpexcept V_CMP_LG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %4:sreg_32_xm0_xexec = nofpexcept V_CMP_LG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %4 ; WAVE32: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_FCMP floatpred(one), %2, %3 %4:vcc(s1) = G_FCMP floatpred(one), %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: fcmp_uno_s16_vv name: fcmp_uno_s16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_uno_s16_vv ; WAVE64-LABEL: name: fcmp_uno_s16_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: %4:sreg_64 = nofpexcept V_CMP_U_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %4:sreg_64_xexec = nofpexcept V_CMP_U_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %4 ; WAVE64: S_ENDPGM 0, implicit %4
; WAVE32-LABEL: name: fcmp_uno_s16_vv ; WAVE32-LABEL: name: fcmp_uno_s16_vv
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: %4:sreg_32 = nofpexcept V_CMP_U_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %4:sreg_32_xm0_xexec = nofpexcept V_CMP_U_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %4 ; WAVE32: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_FCMP floatpred(uno), %2, %3 %4:vcc(s1) = G_FCMP floatpred(uno), %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: fcmp_ueq_s16_vv name: fcmp_ueq_s16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_ueq_s16_vv ; WAVE64-LABEL: name: fcmp_ueq_s16_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: %4:sreg_64 = nofpexcept V_CMP_NLG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %4:sreg_64_xexec = nofpexcept V_CMP_NLG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %4 ; WAVE64: S_ENDPGM 0, implicit %4
; WAVE32-LABEL: name: fcmp_ueq_s16_vv ; WAVE32-LABEL: name: fcmp_ueq_s16_vv
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: %4:sreg_32 = nofpexcept V_CMP_NLG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %4:sreg_32_xm0_xexec = nofpexcept V_CMP_NLG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %4 ; WAVE32: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_FCMP floatpred(ueq), %2, %3 %4:vcc(s1) = G_FCMP floatpred(ueq), %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: fcmp_ugt_s16_vv name: fcmp_ugt_s16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_ugt_s16_vv ; WAVE64-LABEL: name: fcmp_ugt_s16_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: %4:sreg_64 = nofpexcept V_CMP_NLE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %4:sreg_64_xexec = nofpexcept V_CMP_NLE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %4 ; WAVE64: S_ENDPGM 0, implicit %4
; WAVE32-LABEL: name: fcmp_ugt_s16_vv ; WAVE32-LABEL: name: fcmp_ugt_s16_vv
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: %4:sreg_32 = nofpexcept V_CMP_NLE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %4:sreg_32_xm0_xexec = nofpexcept V_CMP_NLE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %4 ; WAVE32: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_FCMP floatpred(ugt), %2, %3 %4:vcc(s1) = G_FCMP floatpred(ugt), %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: fcmp_uge_s16_vv name: fcmp_uge_s16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_uge_s16_vv ; WAVE64-LABEL: name: fcmp_uge_s16_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: %4:sreg_64 = nofpexcept V_CMP_NLT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %4:sreg_64_xexec = nofpexcept V_CMP_NLT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %4 ; WAVE64: S_ENDPGM 0, implicit %4
; WAVE32-LABEL: name: fcmp_uge_s16_vv ; WAVE32-LABEL: name: fcmp_uge_s16_vv
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: %4:sreg_32 = nofpexcept V_CMP_NLT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %4:sreg_32_xm0_xexec = nofpexcept V_CMP_NLT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %4 ; WAVE32: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_FCMP floatpred(uge), %2, %3 %4:vcc(s1) = G_FCMP floatpred(uge), %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: fcmp_ult_s16_vv name: fcmp_ult_s16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_ult_s16_vv ; WAVE64-LABEL: name: fcmp_ult_s16_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: %4:sreg_64 = nofpexcept V_CMP_NGE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %4:sreg_64_xexec = nofpexcept V_CMP_NGE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %4 ; WAVE64: S_ENDPGM 0, implicit %4
; WAVE32-LABEL: name: fcmp_ult_s16_vv ; WAVE32-LABEL: name: fcmp_ult_s16_vv
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: %4:sreg_32 = nofpexcept V_CMP_NGE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %4:sreg_32_xm0_xexec = nofpexcept V_CMP_NGE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %4 ; WAVE32: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_FCMP floatpred(ult), %2, %3 %4:vcc(s1) = G_FCMP floatpred(ult), %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: fcmp_ule_s16_vv name: fcmp_ule_s16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_ule_s16_vv ; WAVE64-LABEL: name: fcmp_ule_s16_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: %4:sreg_64 = nofpexcept V_CMP_NGT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %4:sreg_64_xexec = nofpexcept V_CMP_NGT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %4 ; WAVE64: S_ENDPGM 0, implicit %4
; WAVE32-LABEL: name: fcmp_ule_s16_vv ; WAVE32-LABEL: name: fcmp_ule_s16_vv
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: %4:sreg_32 = nofpexcept V_CMP_NGT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %4:sreg_32_xm0_xexec = nofpexcept V_CMP_NGT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %4 ; WAVE32: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_FCMP floatpred(ule), %2, %3 %4:vcc(s1) = G_FCMP floatpred(ule), %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: fcmp_une_s16_vv name: fcmp_une_s16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_une_s16_vv ; WAVE64-LABEL: name: fcmp_une_s16_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: %4:sreg_64 = nofpexcept V_CMP_NEQ_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %4:sreg_64_xexec = nofpexcept V_CMP_NEQ_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %4 ; WAVE64: S_ENDPGM 0, implicit %4
; WAVE32-LABEL: name: fcmp_une_s16_vv ; WAVE32-LABEL: name: fcmp_une_s16_vv
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: %4:sreg_32 = nofpexcept V_CMP_NEQ_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %4:sreg_32_xm0_xexec = nofpexcept V_CMP_NEQ_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %4 ; WAVE32: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_FCMP floatpred(une), %2, %3 %4:vcc(s1) = G_FCMP floatpred(une), %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
Show All 31 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s16.mir

Show All 9 Lines
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $vgpr0 liveins: $sgpr0, $vgpr0
; WAVE64-LABEL: name: icmp_eq_s16_sv ; WAVE64-LABEL: name: icmp_eq_s16_sv
; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[V_CMP_EQ_U16_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U16_e64 [[COPY]], [[COPY1]], implicit $exec ; WAVE64: [[V_CMP_EQ_U16_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U16_e64 [[COPY]], [[COPY1]], implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_EQ_U16_e64_]] ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_EQ_U16_e64_]]
; WAVE32-LABEL: name: icmp_eq_s16_sv ; WAVE32-LABEL: name: icmp_eq_s16_sv
; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[V_CMP_EQ_U16_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_U16_e64 [[COPY]], [[COPY1]], implicit $exec ; WAVE32: [[V_CMP_EQ_U16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U16_e64 [[COPY]], [[COPY1]], implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_EQ_U16_e64_]] ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_EQ_U16_e64_]]
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0 %1:vgpr(s32) = COPY $vgpr0
%2:sgpr(s16) = G_TRUNC %0 %2:sgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_ICMP intpred(eq), %2, %3 %4:vcc(s1) = G_ICMP intpred(eq), %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: icmp_eq_s16_vs name: icmp_eq_s16_vs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $vgpr0 liveins: $sgpr0, $vgpr0
; WAVE64-LABEL: name: icmp_eq_s16_vs ; WAVE64-LABEL: name: icmp_eq_s16_vs
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE64: [[V_CMP_EQ_U16_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U16_e64 [[COPY]], [[COPY1]], implicit $exec ; WAVE64: [[V_CMP_EQ_U16_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U16_e64 [[COPY]], [[COPY1]], implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_EQ_U16_e64_]] ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_EQ_U16_e64_]]
; WAVE32-LABEL: name: icmp_eq_s16_vs ; WAVE32-LABEL: name: icmp_eq_s16_vs
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE32: [[V_CMP_EQ_U16_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_U16_e64 [[COPY]], [[COPY1]], implicit $exec ; WAVE32: [[V_CMP_EQ_U16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U16_e64 [[COPY]], [[COPY1]], implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_EQ_U16_e64_]] ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_EQ_U16_e64_]]
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:sgpr(s32) = COPY $sgpr0 %1:sgpr(s32) = COPY $sgpr0
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:sgpr(s16) = G_TRUNC %1 %3:sgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_ICMP intpred(eq), %2, %3 %4:vcc(s1) = G_ICMP intpred(eq), %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: icmp_eq_s16_vv name: icmp_eq_s16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: icmp_eq_s16_vv ; WAVE64-LABEL: name: icmp_eq_s16_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_EQ_U16_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U16_e64 [[COPY]], [[COPY1]], implicit $exec ; WAVE64: [[V_CMP_EQ_U16_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U16_e64 [[COPY]], [[COPY1]], implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_EQ_U16_e64_]] ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_EQ_U16_e64_]]
; WAVE32-LABEL: name: icmp_eq_s16_vv ; WAVE32-LABEL: name: icmp_eq_s16_vv
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_EQ_U16_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_U16_e64 [[COPY]], [[COPY1]], implicit $exec ; WAVE32: [[V_CMP_EQ_U16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U16_e64 [[COPY]], [[COPY1]], implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_EQ_U16_e64_]] ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_EQ_U16_e64_]]
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_ICMP intpred(eq), %2, %3 %4:vcc(s1) = G_ICMP intpred(eq), %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: icmp_ne_s16_vv name: icmp_ne_s16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: icmp_ne_s16_vv ; WAVE64-LABEL: name: icmp_ne_s16_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_NE_U16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U16_e64 [[COPY]], [[COPY1]], implicit $exec ; WAVE64: [[V_CMP_NE_U16_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U16_e64 [[COPY]], [[COPY1]], implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NE_U16_e64_]] ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NE_U16_e64_]]
; WAVE32-LABEL: name: icmp_ne_s16_vv ; WAVE32-LABEL: name: icmp_ne_s16_vv
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_NE_U16_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U16_e64 [[COPY]], [[COPY1]], implicit $exec ; WAVE32: [[V_CMP_NE_U16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U16_e64 [[COPY]], [[COPY1]], implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NE_U16_e64_]] ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NE_U16_e64_]]
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_ICMP intpred(ne), %2, %3 %4:vcc(s1) = G_ICMP intpred(ne), %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: icmp_slt_s16_vv name: icmp_slt_s16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: icmp_slt_s16_vv ; WAVE64-LABEL: name: icmp_slt_s16_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_LT_I16_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_I16_e64 [[COPY]], [[COPY1]], implicit $exec ; WAVE64: [[V_CMP_LT_I16_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_LT_I16_e64 [[COPY]], [[COPY1]], implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LT_I16_e64_]] ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LT_I16_e64_]]
; WAVE32-LABEL: name: icmp_slt_s16_vv ; WAVE32-LABEL: name: icmp_slt_s16_vv
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_LT_I16_e64_:%[0-9]+]]:sreg_32 = V_CMP_LT_I16_e64 [[COPY]], [[COPY1]], implicit $exec ; WAVE32: [[V_CMP_LT_I16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_LT_I16_e64 [[COPY]], [[COPY1]], implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LT_I16_e64_]] ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LT_I16_e64_]]
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_ICMP intpred(slt), %2, %3 %4:vcc(s1) = G_ICMP intpred(slt), %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: icmp_sle_s16_vv name: icmp_sle_s16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: icmp_sle_s16_vv ; WAVE64-LABEL: name: icmp_sle_s16_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_LE_I16_e64_:%[0-9]+]]:sreg_64 = V_CMP_LE_I16_e64 [[COPY]], [[COPY1]], implicit $exec ; WAVE64: [[V_CMP_LE_I16_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_LE_I16_e64 [[COPY]], [[COPY1]], implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LE_I16_e64_]] ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LE_I16_e64_]]
; WAVE32-LABEL: name: icmp_sle_s16_vv ; WAVE32-LABEL: name: icmp_sle_s16_vv
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_LE_I16_e64_:%[0-9]+]]:sreg_32 = V_CMP_LE_I16_e64 [[COPY]], [[COPY1]], implicit $exec ; WAVE32: [[V_CMP_LE_I16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_LE_I16_e64 [[COPY]], [[COPY1]], implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LE_I16_e64_]] ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LE_I16_e64_]]
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_ICMP intpred(sle), %2, %3 %4:vcc(s1) = G_ICMP intpred(sle), %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: icmp_ult_s16_vv name: icmp_ult_s16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: icmp_ult_s16_vv ; WAVE64-LABEL: name: icmp_ult_s16_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_LT_U16_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_U16_e64 [[COPY]], [[COPY1]], implicit $exec ; WAVE64: [[V_CMP_LT_U16_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_LT_U16_e64 [[COPY]], [[COPY1]], implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LT_U16_e64_]] ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LT_U16_e64_]]
; WAVE32-LABEL: name: icmp_ult_s16_vv ; WAVE32-LABEL: name: icmp_ult_s16_vv
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_LT_U16_e64_:%[0-9]+]]:sreg_32 = V_CMP_LT_U16_e64 [[COPY]], [[COPY1]], implicit $exec ; WAVE32: [[V_CMP_LT_U16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_LT_U16_e64 [[COPY]], [[COPY1]], implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LT_U16_e64_]] ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LT_U16_e64_]]
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_ICMP intpred(ult), %2, %3 %4:vcc(s1) = G_ICMP intpred(ult), %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: icmp_ule_s16_vv name: icmp_ule_s16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: icmp_ule_s16_vv ; WAVE64-LABEL: name: icmp_ule_s16_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_LE_U16_e64_:%[0-9]+]]:sreg_64 = V_CMP_LE_U16_e64 [[COPY]], [[COPY1]], implicit $exec ; WAVE64: [[V_CMP_LE_U16_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_LE_U16_e64 [[COPY]], [[COPY1]], implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LE_U16_e64_]] ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LE_U16_e64_]]
; WAVE32-LABEL: name: icmp_ule_s16_vv ; WAVE32-LABEL: name: icmp_ule_s16_vv
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_LE_U16_e64_:%[0-9]+]]:sreg_32 = V_CMP_LE_U16_e64 [[COPY]], [[COPY1]], implicit $exec ; WAVE32: [[V_CMP_LE_U16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_LE_U16_e64 [[COPY]], [[COPY1]], implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LE_U16_e64_]] ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LE_U16_e64_]]
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_ICMP intpred(ule), %2, %3 %4:vcc(s1) = G_ICMP intpred(ule), %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir

Show All 12 Lines
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: or_s1_vcc_vcc_vcc ; WAVE64-LABEL: name: or_s1_vcc_vcc_vcc
; WAVE64: liveins: $vgpr0, $vgpr1 ; WAVE64: liveins: $vgpr0, $vgpr1
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec ; WAVE64: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; WAVE64: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec ; WAVE64: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
; WAVE64: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec ; WAVE64: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]], implicit-def dead $scc ; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64_xexec = S_OR_B64 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]], implicit-def dead $scc
; WAVE64: S_ENDPGM 0, implicit [[S_OR_B64_]] ; WAVE64: S_ENDPGM 0, implicit [[S_OR_B64_]]
; WAVE32-LABEL: name: or_s1_vcc_vcc_vcc ; WAVE32-LABEL: name: or_s1_vcc_vcc_vcc
; WAVE32: liveins: $vgpr0, $vgpr1 ; WAVE32: liveins: $vgpr0, $vgpr1
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec ; WAVE32: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; WAVE32: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec ; WAVE32: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
; WAVE32: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_EQ_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec ; WAVE32: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]], implicit-def dead $scc ; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_OR_B32 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]], implicit-def dead $scc
; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]] ; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s32) = G_CONSTANT i32 0 %2:vgpr(s32) = G_CONSTANT i32 0
%3:vcc(s1) = G_ICMP intpred(eq), %0, %2 %3:vcc(s1) = G_ICMP intpred(eq), %0, %2
%4:vcc(s1) = G_ICMP intpred(eq), %1, %2 %4:vcc(s1) = G_ICMP intpred(eq), %1, %2
%5:vcc(s1) = G_OR %3, %4 %5:vcc(s1) = G_OR %3, %4
S_ENDPGM 0, implicit %5 S_ENDPGM 0, implicit %5
▲ Show 20 Lines • Show All 326 Lines • ▼ Show 20 Lines
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: or_s1_vcc_copy_to_vcc ; WAVE64-LABEL: name: or_s1_vcc_copy_to_vcc
; WAVE64: liveins: $vgpr0, $vgpr1 ; WAVE64: liveins: $vgpr0, $vgpr1
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec ; WAVE64: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec ; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
; WAVE64: [[V_AND_B32_e32_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY1]], implicit $exec ; WAVE64: [[V_AND_B32_e32_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY1]], implicit $exec
; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_1]], implicit $exec ; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_1]], implicit $exec
; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc ; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64_xexec = S_OR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
; WAVE64: S_ENDPGM 0, implicit [[S_OR_B64_]] ; WAVE64: S_ENDPGM 0, implicit [[S_OR_B64_]]
; WAVE32-LABEL: name: or_s1_vcc_copy_to_vcc ; WAVE32-LABEL: name: or_s1_vcc_copy_to_vcc
; WAVE32: liveins: $vgpr0, $vgpr1 ; WAVE32: liveins: $vgpr0, $vgpr1
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec ; WAVE32: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec ; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
; WAVE32: [[V_AND_B32_e32_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY1]], implicit $exec ; WAVE32: [[V_AND_B32_e32_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY1]], implicit $exec
; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_1]], implicit $exec ; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_1]], implicit $exec
; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc ; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_OR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]] ; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s1) = G_TRUNC %0 %2:vgpr(s1) = G_TRUNC %0
%3:vgpr(s1) = G_TRUNC %1 %3:vgpr(s1) = G_TRUNC %1
%4:vcc(s1) = COPY %2 %4:vcc(s1) = COPY %2
%5:vcc(s1) = COPY %3 %5:vcc(s1) = COPY %3
%6:vcc(s1) = G_OR %4, %5 %6:vcc(s1) = G_OR %4, %5
Show All 13 Linesbody: |
bb.0: bb.0:
liveins: $vgpr0, $sgpr0 liveins: $vgpr0, $sgpr0
; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave32 ; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
; WAVE64: liveins: $vgpr0, $sgpr0 ; WAVE64: liveins: $vgpr0, $sgpr0
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: %sgpr0:sreg_32 = COPY $sgpr0 ; WAVE64: %sgpr0:sreg_32 = COPY $sgpr0
; WAVE64: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec ; WAVE64: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec ; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def $scc ; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def $scc
; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec ; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64_xexec = S_OR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc ; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64_xexec = S_OR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
; WAVE64: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_OR_B64_]] ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_OR_B64_]]
; WAVE64: S_ENDPGM 0, implicit [[COPY1]] ; WAVE64: S_ENDPGM 0, implicit [[COPY1]]
; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave32 ; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
; WAVE32: liveins: $vgpr0, $sgpr0 ; WAVE32: liveins: $vgpr0, $sgpr0
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: %sgpr0:sreg_32 = COPY $sgpr0 ; WAVE32: %sgpr0:sreg_32 = COPY $sgpr0
; WAVE32: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec ; WAVE32: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec ; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def $scc ; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def $scc
; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec ; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc ; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_OR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_OR_B32_]] ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_OR_B32_]]
; WAVE32: S_ENDPGM 0, implicit [[COPY1]] ; WAVE32: S_ENDPGM 0, implicit [[COPY1]]
%1:vgpr(s32) = COPY $vgpr0 %1:vgpr(s32) = COPY $vgpr0
%0:vgpr(s1) = G_TRUNC %1(s32) %0:vgpr(s1) = G_TRUNC %1(s32)
%sgpr0:sgpr(s32) = COPY $sgpr0 %sgpr0:sgpr(s32) = COPY $sgpr0
%2:sgpr(s1) = G_TRUNC %sgpr0 %2:sgpr(s1) = G_TRUNC %sgpr0
%6:sgpr(s32) = G_CONSTANT i32 0 %6:sgpr(s32) = G_CONSTANT i32 0
%7:sgpr(p1) = G_IMPLICIT_DEF %7:sgpr(p1) = G_IMPLICIT_DEF
Show All 15 Linesbody: |
bb.0: bb.0:
liveins: $vgpr0, $sgpr0 liveins: $vgpr0, $sgpr0
; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave64 ; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave64
; WAVE64: liveins: $vgpr0, $sgpr0 ; WAVE64: liveins: $vgpr0, $sgpr0
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: %sgpr0:sreg_32 = COPY $sgpr0 ; WAVE64: %sgpr0:sreg_32 = COPY $sgpr0
; WAVE64: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec ; WAVE64: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec ; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def $scc ; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def $scc
; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec ; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc ; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64_xexec = S_OR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
; WAVE64: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[S_OR_B64_]] ; WAVE64: S_ENDPGM 0, implicit [[S_OR_B64_]]
; WAVE64: S_ENDPGM 0, implicit [[COPY1]]
; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave64 ; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave64
; WAVE32: liveins: $vgpr0, $sgpr0 ; WAVE32: liveins: $vgpr0, $sgpr0
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: %sgpr0:sreg_32 = COPY $sgpr0 ; WAVE32: %sgpr0:sreg_32 = COPY $sgpr0
; WAVE32: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec ; WAVE32: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec ; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def $scc ; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def $scc
; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec ; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_OR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc ; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_OR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
; WAVE32: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[S_OR_B32_]] ; WAVE32: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[S_OR_B32_]]
; WAVE32: S_ENDPGM 0, implicit [[COPY1]] ; WAVE32: S_ENDPGM 0, implicit [[COPY1]]
%1:vgpr(s32) = COPY $vgpr0 %1:vgpr(s32) = COPY $vgpr0
%0:vgpr(s1) = G_TRUNC %1(s32) %0:vgpr(s1) = G_TRUNC %1(s32)
%sgpr0:sgpr(s32) = COPY $sgpr0 %sgpr0:sgpr(s32) = COPY $sgpr0
%2:sgpr(s1) = G_TRUNC %sgpr0 %2:sgpr(s1) = G_TRUNC %sgpr0
%6:sgpr(s32) = G_CONSTANT i32 0 %6:sgpr(s32) = G_CONSTANT i32 0
%7:sgpr(p1) = G_IMPLICIT_DEF %7:sgpr(p1) = G_IMPLICIT_DEF
%9:vcc(s1) = COPY %0(s1) %9:vcc(s1) = COPY %0(s1)
%10:vcc(s1) = COPY %2(s1) %10:vcc(s1) = COPY %2(s1)
%8:vcc(s1) = G_OR %9, %10 %8:vcc(s1) = G_OR %9, %10
%3:sreg_64_xexec(s1) = COPY %8(s1) %3:sreg_64_xexec(s1) = COPY %8(s1)
S_ENDPGM 0, implicit %3 S_ENDPGM 0, implicit %3
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir

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body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: xor_s1_vcc_vcc_vcc ; WAVE64-LABEL: name: xor_s1_vcc_vcc_vcc
; WAVE64: liveins: $vgpr0, $vgpr1 ; WAVE64: liveins: $vgpr0, $vgpr1
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec ; WAVE64: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; WAVE64: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec ; WAVE64: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
; WAVE64: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec ; WAVE64: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
; WAVE64: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]], implicit-def dead $scc ; WAVE64: [[S_XOR_B64_:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]], implicit-def dead $scc
; WAVE64: S_ENDPGM 0, implicit [[S_XOR_B64_]] ; WAVE64: S_ENDPGM 0, implicit [[S_XOR_B64_]]
; WAVE32-LABEL: name: xor_s1_vcc_vcc_vcc ; WAVE32-LABEL: name: xor_s1_vcc_vcc_vcc
; WAVE32: liveins: $vgpr0, $vgpr1 ; WAVE32: liveins: $vgpr0, $vgpr1
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec ; WAVE32: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; WAVE32: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec ; WAVE32: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
; WAVE32: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_EQ_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec ; WAVE32: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]], implicit-def dead $scc ; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_XOR_B32 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]], implicit-def dead $scc
; WAVE32: S_ENDPGM 0, implicit [[S_XOR_B32_]] ; WAVE32: S_ENDPGM 0, implicit [[S_XOR_B32_]]
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s32) = G_CONSTANT i32 0 %2:vgpr(s32) = G_CONSTANT i32 0
%3:vcc(s1) = G_ICMP intpred(eq), %0, %2 %3:vcc(s1) = G_ICMP intpred(eq), %0, %2
%4:vcc(s1) = G_ICMP intpred(eq), %1, %2 %4:vcc(s1) = G_ICMP intpred(eq), %1, %2
%5:vcc(s1) = G_XOR %3, %4 %5:vcc(s1) = G_XOR %3, %4
S_ENDPGM 0, implicit %5 S_ENDPGM 0, implicit %5
▲ Show 20 Lines • Show All 327 Lines • ▼ Show 20 Lines
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: xor_s1_vcc_copy_to_vcc ; WAVE64-LABEL: name: xor_s1_vcc_copy_to_vcc
; WAVE64: liveins: $vgpr0, $vgpr1 ; WAVE64: liveins: $vgpr0, $vgpr1
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec ; WAVE64: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec ; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
; WAVE64: [[V_AND_B32_e32_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY1]], implicit $exec ; WAVE64: [[V_AND_B32_e32_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY1]], implicit $exec
; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_1]], implicit $exec ; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_1]], implicit $exec
; WAVE64: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc ; WAVE64: [[S_XOR_B64_:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
; WAVE64: S_ENDPGM 0, implicit [[S_XOR_B64_]] ; WAVE64: S_ENDPGM 0, implicit [[S_XOR_B64_]]
; WAVE32-LABEL: name: xor_s1_vcc_copy_to_vcc ; WAVE32-LABEL: name: xor_s1_vcc_copy_to_vcc
; WAVE32: liveins: $vgpr0, $vgpr1 ; WAVE32: liveins: $vgpr0, $vgpr1
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec ; WAVE32: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec ; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
; WAVE32: [[V_AND_B32_e32_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY1]], implicit $exec ; WAVE32: [[V_AND_B32_e32_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY1]], implicit $exec
; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_1]], implicit $exec ; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_1]], implicit $exec
; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc ; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_XOR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
; WAVE32: S_ENDPGM 0, implicit [[S_XOR_B32_]] ; WAVE32: S_ENDPGM 0, implicit [[S_XOR_B32_]]
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s1) = G_TRUNC %0 %2:vgpr(s1) = G_TRUNC %0
%3:vgpr(s1) = G_TRUNC %1 %3:vgpr(s1) = G_TRUNC %1
%4:vcc(s1) = COPY %2 %4:vcc(s1) = COPY %2
%5:vcc(s1) = COPY %3 %5:vcc(s1) = COPY %3
%6:vcc(s1) = G_XOR %4, %5 %6:vcc(s1) = G_XOR %4, %5
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bb.0: bb.0:
liveins: $vgpr0, $sgpr0 liveins: $vgpr0, $sgpr0
; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave32 ; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
; WAVE64: liveins: $vgpr0, $sgpr0 ; WAVE64: liveins: $vgpr0, $sgpr0
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: %sgpr0:sreg_32 = COPY $sgpr0 ; WAVE64: %sgpr0:sreg_32 = COPY $sgpr0
; WAVE64: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec ; WAVE64: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec ; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def $scc ; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def $scc
; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec ; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
; WAVE64: [[S_XOR_B64_:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc ; WAVE64: [[S_XOR_B64_:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
; WAVE64: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_XOR_B64_]] ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_XOR_B64_]]
; WAVE64: S_ENDPGM 0, implicit [[COPY1]] ; WAVE64: S_ENDPGM 0, implicit [[COPY1]]
; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave32 ; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
; WAVE32: liveins: $vgpr0, $sgpr0 ; WAVE32: liveins: $vgpr0, $sgpr0
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: %sgpr0:sreg_32 = COPY $sgpr0 ; WAVE32: %sgpr0:sreg_32 = COPY $sgpr0
; WAVE32: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec ; WAVE32: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec ; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def $scc ; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def $scc
; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec ; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc ; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_XOR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_XOR_B32_]] ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_XOR_B32_]]
; WAVE32: S_ENDPGM 0, implicit [[COPY1]] ; WAVE32: S_ENDPGM 0, implicit [[COPY1]]
%1:vgpr(s32) = COPY $vgpr0 %1:vgpr(s32) = COPY $vgpr0
%0:vgpr(s1) = G_TRUNC %1(s32) %0:vgpr(s1) = G_TRUNC %1(s32)
%sgpr0:sgpr(s32) = COPY $sgpr0 %sgpr0:sgpr(s32) = COPY $sgpr0
%2:sgpr(s1) = G_TRUNC %sgpr0 %2:sgpr(s1) = G_TRUNC %sgpr0
%6:sgpr(s32) = G_CONSTANT i32 0 %6:sgpr(s32) = G_CONSTANT i32 0
%7:sgpr(p1) = G_IMPLICIT_DEF %7:sgpr(p1) = G_IMPLICIT_DEF
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bb.0: bb.0:
liveins: $vgpr0, $sgpr0 liveins: $vgpr0, $sgpr0
; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave64 ; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave64
; WAVE64: liveins: $vgpr0, $sgpr0 ; WAVE64: liveins: $vgpr0, $sgpr0
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: %sgpr0:sreg_32 = COPY $sgpr0 ; WAVE64: %sgpr0:sreg_32 = COPY $sgpr0
; WAVE64: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec ; WAVE64: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec ; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def $scc ; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def $scc
; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec ; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
; WAVE64: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc ; WAVE64: [[S_XOR_B64_:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
; WAVE64: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[S_XOR_B64_]] ; WAVE64: S_ENDPGM 0, implicit [[S_XOR_B64_]]
; WAVE64: S_ENDPGM 0, implicit [[COPY1]]
; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave64 ; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave64
; WAVE32: liveins: $vgpr0, $sgpr0 ; WAVE32: liveins: $vgpr0, $sgpr0
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: %sgpr0:sreg_32 = COPY $sgpr0 ; WAVE32: %sgpr0:sreg_32 = COPY $sgpr0
; WAVE32: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec ; WAVE32: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec ; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def $scc ; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def $scc
; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec ; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_XOR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc ; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_XOR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
; WAVE32: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[S_XOR_B32_]] ; WAVE32: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[S_XOR_B32_]]
; WAVE32: S_ENDPGM 0, implicit [[COPY1]] ; WAVE32: S_ENDPGM 0, implicit [[COPY1]]
%1:vgpr(s32) = COPY $vgpr0 %1:vgpr(s32) = COPY $vgpr0
%0:vgpr(s1) = G_TRUNC %1(s32) %0:vgpr(s1) = G_TRUNC %1(s32)
%sgpr0:sgpr(s32) = COPY $sgpr0 %sgpr0:sgpr(s32) = COPY $sgpr0
%2:sgpr(s1) = G_TRUNC %sgpr0 %2:sgpr(s1) = G_TRUNC %sgpr0
%6:sgpr(s32) = G_CONSTANT i32 0 %6:sgpr(s32) = G_CONSTANT i32 0
%7:sgpr(p1) = G_IMPLICIT_DEF %7:sgpr(p1) = G_IMPLICIT_DEF
%9:vcc(s1) = COPY %0(s1) %9:vcc(s1) = COPY %0(s1)
%10:vcc(s1) = COPY %2(s1) %10:vcc(s1) = COPY %2(s1)
%8:vcc(s1) = G_XOR %9, %10 %8:vcc(s1) = G_XOR %9, %10
%3:sreg_64_xexec(s1) = COPY %8(s1) %3:sreg_64_xexec(s1) = COPY %8(s1)
S_ENDPGM 0, implicit %3 S_ENDPGM 0, implicit %3
... ...