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[TableGen] Allow targets to entirely ignore Psets for registers
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Authored by cdevadas on Sep 22 2021, 10:24 PM.

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Summary

Tablegen currently expects targets to have at least one
pressure set for every broader register category. AMDGPU's
VGPR or AGPR, for instance, seemed to work correctly without
any pset, though we have forced one for each type to avoid
the assertion in computeRegUnitSets.
However, psets can not be entirely empty. At least one
set is mandatory for every target. This patch bypasses
the assertion for the classes when GeneratePressureSet is zero
while ensuring the RegUnitSets are not empty.

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Event Timeline

cdevadas created this revision.Sep 22 2021, 10:24 PM
cdevadas requested review of this revision.Sep 22 2021, 10:24 PM
Herald added a project: Restricted Project. · View Herald TranscriptSep 22 2021, 10:24 PM

LGTM, but needs tablegen test.

cdevadas updated this revision to Diff 374545.Sep 23 2021, 8:03 AM
cdevadas edited the summary of this revision. (Show Details)

Since we liberate the psets for registers now, there is a possibility that targets might skip them entirely.
That shouldn't happen. Added a fatal error to ensure that at least one Pset is generated for the target.
Also, included relevant tests.

arsenm accepted this revision.Sep 23 2021, 9:26 AM
This revision is now accepted and ready to land.Sep 23 2021, 9:26 AM
This revision was landed with ongoing or failed builds.Sep 23 2021, 8:09 PM
This revision was automatically updated to reflect the committed changes.