[WebAssembly] Add prototype relaxed float min max instructions

[ngzhian]

Summary

Add relaxed. f32x4.min, f32x4.max, f64x2.min, f64x2.max. These are only
exposed as builtins, and require user opt-in.

[tlively]

LGTM!

clang/include/clang/Basic/BuiltinsWebAssembly.def

 
 TARGET_BUILTIN(__builtin_wasm_laneselect_i8x16, "V16ScV16ScV16ScV16Sc", "nc", "relaxed-simd")
 TARGET_BUILTIN(__builtin_wasm_laneselect_i16x8, "V8sV8sV8sV8s", "nc", "relaxed-simd")
 TARGET_BUILTIN(__builtin_wasm_laneselect_i32x4, "V4iV4iV4iV4i", "nc", "relaxed-simd")
 TARGET_BUILTIN(__builtin_wasm_laneselect_i64x2, "V2LLiV2LLiV2LLiV2LLi", "nc", "relaxed-simd")
 
 TARGET_BUILTIN(__builtin_wasm_relaxed_swizzle_i8x16, "V16ScV16ScV16Sc", "nc", "relaxed-simd")
 
+TARGET_BUILTIN(__builtin_wasm_relaxed_min_f32x4, "V4fV4fV4f", "nc", "relaxed-simd")
+TARGET_BUILTIN(__builtin_wasm_relaxed_max_f32x4, "V4fV4fV4f", "nc", "relaxed-simd")
+TARGET_BUILTIN(__builtin_wasm_relaxed_min_f64x2, "V2dV2dV2d", "nc", "relaxed-simd")
+TARGET_BUILTIN(__builtin_wasm_relaxed_max_f64x2, "V2dV2dV2d", "nc", "relaxed-simd")
+
 #undef BUILTIN
 #undef TARGET_BUILTIN

clang/lib/CodeGen/CGBuiltin.cpp

case WebAssembly::BI__builtin_wasm_laneselect_i64x2: {
     return Builder.CreateCall(Callee, {A, B, C});
   }
   case WebAssembly::BI__builtin_wasm_relaxed_swizzle_i8x16: {
     Value *Src = EmitScalarExpr(E->getArg(0));
     Value *Indices = EmitScalarExpr(E->getArg(1));
     Function *Callee = CGM.getIntrinsic(Intrinsic::wasm_relaxed_swizzle);
     return Builder.CreateCall(Callee, {Src, Indices});
   }
+  case WebAssembly::BI__builtin_wasm_relaxed_min_f32x4:
+  case WebAssembly::BI__builtin_wasm_relaxed_max_f32x4:
+  case WebAssembly::BI__builtin_wasm_relaxed_min_f64x2:
+  case WebAssembly::BI__builtin_wasm_relaxed_max_f64x2: {
+    Value *LHS = EmitScalarExpr(E->getArg(0));
+    Value *RHS = EmitScalarExpr(E->getArg(1));
+    unsigned IntNo;
+    switch (BuiltinID) {
+    case WebAssembly::BI__builtin_wasm_relaxed_min_f32x4:
+    case WebAssembly::BI__builtin_wasm_relaxed_min_f64x2:
+      IntNo = Intrinsic::wasm_relaxed_min;
+      break;
+    case WebAssembly::BI__builtin_wasm_relaxed_max_f32x4:
+    case WebAssembly::BI__builtin_wasm_relaxed_max_f64x2:
+      IntNo = Intrinsic::wasm_relaxed_max;
+      break;
+    default:
+      llvm_unreachable("unexpected builtin ID");
+    }
+    Function *Callee = CGM.getIntrinsic(IntNo, LHS->getType());
+    return Builder.CreateCall(Callee, {LHS, RHS});
+  }
   default:
     return nullptr;
   }
 }
 
 static std::pair<Intrinsic::ID, unsigned>
 getIntrinsicForHexagonNonGCCBuiltin(unsigned BuiltinID) {
   struct Info {

clang/test/CodeGen/builtins-wasm.c

i64x2 laneselect_i64x2(i64x2 a, i64x2 b, i64x2 c) {
   // WEBASSEMBLY-SAME: <2 x i64> %a, <2 x i64> %b, <2 x i64> %c)
   // WEBASSEMBLY-NEXT: ret
 }
 
 i8x16 relaxed_swizzle_i8x16(i8x16 x, i8x16 y) {
   return __builtin_wasm_relaxed_swizzle_i8x16(x, y);
   // WEBASSEMBLY: call <16 x i8> @llvm.wasm.relaxed.swizzle(<16 x i8> %x, <16 x i8> %y)
 }
+
+f32x4 relaxed_min_f32x4(f32x4 a, f32x4 b) {
+  return __builtin_wasm_relaxed_min_f32x4(a, b);
+  // WEBASSEMBLY: call <4 x float> @llvm.wasm.relaxed.min.v4f32(
+  // WEBASSEMBLY-SAME: <4 x float> %a, <4 x float> %b)
+  // WEBASSEMBLY-NEXT: ret
+}
+
+f32x4 relaxed_max_f32x4(f32x4 a, f32x4 b) {
+  return __builtin_wasm_relaxed_max_f32x4(a, b);
+  // WEBASSEMBLY: call <4 x float> @llvm.wasm.relaxed.max.v4f32(
+  // WEBASSEMBLY-SAME: <4 x float> %a, <4 x float> %b)
+  // WEBASSEMBLY-NEXT: ret
+}
+
+f64x2 relaxed_min_f64x2(f64x2 a, f64x2 b) {
+  return __builtin_wasm_relaxed_min_f64x2(a, b);
+  // WEBASSEMBLY: call <2 x double> @llvm.wasm.relaxed.min.v2f64(
+  // WEBASSEMBLY-SAME: <2 x double> %a, <2 x double> %b)
+  // WEBASSEMBLY-NEXT: ret
+}
+
+f64x2 relaxed_max_f64x2(f64x2 a, f64x2 b) {
+  return __builtin_wasm_relaxed_max_f64x2(a, b);
+  // WEBASSEMBLY: call <2 x double> @llvm.wasm.relaxed.max.v2f64(
+  // WEBASSEMBLY-SAME: <2 x double> %a, <2 x double> %b)
+  // WEBASSEMBLY-NEXT: ret
+}

llvm/include/llvm/IR/IntrinsicsWebAssembly.td

Intrinsic<[llvm_anyvector_ty],
             [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
             [IntrNoMem, IntrSpeculatable]>;
 
 def int_wasm_relaxed_swizzle :
   Intrinsic<[llvm_v16i8_ty],
             [llvm_v16i8_ty, llvm_v16i8_ty],
             [IntrNoMem, IntrSpeculatable]>;
 
+def int_wasm_relaxed_min :
+  Intrinsic<[llvm_anyvector_ty],
+            [LLVMMatchType<0>, LLVMMatchType<0>],
+            [IntrNoMem, IntrSpeculatable]>;
+def int_wasm_relaxed_max :
+  Intrinsic<[llvm_anyvector_ty],
+            [LLVMMatchType<0>, LLVMMatchType<0>],
+            [IntrNoMem, IntrSpeculatable]>;
+
 //===----------------------------------------------------------------------===//
 // Thread-local storage intrinsics
 //===----------------------------------------------------------------------===//
 
 def int_wasm_tls_size :
   Intrinsic<[llvm_anyint_ty],
             [],
             [IntrNoMem, IntrSpeculatable]>;

llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

 // Relaxed swizzle
 //===----------------------------------------------------------------------===//
 
 defm RELAXED_SWIZZLE :
   RELAXED_I<(outs V128:$dst), (ins V128:$src, V128:$mask), (outs), (ins),
          [(set (v16i8 V128:$dst),
            (int_wasm_relaxed_swizzle (v16i8 V128:$src), (v16i8 V128:$mask)))],
          "i8x16.relaxed_swizzle\t$dst, $src, $mask", "i8x16.relaxed_swizzle", 162>;
+
+//===----------------------------------------------------------------------===//
+// Relaxed floating-point min and max.
+//===----------------------------------------------------------------------===//
+
+multiclass SIMD_RELAXED_FMINMAX<Vec vec, bits<32> simdopMin, bits<32> simdopMax> {
+  defm RELAXED_FMIN_#vec :
+    RELAXED_I<(outs V128:$dst), (ins V128:$a, V128:$b), (outs), (ins),
+              [(set (vec.vt V128:$dst), (int_wasm_relaxed_min
+                (vec.vt V128:$a), (vec.vt V128:$b)))],
+              vec.prefix#".relaxed_min\t$dst, $a, $b", vec.prefix#".relaxed_min", simdopMin>;
+  defm RELAXED_FMAX_#vec :
+    RELAXED_I<(outs V128:$dst), (ins V128:$a, V128:$b), (outs), (ins),
+              [(set (vec.vt V128:$dst), (int_wasm_relaxed_max
+                (vec.vt V128:$a), (vec.vt V128:$b)))],
+              vec.prefix#".relaxed_max\t$dst, $a, $b", vec.prefix#".relaxed_max", simdopMax>;
+}
+
+defm "" : SIMD_RELAXED_FMINMAX<F32x4, 0xb4, 0xe2>;
+defm "" : SIMD_RELAXED_FMINMAX<F64x2, 0xd4, 0xee>;

llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll

 declare <4 x float> @llvm.wasm.fms.v4f32(<4 x float>, <4 x float>, <4 x float>)
 define <4 x float> @fms_v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) {
   %v = call <4 x float> @llvm.wasm.fms.v4f32(
     <4 x float> %a, <4 x float> %b, <4 x float> %c
   )
   ret <4 x float> %v
 }
 
+; CHECK-LABEL: relaxed_min_v4f32:
+; CHECK-NEXT: .functype relaxed_min_v4f32 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: f32x4.relaxed_min $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
+declare <4 x float> @llvm.wasm.relaxed.min.v4f32(<4 x float>, <4 x float>)
+define <4 x float> @relaxed_min_v4f32(<4 x float> %a, <4 x float> %b) {
+  %v = call <4 x float> @llvm.wasm.relaxed.min.v4f32(
+    <4 x float> %a, <4 x float> %b
+  )
+  ret <4 x float> %v
+}
+
+; CHECK-LABEL: relaxed_max_v4f32:
+; CHECK-NEXT: .functype relaxed_max_v4f32 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: f32x4.relaxed_max $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
+declare <4 x float> @llvm.wasm.relaxed.max.v4f32(<4 x float>, <4 x float>)
+define <4 x float> @relaxed_max_v4f32(<4 x float> %a, <4 x float> %b) {
+  %v = call <4 x float> @llvm.wasm.relaxed.max.v4f32(
+    <4 x float> %a, <4 x float> %b
+  )
+  ret <4 x float> %v
+}
+
 ; ==============================================================================
 ; 2 x f64
 ; ==============================================================================
 ; CHECK-LABEL: bitselect_v2f64:
 ; CHECK-NEXT: .functype bitselect_v2f64 (v128, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x double> @llvm.wasm.bitselect.v2f64(<2 x double>, <2 x double>, <2 x double>)

 ; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x double> @llvm.wasm.fms.v2f64(<2 x double>, <2 x double>, <2 x double>)
 define <2 x double> @fms_v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c) {
   %v = call <2 x double> @llvm.wasm.fms.v2f64(
     <2 x double> %a, <2 x double> %b, <2 x double> %c
   )
   ret <2 x double> %v
 }
+
+; CHECK-LABEL: relaxed_min_v2f64:
+; CHECK-NEXT: .functype relaxed_min_v2f64 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: f64x2.relaxed_min $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
+declare <2 x double> @llvm.wasm.relaxed.min.v2f64(<2 x double>, <2 x double>)
+define <2 x double> @relaxed_min_v2f64(<2 x double> %a, <2 x double> %b) {
+  %v = call <2 x double> @llvm.wasm.relaxed.min.v2f64(
+    <2 x double> %a, <2 x double> %b
+  )
+  ret <2 x double> %v
+}
+
+; CHECK-LABEL: relaxed_max_v2f64:
+; CHECK-NEXT: .functype relaxed_max_v2f64 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: f64x2.relaxed_max $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
+declare <2 x double> @llvm.wasm.relaxed.max.v2f64(<2 x double>, <2 x double>)
+define <2 x double> @relaxed_max_v2f64(<2 x double> %a, <2 x double> %b) {
+  %v = call <2 x double> @llvm.wasm.relaxed.max.v2f64(
+    <2 x double> %a, <2 x double> %b
+  )
+  ret <2 x double> %v
+}

llvm/test/MC/WebAssembly/simd-encodings.s

main:
     i32x4.laneselect
 
     # CHECK: i64x2.laneselect # encoding: [0xfd,0xd3,0x01]
     i64x2.laneselect
 
     # CHECK: i8x16.relaxed_swizzle # encoding: [0xfd,0xa2,0x01]
     i8x16.relaxed_swizzle
 
+    # CHECK: f32x4.relaxed_min # encoding: [0xfd,0xb4,0x01]
+    f32x4.relaxed_min
+
+    # CHECK: f32x4.relaxed_max # encoding: [0xfd,0xe2,0x01]
+    f32x4.relaxed_max
+
+    # CHECK: f64x2.relaxed_min # encoding: [0xfd,0xd4,0x01]
+    f64x2.relaxed_min
+
+    # CHECK: f64x2.relaxed_max # encoding: [0xfd,0xee,0x01]
+    f64x2.relaxed_max
+
     end_function